23results about "Transversal filters" patented technology

An electronic decoder for decoding of block coded wireless communications signals. The electronic decoder comprises at least two electrically interconnected analogue crossbar arrays (1110, 1120) of memristors. An electrical interconnection (1115) between a column (1111) of an analogue crossbar array of the at least two electrically 5 interconnected analogue crossbar arrays (1110, 1120) and a row (1121) of a following analogue crossbar array of the at least two electrically interconnected analogue crossbar arrays (1110, 1120) comprises a current-to-voltage converter (1101). A first analogue crossbar array (1110) of the at least two analogue crossbar arrays (1110, 1120) comprises at least a first row of memristors (1112a) with a single input and a 10 respective output for each column of memristors.

An adaptive electronic filter (200) comprising a memristive-based filter circuit (201) for filtering an electrical input signal to obtain a filtered electrical signal. The adaptive electronic filter (200) further comprises a memristive-based subtractor circuit (202) for obtaining an error signal based on the filtered electrical signal and a reference signal and an error minimization circuit (203) configured to provide adapted filter coefficients of the memristive-based filter circuit (201) based on the error signal to minimize the error signal.

An electronic filter (200a) for band stop or band pass filtering of an electrical input signal. The electronic filter (200a) comprises a memristive low-pass filter (210) comprising a first crossbar array of memristors (211, 212). Each memristor (211, 212) of the first crossbar array is configured to represent a respective filter coefficient of a low-pass filter implemented as a filter matrix. The electronic filter (200a) further comprises a memristive high-pass filter (220) comprising a second crossbar array of memristors (221, 222). Each memristor of the second crossbar array is configured to represent a respective filter coefficient of a high-pass filter function implemented as a filter matrix.

An analog filter, comprising, a first-time encoding machine (TEM); and a first delay element.

Enhanced Bucket Brigade Delay (BBD) circuits which more readily support cascaded configurations. A gain control mechanism is utilized in combination with an attenuation coupling network between subsequent BBD stages to achieve significantly longer delays than are achievable by the single BBD device, without introducing excessive noise or increased power dissipation associated with the need of reconstructing and biasing the intermediate signal between BBD devices.

Enhanced Bucket Brigade Delay (BBD) circuits which more readily support cascaded configurations. A gain control mechanism is utilized in combination with an attenuation coupling network between subsequent BBD stages to achieve significantly longer delays than are achievable by the single BBD device, without introducing excessive noise or increased power dissipation associated with the need of reconstructing and biasing the intermediate signal between BBD devices.

This bandpass filter comprises: an input terminal (1) that receives an RF signal as an input; a multi-phase distributor (3) that divides the RF signal input to the input terminal into n RF signals having phases differing by 360 deg / n, where n is a natural number greater than or equal to 1; n signal paths (17-20) that are connected to the multi-phase distributor and each have a sample-and-hold element with two switches, each of the n signal paths sampling and holding one of the n RF signals with phases differing by 360 deg / n from the multi-phase distributor and outputting the held signal; a multi-phase synthesizer (4) that is connected to the n signal paths and synthesizes n signals output from the n signal paths; an output terminal (2) that outputs a signal obtained by the synthesizing by the multi-phase synthesizer; and a clock signal source (21) that outputs a clock signal (S1) that drives all the switches.

An N-tap feedforward equalizer (FFE) (100) includes: a group of N FFE taps coupled together in parallel; a filter (140) coupled between the (N-1)th FFE tap and the Nth FFE tap; and an adder coupled to the output of the group of N FFE taps. Each FFE tap includes a unique sample and hold (S / H) circuit (120, 130, 150) that generates a unique time-delay signal and a unique transconductance stage (125, 135, 155) that generates a unique transconductance output based on the unique time-delay signal. The filter causes the N-tap FFE to have characteristics greater than N taps. In some instances, the filter is a first-order high-pass filter that causes coefficients greater than N to have opposite polarity to the Nth coefficient. In some instances, the filter is a first-order low-pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.

In at least one embodiment, a system comprising a first circuit and a second circuit is provided. The first circuit includes a first filter filtering a first input signal and generating a first filtered output signal. The first circuit includes a first comparator comparing the first filtered output signal to a first threshold value and providing a first output signal indicative of a failure condition to one or more first processors. The second circuit includes a second filter filtering the first input signal and generating a second filtered output signal to filter the first input signal in less time than the first filter filtering the first input signal. The second circuit includes a second comparator comparing the second filtered output signal to a second threshold value and providing a second output signal indicative of the failure condition to one or more second processors.

Linear time-invariant (LTI) filters are a staple of modern signal processing. LTI filters perform many operations including signal estimation, bandpass / stopband selection, encoding / decoding, modulation / demodulation, etc. Most modem LTI filters operate in the digital domain due to the flexibility of programming digital processors. However, this means that the incoming signal must be digitized. This introduces the signals to the bottlenecks and latency of digital computing, where digital electronics cannot process the increasing high data-rate and high-bandwidth data in dense spectral environments in real-time. The programmable analog LTI (PA-LTI) architecture is a hardware accelerator that performs real-time LTI operations in the analog domain and is fully programmable, enabling unprecedented acceleration of front-end PHY layer communications processing. Conventional analog LTI processors, such as RLC circuits or amplifiers, can perform only one LTI function. A PA-LTI processor can be digitally programmed to implement any arbitrary finite impulse response (FIR) LTI operation in the analog domain.

Described herein are circuits and systems with fixed impedances (e.g., arranged in an array) that, in accordance with certain embodiments, may be programmable for performing multiplication or similar functions. Some embodiments of the present disclosure provide an integrated circuit with an array of fixed impedances coupled to and between conductive portions of respective layers of the integrated circuit, at least some of the fixed impedances having different fixed impedance values. Some embodiments of the present disclosure provide an integrated circuit with an array of fixed impedances coupled to and between an input terminal and an output terminal of the integrated circuit, the array having fixed impedance values programmed for multiplying a value of an input signal received at the input terminal to produce an output at the output terminal. Embodiments of the present disclosure may be produced at high scale, efficiently, and reliably by leveraging existing integrated circuit technologies.

Described herein are circuits and systems with fixed impedances (e.g., arranged in an array) that, in accordance with certain embodiments, may be programmable for performing multiplication or similar functions. Some embodiments of the present disclosure provide an integrated circuit with an array of fixed impedances coupled to and between conductive portions of respective layers of the integrated circuit, at least some of the fixed impedances having different fixed impedance values. Some embodiments of the present disclosure provide an integrated circuit with an array of fixed impedances coupled to and between an input terminal and an output terminal of the integrated circuit, the array having fixed impedance values programmed for multiplying a value of an input signal received at the input terminal to produce an output at the output terminal. Embodiments of the present disclosure may be produced at high scale, efficiently, and reliably by leveraging existing integrated circuit technologies.

In at least one embodiment, a system comprising a first circuit and a second circuit is provided. The first circuit includes a first filter filtering a first input signal and generating a first filtered output signal. The first circuit includes a first comparator comparing the first filtered output signal to a first threshold value and providing a first output signal indicative of a failure condition to one or more first processors. The second circuit includes a second filter filtering the first input signal and generating a second filtered output signal to filter the first input signal in less time than the first filter filtering the first input signal. The second circuit includes a second comparator comparing the second filtered output signal to a second threshold value and providing a second output signal indicative of the failure condition to one or more second processors.

An apparatus, including: a switched capacitor filter; and an analog-to-digital converter including an input coupled to the switched capacitor filter. A method, includes: operating a switched capacitor filter to filter an input analog signal to generate an output analog signal; and converting the output analog signal into a digital signal.

An electric filtering circuitry for filtering ripples of an input signal, includes an input terminal for applying the input signal, an output terminal to provide an output signal, and a forward path including a clocked integrator circuit and a clocked sample-and-hold or track-and-hold circuit. The electric filtering circuitry also includes a summing node that receives the input signal and the output signal, and provides a difference signal. The clocked integrator circuit has an input side connected to the summing node to receive the difference signal, and an output side to provide an integrator output signal. The clocked sample-and-hold or track-and-hold circuit has an input side to receive the integrator output signal, and an output side to provide a sample-and-hold or track-and-hold output signal. The output side of the sample-and-hold or track-and-hold circuit is coupled to the output terminal. A feedback path is between the output terminal and the summing node.

This bandpass filter comprises: an input terminal (1) that receives an RF signal as an input; a multi-phase distributor (3) that divides the RF signal input to the input terminal into n RF signals having phases differing by 360 deg / n, where n is a natural number greater than or equal to 1; n signal paths (17-20) that are connected to the multi-phase distributor and each have a sample-and-hold element with two switches, each of the n signal paths sampling and holding one of the n RF signals with phases differing by 360 deg / n from the multi-phase distributor and outputting the held signal; a multi-phase synthesizer (4) that is connected to the n signal paths and synthesizes n signals output from the n signal paths; an output terminal (2) that outputs a signal obtained by the synthesizing by the multi-phase synthesizer; and a clock signal source (21) that outputs a clock signal (S1) that drives all the switches.

The invention relates to an apparatus for providing parallel filtering. In at least one embodiment, a system is provided that includes a first circuit and a second circuit. The first circuit includes a first filter that filters a first input signal and generates a first filtered output signal. The first circuit includes a first comparator that compares the first filtered output signal to a first threshold and provides a first output signal indicative of a fault condition to one or more first processors. The second circuit includes a second filter that filters the first input signal and generates a second filtered output signal to filter the first input signal for a shorter time than the first filter filters the first input signal. The second circuit includes a second comparator that compares the second filtered output signal to a second threshold and provides a second output signal indicative of the fault condition to one or more second processors.

A baseband signal processor (400) for wireless communications signals. The baseband signal processor (400) comprises an analog channel select filter (401) for filtering the wireless communications signals. The analog channel select filter (401) comprises an analog crossbar array of memristors. Each memristor of the analog crossbar array is configured to represent a respective filter coefficient of a filter function implemented as a filter matrix.

Analog FIR filter. An FIR filter (15) includes an input terminal for receiving an input signal, a first filter circuit including: a first transconductance device (30a) configured to generate a first current signal (i1) proportional to the input signal; a first analog switch (41a) commutated in n by a first digital gate signal (φ1) and configured to block the current signal when the first digital gate signal has a first value and to transmit the current signal to a first integrating capacitor (45a) when the first digital gate signal has a second value; characterized in that the first digital gate signal (φ1) includes a periodic series of pulses, wherein the pulses have a width proportional to the filter coefficients.

An analog filter, comprising, a first-time encoding machine (TEM); and a first delay element.

An electronic device includes a first resonator electrode and a second resonator electrode in an interconnect stack over a semiconductor substrate. The first resonator electrode includes a first lower resonator electrode, a first upper resonator electrode and a first plurality of vias between the first lower resonator electrode and the first upper resonator electrode. The second resonator electrode includes a second lower resonator electrode, a second upper resonator electrode, and a second plurality of vias between the second lower resonator electrode and the second upper resonator electrode. A cavity in the interconnect stack is bounded by the first resonator electrode and the second resonator electrode. An electron emitter extends from the semiconductor surface between the first and second resonator electrodes and is configured to direct electrons into the cavity. The electronic device may be operated to produce short wavelength radiation, e.g. x-rays.

A filtering device including a transmission line between an input and an output and a resonator, wherein a first microstrip track, a first micro-electromechanical system (MEMS) component, and a second microstrip track are connected in series between the transmission line and a ground point, and a second MEMS component is connected in parallel with the second microstrip track, the first and second MEMS components being switchable and being controlled by a circuit controlling the open or closed state of each of the first and second MEMS components, allowing the filtering device to be placed either in an all-pass operating mode or in a band-stop operating mode about a characteristic frequency of the resonator.

In at least one embodiment, a system comprising a first circuit and a second circuit is provided. The first circuit includes a first filter that filters a first input signal and generates a first filtered output signal. The first circuit includes a first comparator that compares the first filtered output signal to a first threshold and provides a first output signal indicative of an error condition to one or more first processors. The second circuit includes a second filter that filters the first input signal and generates a second filtered output signal, filtering the first input signal in a shorter time than the first filter requires to filter the first input signal.The second circuit includes a second comparator that compares the second filtered output signal to a second threshold and provides a second output signal indicative of the error condition to one or more second processors.