1134 results about "Differential circuits" patented technology

A high-speed I / O driver includes circuitry that is configurable to meet single-ended and differential I / O signal standards. For one embodiment, the driver includes four input circuits that can be configured to implement two CMOS inverters to process single-ended signals or configured to implement a differential circuit to process differential signals.

A DC-DC flyback converter, includes a three-winding transformer; a primary power circuit having a first MOSFET connected to a first winding of the transformer; a secondary power circuit connected to a second winding of the transformer terminals; and a self-driven circuit connected to a third winding of the transformer. The secondary power circuit includes a synchronous rectifier in the form of a second MOSFET and the self-driven circuit further includes a delay drive circuit, an isolation differential circuit, a negative removal circuit having a third MOSFET and a synchronous rectifier trigger switch-off circuit for switching the synchronous rectifier to an off condition.

A differential circuit and an amplifier circuit for reducing an amplitude difference deviation, performing a full-range drive, and consuming less power are disclosed. The circuit includes a first pair of p-type transistors and a second pair of n-type transistors. A first current source and a first switch are connected in parallel between the sources of the first pair of transistors, which are tied together, and a power supply VDD. A second current source and a second switch are connected in parallel between the sources of the second pair of transistors, which are tied together, and a power supply VSS. The circuit further includes connection changeover means that performs the changeover of first and second pairs between a differential pair that receives differential input voltages and a current mirror pair that is the load of the differential pair. When one of the two pairs is the differential pair, the other is the current mirror pair. In a differential amplifier circuit, there is provided an added transistor connected in parallel to a transistor, which is one transistor of a differential pair transistors, whose control terminal is a non-inverting input terminal. The added transistor has a control terminal for receiving a control voltage which is set so that, when an input voltage applied to the non-inverting input terminal is in a range in which the transistor whose control terminal is the non-inverting input terminal is turned off, the added transistor is turned on.

The invention provides a driving circuit and a driving method applied to a flyback-type converter and a quasi-resonant soft-switching flyback-type converter applying the same. According to a driving circuit applied to the flyback-type converter, differential coefficient of the drain-source voltage of a main power switch tube in the flyback-type converter is worked out by a differential circuit, thus leading the time when the drain-source voltage achieves valley floor to correspond to the time when the differential voltage passes the zero point in positive direction. A valley floor voltage detecting circuit is connected with the differential circuit and receives a differential voltage signal; when the drain-source voltage of the main power switch tube achieves the valley floor, a valley floor control signal is output, thus controlling the driving circuit to drive the main power switch tube, and further exactly realizing the aim of conducting the valley floor of the main power switch tube. By adopting the driving circuit, the aim of controlling a quasi-resonant soft switch of the main power switch tube is realized precisely, the driving circuit of the flyback-type converter is optimized so that the controlling effect and the reliability are greatly improved, and the realizing cost is reduced.

A clock and data recovery circuit (CDR) for receiving high-speed digital data, and having an analog phase offset control capability, is improved by providing an adaptive sampling edge position control. A differential circuit samples the raw data signal at three closely spaced sampling points of the eye, and compares advanced and delayed sampled data with the nominal sampled data. If either the advanced or delayed sampled data differ from the nominal sampled data, i.e. if advanced or delayed errors are detected, a shift in the sampling edge position may be required. A logic circuit performs a method determining the occurrence of advanced or delayed errors over progressively longer time intervals, and to adjust the sampling edge position of the CDR by controlling the phase offset.

Disclosed herein is a solid-state image pickup device including: a pixel array portion; a dummy pixel; a differential circuit; a reset voltage supplying section; and a common phase feedback circuit.

A sensor for detecting a substance in liquid includes a sensing circuit including a sensing surface acoustic wave (SAW) element in which a reaction film to react with a substance in liquid, a reference circuit including a reference SAW element including an IDT and not including a reaction film, a first signal source driving the sensing circuit, a second signal source driving the reference circuit and being independent of the first signal source, and a differential circuit arranged to output a differential output between an output of the sensing circuit and an output of the reference circuit. The frequency of a first frequency signal output from the first signal source is different from the frequency of a second frequency signal output from the second signal source, thereby making a driving frequency for the sensing SAW element and a driving frequency for the reference SAW element substantially the same as or different from one another.

An output buffer circuit drives multiple signal formats. The output buffer circuit reduces duplication of output bond pads on an integrated circuit die. The output buffer circuit reduces a need for including conversion buffers on system boards. A single integrated circuit including the output buffer circuit may meet a variety of applications. The output buffer achieves these results with a programmable output voltage swing and a programmable output common mode voltage. In some embodiments of the present invention, an integrated circuit includes at least one single-ended buffer and at least one differential circuit coupled to a pair of outputs. One of the single-ended buffer and the differential circuit is selectively enabled to provide a signal to the outputs.

A DC-DC flyback converter, includes a three-winding transformer; a primary power circuit having a first MOSFET connected to a first winding of the transformer; a secondary power circuit connected to a second winding of the transformer terminals; and a self-driven circuit connected to a third winding of the transformer. The secondary power circuit includes a synchronous rectifier in the form of a second MOSFET and the self-driven circuit further includes a delay drive circuit, an isolation differential circuit, a negative removal circuit having a third MOSFET and a synchronous rectifier trigger switch-off circuit for switching the synchronous rectifier to an off condition.

An image sensing apparatus has a plurality of pixels arranged two dimensionally, each pixel containing a photoelectric converter that outputs a photoelectrically converted signal in response to a quantity of received light, an output unit containing a clamping circuit, a signal supply circuit that outputs a reference signal to the clamping circuit, a control unit that controls to clamp the reference signal prior to outputting the photoelectrically converted signal from the pixel to the clamping circuit, output the photoelectrically converted signal to the clamping circuit, and then output a noise signal from the pixel to the clamping circuit, and a differential circuit that subtracts the noise signal from the photoelectrically converted signal processed by the clamping circuit.

A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product generation can be inhibited or at least reduced to acceptable levels. The mismatch correction circuit receives a digital offset signal, and generates one or more voltage signals to be selectively applied to the signal paths of the passive differential mixer circuit. The voltage signals can be adjusted back gate bias voltages applied to the bulk terminals of selected transistors to adjust their threshold voltages, or the voltage signals can be adjusted common mode voltages applied directly to a selected signal path. Since the differential mixer circuit is passive, no DC current contribution to noise is generated. The switching transistors of the mixer circuit can be maintained at minimal dimensions to reduce switching signal drive loading, resulting in lower power consumption and higher operating frequencies than if larger switching transistors were used.

There is provided a D-type flip-flop circuit which is improved in terms of operating frequency. First and second current supplying circuits are provided as sources for supplying currents to first and third differential circuits for inputting data and to second and fourth differential circuits for holding data in a master circuit and a slave circuit. Further, timing for supplying the currents to the respective differential circuits for inputting and holding data are controlled by first and second clock signals, respectively. The D-type flip-flop circuit is improved in terms of operating frequency by optimizing timing for writing input data and timing for holding data by arranging the first clock signal so as to have a certain delay with respect to the second clock signal. Further, the D-type flip-flop circuit is improved with respect to the operating frequency also by optimizing the value of the currents supplied to the respective differential circuits.

A comparator with an offset canceling function and a D / A conversion apparatus capable of canceling an input / output offset with high accuracy using this comparator. To eliminate unbalance between right and left currents of the differential circuit making up the comparator, the phase of a single end output signal of the differential circuit is inverted and the inverted signal is fed back to one substrate of the differential pair MOS transistors as a substrate bias. Threshold voltages of the MOS transistors are changed and the current capacities of the transistors are adjusted in this way.

A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product generation can be inhibited or at least reduced to acceptable levels. The mismatch correction circuit receives a digital offset signal, and generates one or more voltage signals to be selectively applied to the signal paths of the passive differential mixer circuit. The voltage signals can be adjusted back gate bias voltages applied to the bulk terminals of selected transistors to adjust their threshold voltages, or the voltage signals can be adjusted common mode voltages applied directly to a selected signal path. Since the differential mixer circuit is passive, no DC current contribution to noise is generated. The switching transistors of the mixer circuit can be maintained at minimal dimensions to reduce switching signal drive loading, resulting in lower power consumption and higher operating frequencies than if larger switching transistors were used.

The invention provides an analog circuit that decreases an effect of variation of a transistor. By flowing a bias current in a comperisation operation, a voltage between the gate and source of the transistor to be compensated is held in a capacitor. In a normal operation, the voltage stored in the compensation operation is added to a signal voltage. As the capacitor holds the voltage according to the characteristics of the transistor to be compensated, the effect of variation can be decreased by adding the voltage stored in the capacitor to the signal voltage. Further, an analog circuit which decreases the effect of variation can be provided by applying the aforementioned basis to a differential circuit, an operational amplifier and the like.

An imaging apparatus includes a pixel that generates charge; an integral amplifier that integrates charge transferred from the pixel; a low pass filter to which output of the integral amplifier is supplied and whose time constant is variable; first and second sample-and-hold circuits that sample and hold output of the low pass filter before and after the charge is transferred from the pixel to the integral amplifier, respectively; a differential circuit that outputs a difference between signals held by the first and second sample-and-hold circuits; and a control circuit that changes the time constant. The control circuit decreases the time constant after the sampling by the first sample-and-hold circuit ends, and increases the time constant in the middle of the sampling by the second sample-and-hold circuit.

The invention relates to a receiving circuit for transmission through interconnections used for sending a plurality of electrical signals.Each of the output signals of the receiving circuit produced by the receiving circuit of the invention is delivered by an output of a combining circuit having 4 inputs and 4 outputs. Each signal terminal of the receiving circuit is connected to a first input terminal of a differential circuit, the differential circuit also having a second input terminal and a single output terminal. The common terminal of the receiving circuit is connected to the second input terminal of each of the differential circuits. Each input of the combining circuit is coupled to the output terminal of one of the differential circuits. Each of the output signals of the receiving circuit is a linear combination of the voltages between one of the signal terminals and the common terminal.

The subject invention provides a photoreceiver / amplifier circuit comprising a differential circuit including a differential transistor pair and a bias circuit; an active load; a feedback resistor for converting a photocurrent generated from a photodiode into a voltage; a reference resistor; and a compensation circuit. The resistance of the feedback resistor is greater than the resistance of the reference resistor. The compensation circuit supplies a compensation current from a junction between the feedback resistor and a non-inverting input terminal of the differential amplifier circuit, so as to cancel the difference between a voltage between terminals of the feedback resistor and a voltage between terminals of the reference resistor. This reduces noise and improves offset voltage characteristics. The present invention provides a photoreceiver / amplifier circuit ensuring noise reduction and desirable offset voltage characteristics.

A light sensing array has a plurality of electrically isolated photosensors, each photosensor having a first terminal and a second terminal, each of the terminals of each photosensor being isolated from the terminals of the other photosensors, wherein each photosensor responds to an incident light level by producing a charge difference between the first and second terminal. There is a differential circuit selectively coupled to the first and second terminals of one of the photosensors for producing an output signal related to the charge difference between the first and second terminals.

The invention discloses a parallel inverter current control method adopting voltage differential compensation, which comprises: adopting a LCL wave filter composed by capacitor and damping resistor in series connection to connect with a PWM inverter and power network; adopting a current transmitter to detect the current in the inductor on the power network side of the wave filter and obtain power network current signal; adopting a piezoelectric sender to detect the capacitor branch voltage of the wave filter and obtain current compensation signal by the RC differential circuit; combining the two signals into one signal as a feedback signal for current control of the inverter; comparing with the control given signal of the power network current to obtain error signal; and adjusting and controlling the output of the PWM inverter by proportional integration, wherein, the transformation ratio of the piezoelectric sender and the RC differential time constant are determined by the LCL wave filter parameter. Compared with conventional current feedback control methods, the invention can reduce the damping resistance of the LCL wave filter, thereby reduce the loss caused by damping resistance and improves the ability of the wave filter for inhibiting the ripple current of the inversion switch.

An output buffer circuit in a multi-power system operating at a high power supply voltage and a low power supply voltage includes a pre-driver, and a main driver. The pre-driver performs a differential switching operation on first and second differential input signals to output first and second differential output signals. The main driver performs a differential switching operation on the DC-eliminated and level-shifted first and second differential output signals to output third and fourth differential output signals. The main driver includes a differential switching circuit including first and second NMOS transistors, and performs a differential switching operation on the DC-eliminated and level-shifted first and second differential output signals to output the third and fourth differential output signals, and an equalizer coupled between source electrodes of the first and second NMOS transistors, and controls a bandwidth of the third and fourth differential output signals.

The present invention provides a differentially driven monolithic inductor circuit having a shield differentially driven by phase shift buffers and a single-ended monolithic inductor circuit having single-ended shields driven by phase shift buffers, both inductor circuit types providing high Quality factor (Q) at operating frequencies in the multi-GHz range and circuits incorporating the same.

A communication device for use on high voltage power lines provides for broadband communications over such high voltage power lines. The device has an impedance matching circuit configured to connect at one end to a high voltage line arrester of the high voltage power line, as well as a limiter circuit coupled to the other end of the impedance matching circuit to limit a voltage associated with a broadband signal. A noise blanker circuit is coupled at one end to this other end of the impedance matching circuit and is configured to inhibit presentation of a time delayed incoming signal to the broadband modem upon detection of electrical noise. The communication device can further comprise link aggregation and / or a differential circuit for providing non-inverted and inverted broadband signals for both reception and transmission. A corresponding method of communicating broadband information over a high voltage power line is disclosed.

An output buffer circuit drives multiple signal formats. The output buffer circuit reduces duplication of output bond pads on an integrated circuit die. The output buffer circuit reduces a need for including conversion buffers on system boards. A single integrated circuit including the output buffer circuit may meet a variety of applications. The output buffer achieves these results with a programmable output voltage swing and a programmable output common mode voltage. In some embodiments of the present invention, an integrated circuit includes at least one single-ended buffer and at least one differential circuit coupled to a pair of outputs. One of the single-ended buffer and the differential circuit is selectively enabled to provide a signal to the outputs.

Disclosed herein is a solid-state image pickup device including: a pixel array portion; a dummy pixel; a differential circuit; a reset voltage supplying section; and a common phase feedback circuit.

There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.

The invention provides a device for generating and controlling standard pressure signals, which is applied to the fields of aviation, aerospace and pressure metering calibration, to be specific, the invention provides a precise pressure control device based on a pair of proportional valves. The device is composed of double sensors, a pair of proportional valves, a constant flow source, a sensor conditioning circuit, a practical differential circuit, a PID control circuit, a high resolution DA converter, a proportional valve driving circuit and serial interfaces. By the device, a pressure can be controlled to a scope ranging from 0 to 1500KPa, the indefinite degree is 0.01% F.S, the control stability is better than 0.002%F.S, and the pressure control process is fast and stable. The device is suitable for pressure control and detection under various environmental conditions.

A silicon on insulator (SOI) CMOS circuit, macro and integrated circuit (IC) chip. The chip or macro may include be an SRAM in partially depleted (PD) SOI CMOS. Most field effect transistors (FETs) do not have body contacts. FETs otherwise exhibiting a sensitivity to history effects have body contacts. The body contact for each such FET is connected to at least one other body contact. A back bias voltage may be provided to selected FETs.

The convertor includes input power source, rectifying tube, follow current tube, first drive circuit for driving the rectifying tube and second drive circuit for driving the follow current tube. The said second drive circuit includes second pulse width modulator, reverse isolation differential circuit, electrical level comparison and energy conversion circuit, auxiliary power supply and complement drive circuit connected in sequence. One end of complement drive circuit is connected to gate electrode of the follow current tube, and the other end is connected to ground. When shut-off signal comes, high electrical level output by isolation differential circuit is decreased quickly, and electrical level comparison and energy conversion circuit turns on quickly. The complement drive circuit makes electric charge on grid electrode of synchronous follow current MOS discharge quickly, and makes MOS transistor cut off. Thus, shutting down convertor does not generate negative voltage.

The invention discloses a particle counting system of a micro-fluidic chip based on an electric resistance technology. The system comprises a micro-fluidic chip and a signal detection circuit. The micro-fluidic chip comprises a glass substrate, a PDMS substrate and two pairs of metal needles used as electrodes. Normal conductive metal needles are utilized as the electrodes of the micro-fluidic chip to produce an electric field which is across a micro-channel, therefore the preparation process of the micro-fluidic chip is comparatively simple and the production cost is comparatively low. The signal detection circuit comprises two I / V conversion circuit, a differential circuit, an envelope detection circuit, a high-pass filter circuit, a low-pass filter circuit and an amplifying circuit. The resistance signals are detected in the signal detection circuit by utilizing signal differential detection method to ensure precision of signal detection.