36results about "Active element network" patented technology

The invention relates to a full duplex digital isolator. A circuit is provided. The circuit comprises: a first transmitter circuit having a first input terminal arranged to receive first input data and a first node arranged to transmit first intermediate data corresponding to the first input data; a first receiver circuit including a second node arranged to receive the first intermediate data and a first output terminal arranged to generate first output data corresponding to the first input data; comprising a second input terminal and said second node, the second input terminal arranged to receive second input data, the second node further arranged to transmit second intermediate data corresponding to the second input data; and a second receiver circuit comprising a first node and a second output terminal, the first node being further arranged to receive the second intermediate data, and the second output terminal being arranged to generate second output data corresponding to the second input data.

The present disclosure relates to a capacitance multiplier for decoupling capacitors. An integrated circuit can include one or more circuits coupled to a capacitance multiplier circuit. The capacitance multiplier circuit can include a capacitor, fixed and tunable resistors, and a transconductance circuit. The tunable resistor can be adjusted to control the total capacitance of the capacitance multiplier circuit. The transconductance circuit can include a transistor having a drain terminal coupled to a first electrical component and a source terminal coupled to a second electrical component. The first electrical component can be a diode-connected transistor, a direct shorted wire, a resistor, an inductor, or a current source. The second electrical component can be a current source, a direct shorted wire, a resistor, an inductor, or another diode-connected device. Configured in this way, the capacitance multiplier circuit can provide a large adjustable capacitance without voltage drop and without consuming a large amount of power.

A radio-frequency module includes a first switch, a first filter, second filters, a power amplifier, and a low-noise amplifier. The first switch has a first terminal, a second terminal, and a third terminal. The first terminal is coupled to an antenna terminal. The first filter is coupled to the second terminal. The second filters are coupled to the third terminal. The first filter includes a common filter circuit and an additional filter circuit. The additional filter circuit is coupled between the power amplifier and the common filter circuit. The low-noise amplifier is coupled to a path that branches off from a path connecting between the common filter circuit and the additional filter circuit. The common filter circuit is coupled between the additional filter circuit and the first switch.

Aspects of this disclosure relate to hybrid acoustic LC filter with harmonic suppression. The hybrid acoustic LC filter includes a hybrid passive / acoustic and a non-acoustic LC filter cascaded with the hybrid passive / acoustic filter. The hybrid passive / acoustic filter can be configured to filter a radio frequency signal. The hybrid passive / acoustic filter can include acoustic resonators and a non-acoustic passive component. The non-acoustic LC filter can be configured to suppress a harmonic of the radio frequency signal. The non-acoustic LC filter can be a low pass filter or a harmonic notch filter, for example. Related multiplexers, wireless communication devices, and methods are disclosed.

Aspects of this disclosure relate to a multiplexer with a hybrid acoustic passive filter. The multiplexer includes a plurality of filters configured to filter respective radio frequency signals, a shared filter coupled between each of the plurality of filters and a common node, and a radio frequency filter coupled to the common node. At least a first filter of the plurality of filters includes acoustic resonators and a non-acoustic passive component. Related multiplexers, wireless communication devices, and methods are disclosed.

The utility model relates to the technical field of radio frequency microwave communication, and discloses a radio frequency microwave power synthesis device, which comprises an external power supply, an EMC (Electro Magnetic Compatibility) protection module and a power supply management module, the power management module is electrically connected with a signal preprocessing module, a power amplification module, an input coupling and detection module, a frequency selection switch matrix module, a reconfigurable filter network module, a dynamic power adjustment module, a phase matching module, a power synthesis module, an output coupling and detection module and an intelligent control module. According to the utility model, through cooperation of the dynamic power adjustment module, the phase matching module, the power amplification module and the power synthesis module, the power synthesis efficiency of the radio frequency microwave power synthesis device is improved, the power consumption is reduced, and the signal distortion is reduced; and high-efficiency power synthesis in a wide frequency band is realized.

The invention relates to a multiplexer circuit for a battery management system and a corresponding battery management system. A MUX for a battery management system includes first, second, and third input terminals for coupling to first, second, and third, respectively, of a stack. The first, second, and third switches have respective first, second, and third terminals coupled to first, second, and third input terminals, respectively, of the MUX. The AFE and selection circuit includes first, second and third input terminals coupled to second terminals of the first, second and third switches, respectively, first and third output terminals for coupling to positive inputs of the first and second level shifter circuits, and second and fourth output terminals for coupling to negative inputs of the first and second level shifter circuits, respectively. Each of the first, second, third, and fourth output terminals of the AFE and selection circuit is selectively coupleable to any of the first, second, and third input terminals of the AFE and selection circuit.

A circuit. The circuit includes a first transmitter circuit having a first input terminal arranged to receive a first input data and a first node arranged to transmit a first intermediate data corresponding to the first input data, a first receiver circuit including a second node arranged to receive the first intermediate data and a first output terminal arranged to produce a first output data corresponding to the first input data, a second transmitter circuit including a second input terminal arranged to receive a second input data and the second node that is further arranged to transmit a second intermediate data corresponding to the second input data; and a second receiver circuit including the first node and a second output terminal, the first node further arranged to receive the second intermediate data, and the second output terminal arranged to produce a second output data corresponding to the second input data.

Disclosed is a calibration circuit, a calibration method for a filter and a filter device. The calibration circuit includes: a signal receiving terminal, receiving an output signal from the filter; a frequency detection module, obtaining a count value according to the output signal, the count value representing a frequency of the output signal; an adjustment module, adjusting the control signal according to the count value and a target value representing a target frequency, to adjust the frequency of the output signal provided by the filter until a calibration value, which allows the count value to be consistent with the target value, of the control signal is determined. The filter performs filtering according to the control signal with the calibration value in an operating stage. The calibration circuit performs feedback adjustment on the filter to achieve bandwidth calibration with high calibration accuracy and simple circuit structure.

Participant station (10; 30; 50; 60) for a bus system (1; 2), with a transmitting / receiving device (13) for transmitting a signal via the bus system (1; 2) to another subscriber station and for receiving a signal via the bus system (1; 2), in which at least temporarily exclusive, collision-free access of a subscriber station (10, 20, 30, 50, 60) to a bus line (40) of the bus system (1; 2) is ensured, and a modification device (12; 14) for modifying the transmission characteristics of a transmit path (131) of the transmit / receive device (13) and / or the receiving characteristics of a receive path (132) of the transmit / receive device (13), wherein the modification device (14) comprises a transmitter output stage (150) for pre-distortion of the signal to be transmitted by the transmit / receive device (13) in order to prevent the bus level from settling on a transmit channel within one clock cycle (T S) of the signal to be sent, and / or wherein the modification device (12) is a receiver modification device for changing the detection time (TD) to the right in the eye diagram and the decision threshold (E) upwards in the eye diagram, wherein the transmitter output stage (150) for pre-distortion of the signal to be transmitted by the transmit / receive device (13) is designed such that it adapts the transmitter characteristics of the subscriber station (50; 60) depending on the section of a frame of the bus system (2).

Radio frequency front end modules are provided. In one aspect, a front end system includes at least one power amplifier configured to amplify a transmit radio frequency signal, at least one low noise amplifier configured to receive a receive radio frequency signal, an output node coupled to an antenna. The front end system further includes at least one switch configured to selectively couple the output node to the at least one power amplifier during a transmit period and to the at least one low noise amplifier during a receive period, at least one transmit filter coupled between the power amplifier and the at least one switch, and at least one receive filter coupled between the low noise amplifier and the at least one switch.

A filter device includes a multilayer body including dielectric layers, and an LC resonator including an inductor and a capacitor to transmit a signal from an input terminal to an output terminal. The LC resonator includes plate electrodes on dielectric layers different from each other and connected by a via. The plate electrodes define and function as the inductor. The plate electrodes overlap at least partially in a direction of lamination of the multilayer body. Each of the plate electrodes includes an extending portion extending in an x axis direction, and an extending portion extending in a y axis direction. An area of the extending portion of one plate electrode is smaller than an area of the other extending portion.

A differential amplifier comprises a first differential circuitry structure including a first part comprising at least one branch of transistors and a second part comprising at least one branch of transistors, and a second circuitry structure. The second circuitry structure has a first non-linear device and a second non-linear device. The non-linear devices each comprise a transistor having a control node connected to a differential output terminals of the differential amplifier. A common centre node of the non-linear devices is connected to a control node of one of the transistors of each branch of the first part having a differential output terminal. Amplifier applications, communication devices and network nodes are also disclosed.

A MUX (72) for a battery management system (10') includes a first input terminal for coupling to a first pin (Ci) of a battery stack (B), a second input terminal for coupling to a second pin (Ci-1) of the battery stack (B), and a third input terminal for coupling to a third pin (Ci-2) of the battery stack (B). A first switch (SWi) has a respective first terminal (100i) coupled to the first input terminal of the MUX, a second switch (SWi-1) has a respective first terminal (100i-1) coupled to the second input terminal of the MUX, and a third switch (SWi-2) has a respective first terminal (100i-2) coupled to the third input terminal of the MUX. An AFE and selection circuit (724) includes a first input terminal coupled to a second terminal (102i) of the first switch (SWi), a second input terminal coupled to a second terminal (102i-1) of the second switch (SWi-1), a third input terminal coupled to a second terminal (102i-2) of the third switch (SWi-2), a first output terminal for coupling to a positive input of a first level shifter circuit (16i), a second output terminal for coupling to a negative input of the first level shifter circuit (16i), a third output terminal for coupling to a positive input of a second level shifter circuit (16i-1), and a fourth output terminal for coupling to a negative input of the second level shifter circuit (16i-1). Each of the first, second, third and fourth output terminals of the AFE and selection circuit (724) is selectively couplable to any of the first, second and third input terminals of the AFE and selection circuit (724).

The invention provides a method for realizing power synthesis through multi-stage 90-degree bridge phase superposition, which comprises the following steps of: cascading 90-degree couplers and adding N identical amplifiers to form a power synthesis module, and bonding the N amplifiers with the 90-degree couplers through microstrip lines and gold wires with equal electrical lengths, and the power synthesis module performs N-time power synthesis by utilizing four-port device matching reciprocal transmission, N is 2n, and n is a positive integer. According to the invention, theoretical lossless transmission is realized by using the characteristic of matching reciprocal transmission of the four-port device; expansibility is achieved, and higher power can be formed through multiple times of accumulation based on a currently used coupling power method; the plane structure has the characteristic of adapting to various structures and is suitable for industrial large-scale production.

The application discloses a frequency synthesizer module, and relates to the technical field of radio frequency frequency synthesis, which comprises a control board, a fixed local oscillator board, a frequency hopping local oscillator board and a power division clock board. The control board comprises a programmable logic device, a serial interface circuit and a voltage conversion circuit. The programmable logic device is connected with the first phase-locked synthesizer and the second phase-locked synthesizer through the serial interface circuit. The voltage conversion circuit is connected with the fixed local oscillator board, the frequency hopping local oscillator board and the power division clock board. The power division clock board comprises a phase-locked crystal oscillator circuit and a clock power division network. The output end of the phase-locked crystal oscillator circuit is connected with the input end of the clock power division network. The first output end of the clock power division network is connected with the reference input end of the first phase-locked synthesizer. The second output end of the clock power division network is connected with the reference input end of the second phase-locked synthesizer. At least one output end of the clock power division network is used as the clock output end of the frequency synthesizer module. The frequency synthesizer module can accurately control the output power, suppress the stray and improve the spectral purity, thereby ensuring excellent phase noise performance and controllable frequency hopping time.

The utility model discloses an S-band and C-band broadband high-power synthesis device, which comprises a front-stage power distribution module, at least two amplification modules and a rear-stage power synthesis module, the pre-stage output end is connected with the input ends of the amplification modules, and the output ends of the amplification modules are connected to the post-stage input end in tandem; the amplification module comprises an input T-junction micro-strip power divider, a 90-degree hybrid bridge, a gallium nitride power amplification chip, a matched load and an output T-junction micro-strip power divider, isolation ports of the 90-degree hybrid bridge are connected with the matched load, each stage of power divider is integrated with a quarter-wavelength impedance conversion node, and radio frequency and power supply circuits in the amplification module are arranged in a stacked manner; according to the device, ultra-wideband high-efficiency power synthesis is realized through impedance matching and unbalanced energy directional absorption, and the device has the advantages of thermal management optimization, phase consistency guarantee, modular expandability and maintainability.

A method for configuring a circuit for generating samples from a target distribution comprises: receiving a matrix representing parameters associated with the target distribution; tuning a plurality of tunable capacitance circuits in a tunable capacitance network based at least in part on respective elements of the matrix, wherein the tunable capacitance network consists essentially of interconnected wires intersecting at a plurality of nodes with selected pairs of nodes of the plurality of nodes interconnected by a respective tunable capacitance circuit of the plurality of tunable capacitance circuits and one or more nodes of the plurality of nodes connected to a common ground by a respective tunable capacitance circuit of the plurality of tunable capacitance circuits; recording respective voltage samples from the plurality of nodes of the tunable capacitance network; and storing a linear transformation of a vector of the voltage samples based at least in part on the matrix.

The invention discloses a mode reconfigurable on-chip power amplifier and a power amplification method. The power amplifier comprises an input port, an output port, an input duplexer, an output duplexer, a low-frequency phase shift circuit, a high-frequency phase shift circuit, a low-frequency power amplifier and a high-frequency power amplifier. The input port is configured to be an input port of an input duplexer, and the output port is configured to be an output port of an output duplexer; the input duplexer is used for realizing a function of combining and inputting input low-frequency signals and high-frequency signals, an output end of the input duplexer is respectively connected with input ends of the low-frequency phase-shifting circuit and the high-frequency phase-shifting circuit, an output end of the low-frequency phase-shifting circuit is connected with an input end of the low-frequency power amplifier, and an output end of the high-frequency power amplifier is connected with an output end of the high-frequency power amplifier. The output end of the high-frequency phase shift circuit is connected with the input end of the high-frequency power amplifier; the output end of the low-frequency power amplifier and the output end of the high-frequency power amplifier are both connected with the input end of the output duplexer.

A MUX for a battery management system includes first, second, and third input terminals for coupling to first, second, and third pins of a battery stack, respectively. First, second, and third switches have respective first, second, and third terminals coupled to the first, second, and third input terminals of the MUX, respectively. An AFE and selection circuit includes first, second, and third input terminals coupled to second terminals of the first, second, and third switches, respectively, first and third output terminals for coupling to positive inputs of first and second shifter circuits, second and fourth output terminals for coupling to negative inputs of the first and second level shifter circuits, respectively. Each of the first, second, third and fourth output terminals of the AFE and selection circuit is selectively couplable to any of the first, second and third input terminals of the AFE and selection circuit.

A radar transceiver is provided. The radar transceiver includes an electrical balance duplexer that is coupled to a transmission node of a transmission path, a reception node of a reception path, and an antenna node and that is configured to isolate the transmission path from the reception path. The electrical balance duplexer includes a hybrid transformer network and a non-tunable balancing impedance. The non-tunable balancing impedance is configured to provide a fixed impedance value that corresponds to an impedance value at the antenna node.

The invention discloses a high-power radio frequency circulator based on a silicon-based CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process. The circulator comprises a transmission network consisting of a gyrator and lumped parameter LC elements, the gyrator includes a first pair of switches, a second pair of switches, and a lambda / 4 transmission line connected therebetween. The first switch pair is connected between the transmitting end and the lambda / 4 transmission line, the second switch pair is connected between the lambda / 4 transmission line and the antenna end, and the two groups of switch pairs are respectively controlled by complementary non-overlapped local oscillation signals, so that directional transmission of the signals in the circulator and isolation between ports are realized. A switched capacitor clock booster circuit is further integrated, three times of voltage swing is realized on the premise of not increasing the power supply voltage, the power processing capacity of the transistor switch is remarkably improved, and meanwhile, the system power consumption is reduced. Besides, an LC lumped structure is adopted to replace a distributed transmission line, so that the chip area is greatly reduced, the integration level is improved, and the antenna is suitable for high-power and high-integration-level radio frequency front-end application in a full-duplex communication system.

The invention discloses an anti-interference straight-through switching circuit of a satellite transceiver. The anti-interference straight-through switching circuit comprises a first comparator, a second comparator, a B3 straight-through circuit, a B3 anti-interference circuit, an S straight-through circuit and an S anti-interference circuit, an external mode control signal is input into the input end of the first comparator and the input end of the second comparator, and the output end of the first comparator is connected with the input end of the first B3 change-over switch and the input end of the second S change-over switch. The output end of the second comparator is connected with the input ends of the second B3 change-over switch and the first S change-over switch; the first comparator and the second comparator output opposite output signals; the structure of the B3 frequency point signal processing circuit and the S frequency point signal processing circuit on the circuit board is a central symmetry structure. According to the invention, switching of the direct-through circuit and the anti-interference circuit of the B3 frequency point and the S frequency point can be controlled through the two comparator circuits, the number of components required by a control part is greatly reduced, and the size, the weight and the structural complexity of equipment are effectively reduced.

The invention discloses a frequency synthesizer module, which relates to the technical field of radio frequency synthesis, and comprises a control panel, the control panel comprises a programmable logic device, a serial interface circuit and a voltage conversion circuit, the programmable logic device is respectively connected with a first phase-locked synthesizer and a second phase-locked synthesizer through the serial interface circuit, and the voltage conversion circuit is connected with the first phase-locked synthesizer and the second phase-locked synthesizer through the serial interface circuit. The voltage conversion circuit is respectively connected with the fixed local oscillator plate, the frequency hopping local oscillator plate and the power division clock plate; the power division clock board comprises a phase-locked crystal oscillator circuit and a clock power division network, the output end of the phase-locked crystal oscillator circuit is connected with the input end of the clock power division network, the first output end of the clock power division network is connected with the reference input end of the first phase-locked synthesizer, and the second output end of the clock power division network is connected with the reference input end of the second phase-locked synthesizer. At least one output end of the clock power division network serves as a clock output end of the frequency synthesizer module. The frequency synthesizer module ensures excellent phase noise performance and controllable frequency hopping time by accurately controlling output power, spurious suppression and frequency spectrum purity.

The application discloses a suspended strip line triplexer and limiter integrated device, and relates to the microwave and radio frequency technical field.The device comprises a suspended strip line triplexer composed of a metal cavity and a suspended dielectric substrate, is provided with one input port and three output ports corresponding to different frequency bands, and is provided with a step impedance resonator group between each port, is connected through parallel plate capacitance, and is further connected through a high impedance thin line equivalent series inductance.The step impedance resonator is used for generating a transmission zero point outside the frequency band.The device is provided with PIN diode limiters at the three output ports, the metal cavity is composed of upper and lower metal cover plates, metal patches on the suspended strip line are connected with the upper and lower metal cover plates through vias, radio frequency grounding is realized, and a limiter PIN diode grounding position is reserved.The application has the advantages of compact structure, multi-frequency band signal separation, interference suppression, interference signal amplitude limitation, improved system reliability and stability, and function expansion.

A circuit (10; 10') comprising a switching circuit block (12) comprising a node (SW) configured to provide a modulated signal (PWM); a low-pass filter circuit block (14) coupled to the switching node (SW) of the switching circuit block (12) to receive the modulated signal (PWM), the low-pass filter circuit (14) configured to apply low-pass filtering processing to the modulated signal (PWM) at a low-pass cut-off frequency, providing a demodulated signal (RPL) to a load impedance (Rload) as a result; a replicating circuit block (16) coupled to the switching node (SW) of the switching circuit block (12) to receive the modulated signal (PWM), the replicating circuit (16) configured to apply to the modulated signal (PWM) a replica of the low-pass filtering processing of the low-pass filter circuit (14), providing a reference signal (REF) as a result; a signal processing circuit block (20) coupled to the low-pass filter circuit (14) and to the replicating filter circuit (16), the signal processing circuit block (20) configured to apply signal processing to the demodulated signal (RPL) and to the reference signal (REF), providing at least one indicator signal (Vc, Vpp) indicative of a variation of the cut-off frequency of the at least one demodulator circuit block (14) as a result.

A variable gain amplifier includes a differential amplifier circuit having a pair of input terminals and a pair of output terminals, and a first variable attenuation circuit connected between at least one of the pair of input terminals and the pair of output terminals of the differential amplifier circuit and capable of switching a resistance value on the basis of a control signal which is input from the outside.

A radio frequency (RF) receiver, for example a satellite positioning system receiver, can be configured to use a single phase locked loop for generating an oscillator signal to perform downconversion of signals in two different frequency bands using two or more local oscillators. A first RF signal portion includes a first signal band and undergoes double downconversion using a first mixer and a second mixer, while a second RF signal portion includes a second signal band and undergoes single downconversion using a single mixer. A controller is configured to determine a first oscillator divider value and a second oscillator divider value to avoid a jammer frequency and frequency dividers are used to generate the two or more local oscillators.

This application relates to a switching circuit. A method and switching circuit for providing a switch array with on-resistance are proposed. The switch array has multiple switches, each arranged in a different configuration state. The states include an enabled configuration and a disabled configuration. The switch states include an on state and an off state. Each switch remains in the off state when in the disabled configuration. A control circuit sets the switches to the enabled or disabled configuration, and a memory element is coupled to the control circuit and arranged to store configuration data for setting the configuration state of each of the switches. The control circuit sets the configuration state of the switches based on signals received from the memory element. The on-resistance of the switch array depends on the switching state of the switches and their respective on-resistances.

The present disclosure provides a capacitance circuit which has an input terminal and is configured to provide an increased capacitance between the input terminal and a first reference voltage. The capacitance circuit comprises a current source structure configured to provide a compensation current at the input terminal, a first transistor having a first control terminal and a first load current and being coupled to the input terminal, a second transistor having a second control terminal, a capacitance amplification circuit configured to provide a capacitance amplification factor and being coupled between the first control terminal and the second control terminal, and a capacitor having a core capacitance and being coupled between the first control terminal and the input terminal, wherein the compensation current corresponds to the first load current during direct current operation, and wherein the increased capacitance is based on the core capacitance and the capacitance amplification factor.