122results about "Active element network" patented technology

The invention discloses an active power synthesis network of a micro-strip and waveguide hybrid architecture. The active power synthesis network comprises a micro-strip power division network, a micro-strip power amplification circuit, a waveguide power combiner and a power-on / power-off sequence control circuit. The power synthesis network is designed by adopting a micro-strip and waveguide hybrid architecture, so that the overall size can be greatly reduced on the premise of ensuring the power capacity of the power synthesis network; the power-on / power-off sequence control circuit based on the Zener diode is designed, the power amplification chip can be effectively protected and prevented from being damaged due to the wrong power-on / power-off sequence, meanwhile, the number of power needing to be supplied to the power amplification chip at the same time is reduced, and the use complexity of the power synthesis module is reduced.

The invention provides a harmonic enhancement type load traction system. The harmonic enhancement type load traction system comprises a circulator, an impedance tuner, a high-pass filter, a radio frequency power amplifier and a non-reflection duplexer which are connected end to end to form a closed-loop structure, the input end of the circulator is connected with a bias structure of a to-be-tested device, and the non-reflection duplexer is connected with a fundamental wave signal to form an open-loop structure; the active closed-loop load traction structure is used at the harmonic wave position, the active open-loop load traction structure is used at the fundamental wave position, tuning of the fundamental wave and tuning of the second harmonic wave are effectively compatible, the integration level is high, and impedance tuning of the harmonic wave can be achieved under the condition that other equipment such as a signal source is not introduced.

The invention relates to a full duplex digital isolator. A circuit is provided. The circuit comprises: a first transmitter circuit having a first input terminal arranged to receive first input data and a first node arranged to transmit first intermediate data corresponding to the first input data; a first receiver circuit including a second node arranged to receive the first intermediate data and a first output terminal arranged to generate first output data corresponding to the first input data; comprising a second input terminal and said second node, the second input terminal arranged to receive second input data, the second node further arranged to transmit second intermediate data corresponding to the second input data; and a second receiver circuit comprising a first node and a second output terminal, the first node being further arranged to receive the second intermediate data, and the second output terminal being arranged to generate second output data corresponding to the second input data.

A programmable impedance element includes a plurality of nominally identical two-port elements, each two-port element having an impedance element and two switches. The two-port elements are arranged in a chain with a structured switch group such that a certain range of impedances can be obtained from each unit by dynamically changing the connections between the impedance elements in the unit. A common unit is constructed by connecting the nominally identical two-port impedance elements in such a way that the number of possible combinations of impedance elements is reduced to a subset of all possible combinations using the minimum possible number of connections. This structure allows the use of industry-standard devices to generate matching impedances. The connections between the impedance elements are switches, which can be "field programmable", i.e., they can be set on the chip after manufacturing and configured during the operation of the circuit or can be mask programmable.

The present disclosure relates to a capacitance multiplier for decoupling capacitors. An integrated circuit can include one or more circuits coupled to a capacitance multiplier circuit. The capacitance multiplier circuit can include a capacitor, fixed and tunable resistors, and a transconductance circuit. The tunable resistor can be adjusted to control the total capacitance of the capacitance multiplier circuit. The transconductance circuit can include a transistor having a drain terminal coupled to a first electrical component and a source terminal coupled to a second electrical component. The first electrical component can be a diode-connected transistor, a direct shorted wire, a resistor, an inductor, or a current source. The second electrical component can be a current source, a direct shorted wire, a resistor, an inductor, or another diode-connected device. Configured in this way, the capacitance multiplier circuit can provide a large adjustable capacitance without voltage drop and without consuming a large amount of power.

Certain aspects of the present disclosure generally relate to radio frequency (RF) front-end circuit systems. For example, certain aspects provide a device having a first converter circuit and a second converter circuit, the first converter circuit being configured to up-convert a first baseband (BB) signal to a first radio frequency (RF) signal based on an operating mode, and the second converter circuit being configured to up-convert a second BB signal to a second RF signal based on an operating mode. The device also includes a first RF weight adjustment circuit and a controller, the first RF weight adjustment circuit being configured to selectively apply an amplitude weight or a phase weight to at least one of the first RF signal or the second RF signal based on an operating mode, and the controller being configured to control a power state of the second converter circuit according to the operating mode.

A radio-frequency module includes a first switch, a first filter, second filters, a power amplifier, and a low-noise amplifier. The first switch has a first terminal, a second terminal, and a third terminal. The first terminal is coupled to an antenna terminal. The first filter is coupled to the second terminal. The second filters are coupled to the third terminal. The first filter includes a common filter circuit and an additional filter circuit. The additional filter circuit is coupled between the power amplifier and the common filter circuit. The low-noise amplifier is coupled to a path that branches off from a path connecting between the common filter circuit and the additional filter circuit. The common filter circuit is coupled between the additional filter circuit and the first switch.

The present invention provides a cavity coupler, including a main body, and a coupling structure and an active compensation circuit fixedly connected to the main body via a printed circuit board. The main body is a shell having a cavity inside, and an inner conductor penetrating the cavity is arranged inside the main body; the coupling structure is a metal conductor arranged inside the cavity and fixedly connected to the printed circuit board; the active compensation circuit includes a passive compensation network and an active amplification circuit, and the active compensation circuit adjusts the first coupling coefficient with a span value greater than 60dB output by the coupling structure to a second coupling coefficient with a fixed value A and a flatness of ±1dB. The present invention provides a cavity coupler, which realizes a high-power ultra-wideband directional coupler of 1MHz~1.2GHz by using a weak coupling method with an active compensation circuit. At the same time, an active amplification circuit is added after the passive compensation network to reduce the complexity of the passive compensation network.

Aspects of this disclosure relate to a parallel hybrid acoustic passive filter. The parallel hybrid acoustic passive filter includes a first sub-filter and a second sub-filter. The first sub-filter includes a first acoustic resonator and a first non-acoustic passive component. The second sub-filter includes a second acoustic resonator and second first non-acoustic passive component. The first sub-filter and the second sub-filter are together arranged to filter a radio frequency signal. The parallel hybrid acoustic filter can be a band pass filter or a band stop filter, for example. Related multiplexers, wireless communication devices, and methods are disclosed.

To improve the heat dissipation properties of a filter.SOLUTION: A duplexer 100 includes a substrate 10, a receiving filter 40 provided on the substrate 10 and including series resonators S21 to S23 and parallel resonators P21, P22, a transmitting filter 30 provided on the substrate 10 alongside the receiving filter 40 and including series resonators S11 to S14 and parallel resonators P11 to P14, a lid provided on the substrate 10 and sandwiching a gap 18, where the receiving filter 40 and the transmitting filter 30 are located, between the substrate 10 and the lid, columnar bodies 80b provided in a region 42 of the receiving filter 40 between the substrate 10 and the lid within the gap 18, and columnar bodies 80a provided in a region 32 of the transmitting filter 30 between the substrate 10 and the lid within the gap 18, the number of columnar bodies being greater than the number of columnar bodies 80b.SELECTED DRAWING: Figure 1

A multiplexing circuit, an interface circuit system, and a mobile terminal, to resolve a problem that a charging current significantly decreases when a headset is used during charging of the mobile terminal. In a multiplexing circuit, a first switch circuit transmits a right-channel audio signal on a right-channel transmission end to a first external transmission end; a second switch circuit transmits a left-channel audio signal on a left-channel transmission end to a second external transmission end; when a second on voltage is received, but a first on voltage is not received, an isolation circuit transmits the second on voltage to a third switch circuit; and when the first on voltage and the second on voltage are received, the isolation circuit pulls down the third switch circuit, and isolates a ground end from a second on voltage end.

The error amplifier circuit of the present invention includes: a plurality of error amplifiers that respectively obtain outputs of errors regarding two input signals; and a multiplexer that selects or deselects the outputs of the plurality of error amplifiers and outputs the output of the selected error amplifier as a control signal for a controlled circuit. In the multiplexer, for one of the plurality of error amplifiers whose output is not selected, a delay element provided on the input path of the one error amplifier is short-circuited to expand the frequency band of the error amplifier.

Aspects of this disclosure relate to hybrid acoustic LC filter with harmonic suppression. The hybrid acoustic LC filter includes a hybrid passive / acoustic and a non-acoustic LC filter cascaded with the hybrid passive / acoustic filter. The hybrid passive / acoustic filter can be configured to filter a radio frequency signal. The hybrid passive / acoustic filter can include acoustic resonators and a non-acoustic passive component. The non-acoustic LC filter can be configured to suppress a harmonic of the radio frequency signal. The non-acoustic LC filter can be a low pass filter or a harmonic notch filter, for example. Related multiplexers, wireless communication devices, and methods are disclosed.

Aspects of this disclosure relate to a multiplexer with a hybrid acoustic passive filter. The multiplexer includes a plurality of filters configured to filter respective radio frequency signals, a shared filter coupled between each of the plurality of filters and a common node, and a radio frequency filter coupled to the common node. At least a first filter of the plurality of filters includes acoustic resonators and a non-acoustic passive component. Related multiplexers, wireless communication devices, and methods are disclosed.

The utility model relates to the technical field of radio frequency microwave communication, and discloses a radio frequency microwave power synthesis device, which comprises an external power supply, an EMC (Electro Magnetic Compatibility) protection module and a power supply management module, the power management module is electrically connected with a signal preprocessing module, a power amplification module, an input coupling and detection module, a frequency selection switch matrix module, a reconfigurable filter network module, a dynamic power adjustment module, a phase matching module, a power synthesis module, an output coupling and detection module and an intelligent control module. According to the utility model, through cooperation of the dynamic power adjustment module, the phase matching module, the power amplification module and the power synthesis module, the power synthesis efficiency of the radio frequency microwave power synthesis device is improved, the power consumption is reduced, and the signal distortion is reduced; and high-efficiency power synthesis in a wide frequency band is realized.

The invention provides a switching circuit, an attenuation circuit, a receiver, a base station and a mobile device. The switching circuit includes: a first node for coupling to a first conductive path; and a second node for coupling to a second conductive path. Further, the switching circuit includes a first stack and a second stack of transistors arranged between the first node and the second node. The first transistor in the first stack and the first transistor in the second stack are cross-coupled with the second transistor in the second stack and the second transistor in the first stack, respectively. The first transistors in the first stack and the second stack are coupled to a first node. The third transistor in the first stack and the third transistor in the second stack are cross-coupled with the fourth transistor in the second stack and the fourth transistor in the first stack, respectively. The fourth transistors in the first stack and the second stack are coupled to a second node.

Provided is a semiconductor device. In a first operation mode, a first modulated signal is input to a plurality of inverter circuits provided in a first amplifier circuit, and a second modulated signal is input to a plurality of inverter circuits provided in a second amplifier circuit. In a second operation mode, a test signal generation circuit modulates a test signal to generate a third modulated signal and a fourth modulated signal. The third modulated signal is input to some of the plurality of inverter circuits provided in the first amplifier circuit, and outputs of other inverter circuits have high impedances. The fourth modulated signal is input to some of the plurality of inverter circuits provided in the second amplifier circuit, and outputs of other inverter circuits have high impedances. A peak frequency detection circuit detects a frequency range including a frequency of the test signal at which an impedance of a sound reproduction device peaks.

A coupling module can be used to communicate high speed signals between an optical transceiver and a processing module of an optical communication device, such as an optical line termination (OLT) or an optical network unit (ONU). The coupling module can adjust the common mode voltage level of a differential signal output by the optical transceiver to the common mode voltage level required by the processing module. In addition, the coupling module splits each of the differential output signals from the optical transceiver and passes the split signals to both a high-pass filter and a low-pass filter that are connected in parallel. The outputs of the high-pass filter and the low-pass filter from different paths of the differential signal are cross-coupled and combined to provide a differential signal to the processing module.

The invention relates to a local oscillator power division circuit applied to large-scale MIMO independent local oscillator configuration, which comprises a reference low-frequency local oscillator source, a plurality of phase-locked loop modules, a power distribution module, a plurality of IQ mixers and a radio frequency processing module, the output end of the reference low-frequency local oscillator source is respectively connected with the plurality of phase-locked loop modules, the output end of each phase-locked loop module is connected with the power distribution module, the input end of each IQ frequency mixer is respectively connected with the output end of the power distribution module, and the input end of each IQ frequency mixer also receives an independent IQ signal; and the output end of the reference low-frequency local oscillator source is also connected with the power distribution module. By adopting the local oscillator power division circuit applied to the large-scale MIMO independent local oscillator configuration, a plurality of local oscillator signals which are independent, small in stray and adjustable in frequency and power can be obtained, a plurality of local oscillators can be independently provided for each receiving and transmitting channel of an MIMO system, and a receiving and transmitting channel is more flexible and adapts to a more complex environment.

The invention discloses a circuit topological structure of a multiplexer, a radio frequency module and an electronic device, and relates to the technical field of multiplexers, the circuit topological structure comprises an antenna matching inductor, the antenna matching inductor comprises at least one component, and the signal path direction from the head end to the tail end of the component is anticlockwise; the transmitting filter comprises a series arm structure and a parallel arm structure connected with the series arm structure, the series arm structure comprises at least one series arm, one series arm comprises at least one series resonator, the parallel arm structure comprises at least one parallel arm, the series resonator comprises at least one series resonator, and the parallel resonator comprises at least one series resonator. And one parallel arm comprises at least one parallel resonator and a grounding inductor which is connected with the parallel resonator in series. According to the invention, the purpose of reducing the space occupied by the plurality of inductors in the substrate is achieved on the premise of ensuring the out-of-band signal suppression and isolation performance of the multiplexer.

The utility model relates to a circuit structure for direct single-point superposition output of multi-stack signal frequency. The circuit structure comprises a signal input end, a signal coupling module, an input filtering module, a register filtering module, an operational amplifier circuit module, an output bias resistor, a first ground resistor and a signal output end, the signal input end is connected with the input end of the signal coupling module, the output end of the signal coupling module is connected with the input end of the input filtering module, the output end of the input filtering module is connected with the input end of the register filtering module, and the output end of the register filtering module is connected with the input end of the operational amplifier circuit module. The output end of the operational amplifier circuit module is connected with the first end of the output bias resistor and the input end of the register filter module, the second end of the output bias resistor is connected with the input end of the operational amplifier circuit module, the first end of the first resistor to ground is connected with the input end of the operational amplifier circuit module, and the second end of the first resistor to ground is grounded. The signal output end is connected with the second end of the output bias resistor.

A noise filtering circuit, a digital to analog converter and an electronic device are provided. The noise filtering circuit comprises a first amplifier configured to receive a bias voltage at a first input terminal, receive a bias output voltage at a second input terminal though a feedback path, and compensate for a difference between the bias voltage and the bias output voltage; a first transistor connected to an output of the first amplifier and having a gate to which an off-voltage is applied; a first capacitor connected to the first transistor; a second capacitor connected to the output of the first amplifier; a second transistor connected to the second capacitor and having a gate to which an off-voltage is applied, and a second amplifier having an input terminal connected to the first capacitor and a second input terminal connected to the second transistor.

The invention provides a multiplexer which improves the heat dissipation performance of a filter. A duplexer (100) is provided with: a substrate (10); a reception filter (40) provided on the substrate (10) and including series resonators (S21-S23) and parallel resonators (P21, P22); a transmission filter (30), which is provided on the substrate (10) so as to be aligned with the reception filter (40), and which includes series resonators (S11-S14) and parallel resonators (P11-P14); a cover that is provided on the substrate (10) and that sandwiches a gap (18) between the cover and the substrate (10), the reception filter (40) and the transmission filter (30) being located in the gap (18); a columnar body (80b) provided in a region (42) of the receiving filter (40) between the substrate (10) and the cover within the void (18); and columnar bodies (80a) provided in a region (32) of the transmission filter (30) between the substrate (10) and the cover within the void (18), the number of the columnar bodies (80a) being larger than the number of the columnar bodies (80b).

The invention relates to a multiplexer circuit for a battery management system and a corresponding battery management system. A MUX for a battery management system includes first, second, and third input terminals for coupling to first, second, and third, respectively, of a stack. The first, second, and third switches have respective first, second, and third terminals coupled to first, second, and third input terminals, respectively, of the MUX. The AFE and selection circuit includes first, second and third input terminals coupled to second terminals of the first, second and third switches, respectively, first and third output terminals for coupling to positive inputs of the first and second level shifter circuits, and second and fourth output terminals for coupling to negative inputs of the first and second level shifter circuits, respectively. Each of the first, second, third, and fourth output terminals of the AFE and selection circuit is selectively coupleable to any of the first, second, and third input terminals of the AFE and selection circuit.

A circuit. The circuit includes a first transmitter circuit having a first input terminal arranged to receive a first input data and a first node arranged to transmit a first intermediate data corresponding to the first input data, a first receiver circuit including a second node arranged to receive the first intermediate data and a first output terminal arranged to produce a first output data corresponding to the first input data, a second transmitter circuit including a second input terminal arranged to receive a second input data and the second node that is further arranged to transmit a second intermediate data corresponding to the second input data; and a second receiver circuit including the first node and a second output terminal, the first node further arranged to receive the second intermediate data, and the second output terminal arranged to produce a second output data corresponding to the second input data.

The present application relates to the field of quantum chips, and discloses a parameter determination method and apparatus for a quantum chip, and a filtering regulation and control method and apparatus for a quantum chip, for use in solving the problem that a large amount of space of a quantum chip is occupied in order to meet a filtering function of the quantum chip having a large number of bits. Josephson junctions are provided on a coplanar waveguide of a filter. By adjusting the critical current of the Josephson junctions, the equivalent inductance corresponding to the filter is changed, thereby achieving the adjustment of the center frequency of the filter; and by screening for an initial length meeting a center frequency range and a bandwidth range and screening for an inductance set, the Josephson junctions can cover the frequencies required by all resonant cavities during adjustment, thereby achieving the coverage of all resonant cavity frequency bands through one filter. Since the center frequency of the filter is adjustable, the bandwidth of the filter can be designed to be narrower to improve a filtering effect, so that the frequency range for filtering is not compromised and the space required by a filtering circuit is also saved, and therefore, the filter can be integrated on a quantum chip having a large number of bits.

An N-tap feedforward equalizer (FFE) (100) includes: a group of N FFE taps coupled together in parallel; a filter (140) coupled between the (N-1)th FFE tap and the Nth FFE tap; and an adder coupled to the output of the group of N FFE taps. Each FFE tap includes a unique sample and hold (S / H) circuit (120, 130, 150) that generates a unique time-delay signal and a unique transconductance stage (125, 135, 155) that generates a unique transconductance output based on the unique time-delay signal. The filter causes the N-tap FFE to have characteristics greater than N taps. In some instances, the filter is a first-order high-pass filter that causes coefficients greater than N to have opposite polarity to the Nth coefficient. In some instances, the filter is a first-order low-pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.

The present invention is provided with a filter circuit (104) having resistors (201a, 201b), MOS capacitors (202a, 202b), and an MOM capacitor (203) laminated on the resistors (201a, 201b) or / and the MOS capacitors (202a, 202b). Given the cutoff frequency of a filter circuit (104) is ft, the resistance area of a resistance formation region (600) in which resistors (201a, 201b) are formed is Mr, the MOS capacitance area of an MOS capacitance formation region (500) in which MOS capacitors (202a, 202b) are formed is Mc, the resistivity of the resistors (201a, 201b) is alpha, the MOS permittivity of the MOS capacitors (202a, 202b) is beta, and the MOM permittivity of the MOM capacitor (203) is gamma, # imgabs0 # is satisfied.

Disclosed is a calibration circuit, a calibration method for a filter and a filter device. The calibration circuit includes: a signal receiving terminal, receiving an output signal from the filter; a frequency detection module, obtaining a count value according to the output signal, the count value representing a frequency of the output signal; an adjustment module, adjusting the control signal according to the count value and a target value representing a target frequency, to adjust the frequency of the output signal provided by the filter until a calibration value, which allows the count value to be consistent with the target value, of the control signal is determined. The filter performs filtering according to the control signal with the calibration value in an operating stage. The calibration circuit performs feedback adjustment on the filter to achieve bandwidth calibration with high calibration accuracy and simple circuit structure.

In certain examples, methods and circuit-based apparatuses involve or are directed to a transducer to be operated via at least one resonance frequency of the transducer, and to a tunable circuitry (e.g., negative capacitance control and / or resistance control) to change the resonance frequency and / or a bandwidth around the resonance frequency. In more specific aspects, a tunable negative capacitance control may be used to change the resonance frequency and / or damping resistance control without degrading a degree of sensitivity provided by the transducer. Another example, specific to a method, involves: operating a transducer, coupled to a negative capacitance, at a resonance frequency of the transducer; and changing or setting a characteristic concerning the resonance frequency by using a tunable circuit to effect a change of the resonance frequency and / or a bandwidth around the resonance frequency.