133results about "Pulse descrimination" patented technology

The invention discloses a data sampling timing error evaluation method based on an evaluation model, relates to the technical field of timing error evaluation, and solves the problem that timing error evaluation is not accurate enough. Wherein the sampling module realizes undistorted receiving and clock signal frequency output of a clock signal through a CMOS clock input circuit, a third-order digital phase-locked loop circuit and a DSP digital signal processing chip, and a Fourier phase difference algorithm removes harmonic interference to solve a phase difference between the clock signal and an ideal clock signal; the clock signal feature recognition unit adopts a convolutional neural network to carry out iterative training on a training set of the timing error evaluation module to obtain an error evaluation module, the error evaluation module and the time migration algorithm module realize accurate calculation of a timing error value, and the timing error value calculation accuracy is greatly improved.

The demodulation circuit includes a waveform regulator, a first counter, a second counter, and an SR latch. The waveform regulator generates a regulated modulation signal according to a pair of differential isolated modulation signals, which is generated according to a modulation of an input data signal with a carrier clock signal. The first counter counts cycles of the regulated modulation signal so as to generate a set signal. The second counter counts cycles of a reference clock signal so as to generate a reset signal. The SR latch includes a set terminal for receiving the set signal, a reset terminal for receiving the reset signal, and an output terminal for outputting a demodulated output signal. The SR latch is triggered by the set signal to pull up the demodulated output signal, and is triggered by the reset signal to pull down the demodulated output signal.

The invention provides a pulse width modulation (PWM) signal capturing method and device and electronic equipment, and belongs to the technical field of electronic signals.The pulse width modulation (PWM) signal capturing method comprises the steps that when it is detected that the duty ratio of a pulse width modulation (PWM) signal is within an extreme duty ratio range, the PWM signal is captured; predicting an expected arrival time interval of the next expected edge according to a plurality of historical period parameters of the PWM signal in the sliding window; before the expected arrival time interval, the level state of the PWM signal is obtained according to a preset frequency, the synchronous count value of the timer when the expected level state is collected is recorded, and the preset frequency is higher than the timing frequency of the timer; and determining a current period parameter of the PWM signal according to the synchronous count value. The missed capture rate can be reduced when a single-channel timer is adopted to capture a PWM signal.

The invention discloses a high-voltage positive and negative pulse detection circuit, which relates to the technical field of signal conditioning, and is characterized in that a voltage division circuit is responsible for attenuating input pulse signals, a switching diode is responsible for rectification and inputting positive and negative pulse signals into corresponding conditioning circuits respectively, and a charging circuit is responsible for maintaining pulse width characteristics of the signals; and the steepness of the signal edge is ensured by the comparator, and FPGA identification can be realized. Uncertain high-voltage pulse signals can be processed, and application scenes are diversified. The edge characteristic, pulse width and pulse direction of the pulse signal can be identified, and the signal processing capability is prominent.

An active eye open monitor calibration apparatus and method for active eye open monitor calibration are provided. A reference clock signal and an eye open monitor clock signal are received and a calibration selecting signal is used to control whether the reference clock signal samples the eye open monitor clock signal. An indicator signal is output and received by a phase indicating determination circuit for performing a calibration flow and accordingly calculating a phase offset signal. The eye open monitor clock is corrected based on the phase offset signal, such that a calibrated eye open monitor clock signal is synchronously in phase with the reference clock signal. By employing the proposed eye open monitor calibration apparatus and method thereof, the invention is effective in achieving phase synchronization for an eye open monitor clock signal in related to its reference clock signal, solving the phase mismatch in the related arts.

The invention relates to the technical field of signal frequency measurement, in particular to a low-frequency-band fixed square wave frequency high-precision measurement method based on a kernel clock, which is suitable for the field of embedded systems and digital signal processing, is mainly used for low-frequency and fixed-frequency-band high-precision frequency measurement, and is not a frequency meter method specially used for measuring frequency. The method is suitable for measuring the fixed output frequency in a test system and the like. According to the method, a kernel clock of an embedded system (such as an STM32 single-chip microcomputer) is mainly utilized, a time constant is calibrated by measuring the count value of the duration of high and low levels of a fixed time window, and therefore the square wave frequency is obtained through calculation.

The demodulation circuit includes a waveform regulator, a first counter, a second counter, and an SR latch. The waveform regulator generates a regulated modulation signal according to a pair of differential isolated modulation signals, which is generated according to a modulation of an input data signal with a carrier clock signal. The first counter counts cycles of the regulated modulation signal so as to generate a set signal. The second counter counts cycles of a reference clock signal so as to generate a reset signal. The SR latch includes a set terminal for receiving the set signal, a reset terminal for receiving the reset signal, and an output terminal for outputting a demodulated output signal. The SR latch is triggered by the set signal to pull up the demodulated output signal, and is triggered by the reset signal to pull down the demodulated output signal.

An example apparatus includes: first current source circuitry having a terminal; a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor coupled to the terminal of the first current source circuitry, the control terminal of the first transistor coupled to the terminal of the first frequency multiplier circuitry; second current source circuitry having a terminal; a second transistor having a first terminal and a second terminal, the first terminal of the second transistor coupled to the terminal of the second current source circuitry; an inductor having a first terminal and a second terminal; a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the first terminal of the inductor; and an amplifier having a terminal coupled to the second terminal of the first transistor, the second terminal of the second transistor.

An electronic system (fig. 1: 10) is disclosed. The system has a differential signal generator (fig. 1: 100) configured to generate first and second single ended signals (fig. 1: D, DN) having opposite polarities. The input signal (fig 1: IN), and the first and second single ended signals transition between a first power voltage and a first ground voltage (fig. 1: Vdd1, Gnd1). The system also has a glitch management circuit (fig. 1: 200, fig. 4: 210, 220) configured to generate an output signal (fig. 1, 4: Out) based on the first and second single ended signals (fig. 1, 4: D, DN), where the output signal transitions between a second power voltage and a second ground voltage. The glitch management circuit includes a first latch (fig. 4: 210) configured to receive the first and second single ended signals (fig. 11, 4: D, DN), and to generate first and second intermediate signals (fig. 4: I, IB). The first and second intermediate signals each transition between the second power voltage and the second ground voltage. The system also has a second latch (fig. 4: 220) configured generate the output signal (fig. 1, 4: Out) based on the first and second intermediate signals.

The present application relates to a circuit and method for detecting clock anomalies, a clock circuit, a chip, and a radar. The circuit for detecting clock anomalies includes: a first clock frequency determination unit configured to determine a first clock frequency of a received first clock signal; a reference quantity determination unit configured to determine a reference quantity corresponding to the first clock signal, where the reference quantity is determined based on a second clock signal and / or a time stamp; and a clock anomaly detection unit connected to the first clock frequency determination unit and the reference quantity determination unit respectively, and configured to perform anomaly detection on the first clock signal based on the first clock frequency and the reference quantity. The present application can improve the reliability of the clock signal, thereby enhancing the personal safety and property safety of users.

Provided are a malicious attack protection circuit, a system-on-chip including the same, and an operating method thereof. The malicious attack protection circuit includes a reference interrupt generator to output a reference interrupt signal every reference interrupt period, a variable clock manager for outputting an operating clock signal to a logic circuit outside the malicious attack protection circuit and a variable clock signal having a variable period, a variable interrupt generator to output an interrupt signal every variable interrupt period based on the variable clock signal, a comparison circuit to compare the reference interrupt signal with the interrupt signal and output a comparison result signal, and a controller that interrupts the output of the operating clock signal input to the logic circuit, according to the comparison result signal.

The invention relates to an exception handling circuit and exception handling method for clock data recovery. According to the method and the device, the data sender can be supported to implement data scrambling with direct current balance as a target on the target data to be transmitted, so that the data receiver can receive scrambled data with a direct current balance characteristic through a physical channel. On the basis, periodic samples of sampled data obtained by sampling the scrambled data by a data receiver can be obtained, and when it is judged that a sampling clock phase of the scrambled data is locked at a false eye position in an eye pattern of the scrambled data according to periodic direct-current unbalance deviation of a plurality of continuous periodic samples, the scrambled data is locked at the false eye position in the eye pattern of the scrambled data. According to the method, the phase of the sampling clock can be separated from the false eye position by implementing unlocking phase adjustment on the phase of the sampling clock, so that the dynamic calibration of the phase of the sampling clock can be recovered in time, and the failure risk of clock data recovery can be reduced.

The circuit device includes an output terminal, an output transistor, and a gate voltage control circuit. The output transistor is disposed between the first power supply node and the output terminal. After the input signal (TX) transitions from a first logic level to a second logic level, the gate voltage control circuit causes the gate voltage of the output transistor to change at a first time-voltage change rate. After the gate voltage reaches a first determination voltage, the circuit causes the gate voltage to change at a second time-voltage change rate that is smaller than the first time-voltage change rate. After the gate voltage reaches a second determination voltage, the circuit causes the gate voltage to change at a third time-voltage change rate that is larger than the second time-voltage change rate.

This invention relates to the field of high-resolution time measurement systems and integrated circuit technology, providing a time measurement circuit with a two-dimensional address-modulated TOT pulse, comprising: a common-gate transimpedance amplifier, a high-speed high-gain comparator, a current-mode logic output stage, a common-mode feedback threshold setting circuit, and a two-dimensional address-modulated TOT pulse circuit; the address modulation pulse circuit includes an address modulation pulse width circuit and an address modulation pulse amplitude circuit, wherein the address modulation pulse width circuit includes: multiple sets of first modulation units, multiple sets of second modulation units, multiple inverters, and multiple bits of first digital code; the address modulation pulse amplitude circuit includes: multiple sets of third modulation units and multiple bits of second digital code. This invention allows a single TOT signal to simultaneously carry time information, energy information, and address information, reducing wiring, improving reliability, and increasing integration density.

An apparatus and a method for facilitating a first frequency filtering and a second frequency filtering together with non-reciprocal frequency conversion for electromagnetic isolation.

An example apparatus includes; first current source circuitry (270) having a terminal; a first transistor (275) having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor coupled to the terminal of the first current source circuitry, the control terminal of the first transistor coupled to the terminal of the first frequency multiplier circuitry (200); second current source circuitry (250) having a terminal; a second transistor (260) having a first terminal and a second terminal, the first terminal of the second transistor coupled to the terminal of the second current source circuitry; an inductor (296) having a first terminal and a second terminal; a capacitor (292) having a first terminal and a second terminal, the first terminal of the capacitor coupled to the first terminal of the inductor; and an amplifier (265) having a terminal coupled to the second terminal of the first transistor, the second terminal of the second transistor.

An electronic system and a method of using the electronic system are disclosed. The system includes a differential signal generator configured to generate a first single-ended signal and a second single-ended signal having opposite polarities. The input signal and the first and second single-ended signals transition between a first power supply voltage and a first ground voltage. The system also includes a glitch management circuit configured to generate an output signal based on the first and second single-ended signals. The output signal transitions between a second power supply voltage and a second ground voltage. The glitch management circuit includes a first latch configured to receive the first and second single-ended signals and generate first and second intermediate signals. The first and second intermediate signals each transition between the second power supply voltage and the second ground voltage. The system also includes a second latch configured to generate an output signal based on the first and second intermediate signals.

A comparator circuit includes a first transistor (206), a second transistor (208), a first switch (210), a second switch (212), and a timing circuit. The first transistor (206) and the second transistor (208) are coupled as a differential pair and are configured to compare an input signal with a hysteresis voltage. The first switch (210) is coupled to the first transistor (206) and is configured to selectively enable the first transistor (206). The second switch (212) is coupled to the second transistor (208) and is configured to selectively enable the second transistor (208). The timing circuit is coupled to the first switch (210) and the second switch (212) and is configured to close the first switch (210) in response to a signal transition at the output of the comparator circuit and to close the second switch (212) a predetermined delay time after the first switch (210) is closed.

The invention discloses a second pulse detection protection circuit, system and method and a vehicle. The second pulse detection protection circuit comprises a second pulse transmission module, an input signal detection module and an output signal detection module. The second pulse transmission module outputs a second pulse signal, the input signal detection module outputs a second pulse sampling signal I, the input end of the output signal detection module is connected with the output end of the second pulse transmission module, and the output signal detection module outputs a second pulse sampling signal II; the positioning module is used for judging whether to generate the second pulse signal based on the second pulse sampling signal I and selecting to generate the second pulse signal, and judging whether to stop generating the second pulse signal and whether to output the second pulse signal based on the second pulse sampling signal I and the second pulse sampling signal II. According to the invention, accurate second pulse signals can be obtained in real time.

The invention relates to a transmission device (100) comprising two galvanically isolated sub-circuits (110, 50). The first sub-circuit (110) comprises a carrier signal source (116) for outputting a carrier signal, a digital signal source (112) for outputting a binary signal level, and a logic component (118) for performing an AND operation on two input signals, the logic component having two logic inputs and a first logic output (130), the logic inputs being connected to the signal level output and the carrier signal source output, respectively. The second sub-circuit (150) comprises a signal input (154), a signal output (164), and a first RC element (160, 162), the signal input (154), the signal output (164), and the RC element (160, 162) being connected in parallel with respect to a second reference potential. A first isolation capacitor (202) is connected between the first logic output and the signal input for galvanic isolation. A second isolation capacitor (204) is connected between a first reference potential and the second reference potential for galvanic isolation.

The present invention discloses a pulse identification method for MWD, an apparatus thereof, and an electronic device thereof, relating to the field of pulse technology. The pulse identification method comprises: receiving pulse signal data, and extracting pulse signal segments of a preset length from the pulse signal data in chronological order based on pulse width; processing each pulse signal segment to obtain a target pulse signal segment; identifying the peak pulse on each target pulse signal segment; and determining the target position of each peak pulse on a pulse signal sequence to obtain an initial pulse sequence; removing erroneous pulses on each target pulse signal segment in the initial pulse sequence based on a preset pulse permutation and combination to obtain a target pulse sequence; and converting the target pulse sequence into a decoded value based on a preset pulse parameter table. The present invention solves the technical problem of low accuracy in pulse identification in the related art.

The utility model discloses an AC / DC power supply input identification wake-up circuit and an EVCC, and the circuit comprises a PWM wave signal voltage amplitude stabilizing circuit, a PWM wave signal duty ratio detection circuit, a D trigger module, an AND gate chip, a power supply module, and an EVCC control chip. An external CP input signal is connected with the input end of the PWM wave signal duty ratio detection circuit through the PWM wave signal voltage amplitude stabilizing circuit, and the output end of the PWM wave signal duty ratio detection circuit is connected with a first input pin of the AND gate chip. CP input signals are connected with a signal input end of the D trigger module, a signal output end of the D trigger module is connected with a second input pin of the AND gate chip, an output pin of the AND gate chip is connected with an enabling pin of the power supply module, and an output end of the power supply module is connected with a power supply input end of the EVCC control chip. According to the identification wake-up circuit provided by the utility model, the input power supply signal can be completely and accurately judged by detecting the duty ratio of the CP signal; and when the direct current power supply signal is identified, the EVCC control chip is awakened.

This invention relates to integrated circuit technology and includes a fixed wide pulse production unit, a detection unit, and a calculation unit. The detection unit comprises an oscillation signal output terminal, a first delay unit, and a second delay unit. The first delay unit includes at least two delay units connected in series at its beginning and end. One series connection point is connected to the oscillation signal output terminal. The end unit is connected to the output terminal of the second delay unit via a second detection interface, and the beginning unit is connected to the output terminal of the second delay unit via the first detection interface. A first switch is provided between the beginning and end of the first delay unit, and a second switch is provided between the input and output terminals of the second delay unit. This invention features low power consumption and a small area.

The application belongs to the technical field of signal processing, and discloses a digital peak-plateau double-channel shaping method and system for processing nuclear pulse signals, wherein the correlation between peak pulse shaping and plateau pulse shaping results is analyzed, and a peak-plateau double-channel shaping method is established; the severity of pulse pile-up is judged by using the peak pulse shaping channel, whether the pulse is reserved is judged, and the position of the pulse is determined; the peak value signal is provided by using the plateau shaping channel, and the pulse amplitude is extracted. The digital pulse amplitude analyzer adopting the peak-plateau double-channel shaping algorithm can identify and reserve the effective pulse amplitude in the pulse pile-up, so that the resolution of the nuclear energy spectrum is improved. The peak-plateau double-channel shaping method can effectively solve the problem of pulse pile-up in the nuclear energy spectrum measurement system, and greatly improves the count rate in the nuclear energy spectrum measurement. The application also has the advantages of high resolution, good shaping linearity and the like.

This invention provides a clock data recovery method and apparatus based on injection-locked oscillator. The method includes sampling an analog clock signal to obtain an initial sampled signal; detecting a clock error in the initial sampled signal to obtain a clock error signal; performing a first digital filtering process on the clock error signal to obtain a first clock control signal; acquiring a clock jitter estimate output from a digital filter within an injection-locked oscillator; injecting the clock jitter estimate into the clock error signal and performing a second digital filtering process; calculating a second clock control signal based on the clock signal after the second digital filtering process; and adjusting the phase of the sampled clock signal based on the first and second clock control signals. This invention also provides an apparatus for implementing the above method. The clock data recovery method of this invention has strong clock jitter tracking capability and low noise, and can be applied to next-generation communication technologies.

The application discloses an IGBT current rate peak extraction circuit, system and method, and the peak circuit comprises: a positive value translation circuit, which is used for shifting downward the detection waveform of the change rate of the power device switching transient current when the power device switching transient current drops; a negative value translation flip circuit, which is used for flipping and shifting downward the detection waveform of the change rate of the power device switching transient current when the power device switching transient current rises; a rectification amplification circuit, which is used for amplifying the voltage waveform at the peak after the treatment of the positive value translation circuit or the negative value translation flip circuit; a peak holding circuit, which is used for extracting and maintaining the maximum value of the voltage waveform; and an RC discharge equivalent circuit, which is used for equivalently discharging the extracted peak in the form of a capacitor-resistor discharge time. The application can extract the switching transient current change rate in real time, and is helpful to the online health analysis of the power module and the diode.

The invention discloses a pulse width detection circuit and a field programmable gate array, and belongs to the technical field of integrated circuits, the circuit comprises a time delay module, a serial-to-parallel conversion module and a control module, at least one of the time delay module and the serial-to-parallel conversion module is circuit-cured; the first input end of the time delay module is used for receiving a periodic first signal, the second input end of the time delay module is connected with the output end of the control module and used for receiving the control quantity output by the control module, and the output end of the time delay module is connected with the first input end of the serial-parallel conversion module and used for outputting a second signal; the output end of the serial-parallel conversion module is connected with the first input end of the control module and used for outputting first data, and the control module is used for determining the pulse width of the first signal based on the first data corresponding to the multiple different control quantities. The circuit can be simplified, resource occupation is reduced, cost is reduced, and interference from technology, voltage, temperature and power supply noise is small.

The invention provides a key detection method, a control device, electronic equipment and a storage medium. The method comprises the following steps: acquiring a level signal corresponding to a key; when it is detected that the level signal is changed from a first level to a second level, the level signal is monitored in a first preset phase discrimination window, the first level corresponds to a key release state, and the second level corresponds to a key press-down state; and if the level signals in the first preset phase discrimination window are all the second level signals, determining that the key is pressed down. According to the key detection method provided by the invention, when the level of the key is changed from the release state to the press-down state, the key is judged to be pressed down only when the level signals in the first preset phase discrimination window are all the second level, namely the press-down state, that is to say, the level signals are monitored in the first preset phase discrimination window, so that the detection accuracy of the key is improved. And whether the second level signal is stable is observed, so that misjudgment caused by key jitter is eliminated.

Apparatus, methods, and systems relate to an electrophysiology (EP) recording system for acquisition and preservation of cardiac electrical signals. The EP recording system provides defibrillator protection and radio frequency (RF) ablation signal noise suppression while preserving the integrity of relevant components of raw small signals. The EP recording system has a low-noise amplifier topology with minimal hardware filtering and a high-resolution A / D converter that provides clean, raw digital signals. The raw signals are filtered and processed by the EP system using software-based digital signal processing algorithms that allow the real-time display of signals as a raw signal, or as a combination of raw and processed signals simultaneously, in a single window or in multiple windows. The EP recording system allows for the synchronized display of signals with more than one signal processing algorithm applied at the same time, allowing a user to study signals filtered for specific purposes.

This invention relates to a high-speed signal acquisition system, specifically a single-channel wide dynamic range single fast pulse signal acquisition system, solving the technical problem of acquiring a large dynamic range of a single fast pulse P1. The single-channel wide dynamic range single fast pulse signal acquisition system provided by this invention includes a composite pulse train shaping circuit S1, a data acquisition unit S2, and an acquisition and restoration unit S3. The composite pulse train shaping circuit S1 includes a power divider circuit U1, N attenuation circuits U2, N analog delay circuits U3, and a composite circuit U4, where N is an integer greater than 1. The input terminal of the composite pulse train shaping circuit S1 receives a fast pulse P1, first splits the input fast pulse P1, then delays each of the split circuits, and finally combines them into a pulse train P2. Multiple samplings of the single fast pulse P1 signal are achieved within a short time using a single recording channel. Furthermore, by configuring different attenuation parameters for each split circuit, a large dynamic range of the single fast pulse P1 signal can be acquired.