207results about "Pulse descrimination" patented technology

The invention discloses a data sampling timing error evaluation method based on an evaluation model, relates to the technical field of timing error evaluation, and solves the problem that timing error evaluation is not accurate enough. Wherein the sampling module realizes undistorted receiving and clock signal frequency output of a clock signal through a CMOS clock input circuit, a third-order digital phase-locked loop circuit and a DSP digital signal processing chip, and a Fourier phase difference algorithm removes harmonic interference to solve a phase difference between the clock signal and an ideal clock signal; the clock signal feature recognition unit adopts a convolutional neural network to carry out iterative training on a training set of the timing error evaluation module to obtain an error evaluation module, the error evaluation module and the time migration algorithm module realize accurate calculation of a timing error value, and the timing error value calculation accuracy is greatly improved.

The invention provides signal detection equipment, system and method. The equipment comprises a clock module, an input module, a detection module and an output module, the input module comprises at least two analog-to-digital converters; the clock module is used for sequentially providing clock signals for the analog-to-digital converters of the input module according to corresponding phases; the input module is used for controlling each analog-to-digital converter to sample the current to-be-detected signal under the triggering of the corresponding clock signal, and performing analog-to-digital conversion to obtain a corresponding digital signal; combining the obtained digital signals according to a sampling time sequence to obtain a first digital signal; the detection module is used for carrying out detection processing on the first digital signal to obtain a second digital signal; and the output module is used for detecting the second digital signal in real time, and outputting the second digital signal if the second digital signal is detected to meet a preset jitter judgment condition. And detecting the signal in a complex noise environment to obtain a target signal.

The invention provides a method and a system for measuring pulse width. The method comprises the following steps of: inputting a pulse to be measured into a delay chain; if the pulse to be measured is a negative pulse, directly inputting the pulse to be measured into the delay chain; if the to-be-measured pulse is a positive pulse, inverting the to-be-measured pulse and inputting the to-be-measured pulse into the delay chain; a pulse to be measured is output in a delay chain through a plurality of taps in sequence in a delay manner, and an output signal of each tap of the delay chain is input to the corresponding two-stage D flip-flop; if the to-be-detected pulse output by a certain tap has a negative pulse signal, the corresponding two-stage D trigger outputs a high level; otherwise, outputting a low level; counting the number M of the two stages of D triggers outputting high level, and taking the sum of the reduced widths of negative pulses caused by the delay time of the first M taps on the delay chain propagation path as the width of the negative pulses; wherein M is a positive integer. The pulse compression technology is adopted, the dead time is short, and the resolution ratio is high.

The demodulation circuit includes a waveform regulator, a first counter, a second counter, and an SR latch. The waveform regulator generates a regulated modulation signal according to a pair of differential isolated modulation signals, which is generated according to a modulation of an input data signal with a carrier clock signal. The first counter counts cycles of the regulated modulation signal so as to generate a set signal. The second counter counts cycles of a reference clock signal so as to generate a reset signal. The SR latch includes a set terminal for receiving the set signal, a reset terminal for receiving the reset signal, and an output terminal for outputting a demodulated output signal. The SR latch is triggered by the set signal to pull up the demodulated output signal, and is triggered by the reset signal to pull down the demodulated output signal.

The invention provides a high-integration-level signal reading module for a neutron proportional counter tube, and belongs to the technical field of neutron detection, the high-integration-level signal reading module comprises stacked double-layer circuit boards, and the upper circuit board and the lower circuit board are connected through pin interfaces; the upper circuit board is provided with a signal processing circuit which is used for reading, amplifying, discriminating and shaping signals of the neutron proportional counter tube. The lower-layer circuit board is provided with a positive and negative dual-power-supply support circuit which provides + / -3.3 V power supply support for the signal processing circuit of the upper-layer circuit board. The module supplies power through the lower-layer power panel, and the lower-layer circuit board supplies positive and negative power to the upper-layer circuit board after completing power conversion. Signals are input through the IPX interface of the upper-layer circuit board and are output through the other IPX interface after being processed. The charge sensitive pre-amplifier, the broadband voltage amplifier, the pulse discriminator circuit, the pulse shaping circuit and the power management module are integrated in the same module, so that the real integrated design is realized.

The invention provides a pulse width modulation (PWM) signal capturing method and device and electronic equipment, and belongs to the technical field of electronic signals.The pulse width modulation (PWM) signal capturing method comprises the steps that when it is detected that the duty ratio of a pulse width modulation (PWM) signal is within an extreme duty ratio range, the PWM signal is captured; predicting an expected arrival time interval of the next expected edge according to a plurality of historical period parameters of the PWM signal in the sliding window; before the expected arrival time interval, the level state of the PWM signal is obtained according to a preset frequency, the synchronous count value of the timer when the expected level state is collected is recorded, and the preset frequency is higher than the timing frequency of the timer; and determining a current period parameter of the PWM signal according to the synchronous count value. The missed capture rate can be reduced when a single-channel timer is adopted to capture a PWM signal.

The invention discloses a high-voltage positive and negative pulse detection circuit, which relates to the technical field of signal conditioning, and is characterized in that a voltage division circuit is responsible for attenuating input pulse signals, a switching diode is responsible for rectification and inputting positive and negative pulse signals into corresponding conditioning circuits respectively, and a charging circuit is responsible for maintaining pulse width characteristics of the signals; and the steepness of the signal edge is ensured by the comparator, and FPGA identification can be realized. Uncertain high-voltage pulse signals can be processed, and application scenes are diversified. The edge characteristic, pulse width and pulse direction of the pulse signal can be identified, and the signal processing capability is prominent.

The embodiment of the invention discloses a clock detection circuit which is used in the technical field of clock detection. In the circuit, the input end of a level clock discrimination module is connected with a signal input end, and the output end of the level clock discrimination module is connected with a conduction control end of a second switch tube; the first output end of the second switch tube is connected with the input end of the capacitor charging and discharging unit, the second output end of the second switch tube is connected with the second input end of the current mirror, and the current mirror is used for driving a capacitor of the capacitor charging and discharging unit to charge and discharge; the output end of the capacitor charging and discharging unit is connected with the second comparison end of the current comparator module, the output end of the current comparator module is connected with the signal output end, and the current comparator module is used for comparing signals received by the first comparison end and the second comparison end and outputting a level signal of a comparison result. The current mirror is used for driving the capacitor of the capacitor charging and discharging unit to perform charging and discharging, and the current mirror has relatively large resistance, so that the clock detection circuit has a relatively small area under the condition of meeting low power consumption.

An active eye open monitor calibration apparatus and method for active eye open monitor calibration are provided. A reference clock signal and an eye open monitor clock signal are received and a calibration selecting signal is used to control whether the reference clock signal samples the eye open monitor clock signal. An indicator signal is output and received by a phase indicating determination circuit for performing a calibration flow and accordingly calculating a phase offset signal. The eye open monitor clock is corrected based on the phase offset signal, such that a calibrated eye open monitor clock signal is synchronously in phase with the reference clock signal. By employing the proposed eye open monitor calibration apparatus and method thereof, the invention is effective in achieving phase synchronization for an eye open monitor clock signal in related to its reference clock signal, solving the phase mismatch in the related arts.

The invention relates to a pulse width modulation (PWM) signal capturing method and device, a storage medium and a chip, the method can be applied to a processor, the method comprises the following steps: in response to trigger interruption, obtaining a signal identifier, an edge state, a first count value and a second count value corresponding to a PWM signal, the first count value is obtained by a count value of a first counter, and the second count value is obtained by a second counter; the second count value is a count value based on a second counter, the second counter is deployed in the memory, and the count range of the second counter is larger than that of the first counter; determining that the interruption is edge triggering and / or counting triggering; correcting the second count value according to the interruption as edge triggering and / or counting triggering, and / or determining the edge time of the PWM signal according to the second count value and the first count value; an interrupt is performed according to the edge time to capture the PWM signal. And the reliability of PWM signal capture can be effectively ensured.

The invention relates to the technical field of signal frequency measurement, in particular to a low-frequency-band fixed square wave frequency high-precision measurement method based on a kernel clock, which is suitable for the field of embedded systems and digital signal processing, is mainly used for low-frequency and fixed-frequency-band high-precision frequency measurement, and is not a frequency meter method specially used for measuring frequency. The method is suitable for measuring the fixed output frequency in a test system and the like. According to the method, a kernel clock of an embedded system (such as an STM32 single-chip microcomputer) is mainly utilized, a time constant is calibrated by measuring the count value of the duration of high and low levels of a fixed time window, and therefore the square wave frequency is obtained through calculation.

The invention relates to a pulse power amplifier detection control method and system, and belongs to the technical field of pulse power amplifier detection control. The signal sampling and processing module samples and converts forward radio frequency signals to obtain forward pulse digital voltage signals, samples and converts reverse radio frequency signals to obtain reverse pulse protection signals, and the reverse pulse protection signals serve as input of the detection control module composed of the MCU and the FPGA. In the detection control module, the MCU calculates a period counting threshold value and a high level counting threshold value based on the set maximum pulse width and the set maximum duty ratio and sends the period counting threshold value and the high level counting threshold value to the FPGA, and the FPGA detects and counts an obtained high level counting value exceeding the high level counting threshold value by detecting an input forward pulse digital voltage signal in a single detection period. According to the invention, fault control is started and detection is stopped only when the reverse pulse protection signal is determined to be at a high level or the reverse pulse protection signal is determined to be at a high level, and continuous detection is carried out by counting a clock cycle and repeatedly and circularly detecting a cycle, so that the problems of low precision, poor real-time performance, easy interference and high resource occupation in the prior art are solved.

Embodiments of the present disclosure provide a pulse signal monitoring circuit, a chip, and an electronic device. The circuit comprises a pulse monitoring module. The pulse monitoring module comprises: a pulse period monitoring module used for monitoring, on the basis of a reference clock signal, the period of a pulse signal to be tested and the period change between two adjacent periods; and a pulse duty ratio monitoring module used for monitoring, on the basis of the reference clock signal, the duty ratio of said pulse signal and the duty ratio change between two adjacent periods.

The demodulation circuit includes a waveform regulator, a first counter, a second counter, and an SR latch. The waveform regulator generates a regulated modulation signal according to a pair of differential isolated modulation signals, which is generated according to a modulation of an input data signal with a carrier clock signal. The first counter counts cycles of the regulated modulation signal so as to generate a set signal. The second counter counts cycles of a reference clock signal so as to generate a reset signal. The SR latch includes a set terminal for receiving the set signal, a reset terminal for receiving the reset signal, and an output terminal for outputting a demodulated output signal. The SR latch is triggered by the set signal to pull up the demodulated output signal, and is triggered by the reset signal to pull down the demodulated output signal.

An example apparatus includes: first current source circuitry having a terminal; a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor coupled to the terminal of the first current source circuitry, the control terminal of the first transistor coupled to the terminal of the first frequency multiplier circuitry; second current source circuitry having a terminal; a second transistor having a first terminal and a second terminal, the first terminal of the second transistor coupled to the terminal of the second current source circuitry; an inductor having a first terminal and a second terminal; a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the first terminal of the inductor; and an amplifier having a terminal coupled to the second terminal of the first transistor, the second terminal of the second transistor.

An electronic system (fig. 1: 10) is disclosed. The system has a differential signal generator (fig. 1: 100) configured to generate first and second single ended signals (fig. 1: D, DN) having opposite polarities. The input signal (fig 1: IN), and the first and second single ended signals transition between a first power voltage and a first ground voltage (fig. 1: Vdd1, Gnd1). The system also has a glitch management circuit (fig. 1: 200, fig. 4: 210, 220) configured to generate an output signal (fig. 1, 4: Out) based on the first and second single ended signals (fig. 1, 4: D, DN), where the output signal transitions between a second power voltage and a second ground voltage. The glitch management circuit includes a first latch (fig. 4: 210) configured to receive the first and second single ended signals (fig. 11, 4: D, DN), and to generate first and second intermediate signals (fig. 4: I, IB). The first and second intermediate signals each transition between the second power voltage and the second ground voltage. The system also has a second latch (fig. 4: 220) configured generate the output signal (fig. 1, 4: Out) based on the first and second intermediate signals.

The invention relates to a slope detector, an adaptive equalization circuit and electronic equipment. The slope detector comprises a first transistor and a second transistor, the grid electrode of the first transistor is connected with a first voltage input end, the grid electrode of the second transistor is connected with a second voltage input end, and the first transistor and the second transistor have the same channel width-to-length ratio; the positive electrode of the current source module is connected with the first electrode of the first transistor, the first electrode of the second transistor and the voltage output end, and the negative electrode is connected with the common end of the slope detector; the first end of the first inductor module is connected with the second electrode of the first transistor, and the second end is connected with the power supply voltage connecting end of the slope detector; the first end of the second inductor module is connected with the second electrode of the second transistor, and the second end is connected with the power voltage connecting end; and two ends of the capacitor module are respectively connected with the voltage output end and the common end. According to the invention, the signal bandwidth of the slope detector can be expanded.

The present application relates to a circuit and method for detecting clock anomalies, a clock circuit, a chip, and a radar. The circuit for detecting clock anomalies includes: a first clock frequency determination unit configured to determine a first clock frequency of a received first clock signal; a reference quantity determination unit configured to determine a reference quantity corresponding to the first clock signal, where the reference quantity is determined based on a second clock signal and / or a time stamp; and a clock anomaly detection unit connected to the first clock frequency determination unit and the reference quantity determination unit respectively, and configured to perform anomaly detection on the first clock signal based on the first clock frequency and the reference quantity. The present application can improve the reliability of the clock signal, thereby enhancing the personal safety and property safety of users.

Provided are a malicious attack protection circuit, a system-on-chip including the same, and an operating method thereof. The malicious attack protection circuit includes a reference interrupt generator to output a reference interrupt signal every reference interrupt period, a variable clock manager for outputting an operating clock signal to a logic circuit outside the malicious attack protection circuit and a variable clock signal having a variable period, a variable interrupt generator to output an interrupt signal every variable interrupt period based on the variable clock signal, a comparison circuit to compare the reference interrupt signal with the interrupt signal and output a comparison result signal, and a controller that interrupts the output of the operating clock signal input to the logic circuit, according to the comparison result signal.

The invention relates to an exception handling circuit and exception handling method for clock data recovery. According to the method and the device, the data sender can be supported to implement data scrambling with direct current balance as a target on the target data to be transmitted, so that the data receiver can receive scrambled data with a direct current balance characteristic through a physical channel. On the basis, periodic samples of sampled data obtained by sampling the scrambled data by a data receiver can be obtained, and when it is judged that a sampling clock phase of the scrambled data is locked at a false eye position in an eye pattern of the scrambled data according to periodic direct-current unbalance deviation of a plurality of continuous periodic samples, the scrambled data is locked at the false eye position in the eye pattern of the scrambled data. According to the method, the phase of the sampling clock can be separated from the false eye position by implementing unlocking phase adjustment on the phase of the sampling clock, so that the dynamic calibration of the phase of the sampling clock can be recovered in time, and the failure risk of clock data recovery can be reduced.

The circuit device includes an output terminal, an output transistor, and a gate voltage control circuit. The output transistor is disposed between the first power supply node and the output terminal. After the input signal (TX) transitions from a first logic level to a second logic level, the gate voltage control circuit causes the gate voltage of the output transistor to change at a first time-voltage change rate. After the gate voltage reaches a first determination voltage, the circuit causes the gate voltage to change at a second time-voltage change rate that is smaller than the first time-voltage change rate. After the gate voltage reaches a second determination voltage, the circuit causes the gate voltage to change at a third time-voltage change rate that is larger than the second time-voltage change rate.

This invention relates to the field of high-resolution time measurement systems and integrated circuit technology, providing a time measurement circuit with a two-dimensional address-modulated TOT pulse, comprising: a common-gate transimpedance amplifier, a high-speed high-gain comparator, a current-mode logic output stage, a common-mode feedback threshold setting circuit, and a two-dimensional address-modulated TOT pulse circuit; the address modulation pulse circuit includes an address modulation pulse width circuit and an address modulation pulse amplitude circuit, wherein the address modulation pulse width circuit includes: multiple sets of first modulation units, multiple sets of second modulation units, multiple inverters, and multiple bits of first digital code; the address modulation pulse amplitude circuit includes: multiple sets of third modulation units and multiple bits of second digital code. This invention allows a single TOT signal to simultaneously carry time information, energy information, and address information, reducing wiring, improving reliability, and increasing integration density.

The embodiment of the present application provides a pulse signal monitoring circuit, chip and electronic device, the circuit includes: a pulse monitoring module, the pulse monitoring module includes: a pulse period monitoring module, which is used to monitor the period of the pulse signal to be tested and the period change between two adjacent periods based on a reference clock signal; a pulse duty cycle monitoring module, which is used to monitor the duty cycle of the pulse signal to be tested and the duty cycle change between two adjacent periods based on a reference clock signal. The embodiment of the present application can monitor pulse signals with any duty cycle, which solves the problem in the related art that pulse signals with a duty cycle other than 50% cannot be monitored, and can improve the system applicability and enhance the system stability.

An apparatus and a method for facilitating a first frequency filtering and a second frequency filtering together with non-reciprocal frequency conversion for electromagnetic isolation.

An example apparatus includes; first current source circuitry (270) having a terminal; a first transistor (275) having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor coupled to the terminal of the first current source circuitry, the control terminal of the first transistor coupled to the terminal of the first frequency multiplier circuitry (200); second current source circuitry (250) having a terminal; a second transistor (260) having a first terminal and a second terminal, the first terminal of the second transistor coupled to the terminal of the second current source circuitry; an inductor (296) having a first terminal and a second terminal; a capacitor (292) having a first terminal and a second terminal, the first terminal of the capacitor coupled to the first terminal of the inductor; and an amplifier (265) having a terminal coupled to the second terminal of the first transistor, the second terminal of the second transistor.

An electronic system and a method of using the electronic system are disclosed. The system includes a differential signal generator configured to generate a first single-ended signal and a second single-ended signal having opposite polarities. The input signal and the first and second single-ended signals transition between a first power supply voltage and a first ground voltage. The system also includes a glitch management circuit configured to generate an output signal based on the first and second single-ended signals. The output signal transitions between a second power supply voltage and a second ground voltage. The glitch management circuit includes a first latch configured to receive the first and second single-ended signals and generate first and second intermediate signals. The first and second intermediate signals each transition between the second power supply voltage and the second ground voltage. The system also includes a second latch configured to generate an output signal based on the first and second intermediate signals.

A comparator circuit includes a first transistor (206), a second transistor (208), a first switch (210), a second switch (212), and a timing circuit. The first transistor (206) and the second transistor (208) are coupled as a differential pair and are configured to compare an input signal with a hysteresis voltage. The first switch (210) is coupled to the first transistor (206) and is configured to selectively enable the first transistor (206). The second switch (212) is coupled to the second transistor (208) and is configured to selectively enable the second transistor (208). The timing circuit is coupled to the first switch (210) and the second switch (212) and is configured to close the first switch (210) in response to a signal transition at the output of the comparator circuit and to close the second switch (212) a predetermined delay time after the first switch (210) is closed.

The invention discloses a second pulse detection protection circuit, system and method and a vehicle. The second pulse detection protection circuit comprises a second pulse transmission module, an input signal detection module and an output signal detection module. The second pulse transmission module outputs a second pulse signal, the input signal detection module outputs a second pulse sampling signal I, the input end of the output signal detection module is connected with the output end of the second pulse transmission module, and the output signal detection module outputs a second pulse sampling signal II; the positioning module is used for judging whether to generate the second pulse signal based on the second pulse sampling signal I and selecting to generate the second pulse signal, and judging whether to stop generating the second pulse signal and whether to output the second pulse signal based on the second pulse sampling signal I and the second pulse sampling signal II. According to the invention, accurate second pulse signals can be obtained in real time.

The invention relates to a transmission device (100) comprising two galvanically isolated sub-circuits (110, 50). The first sub-circuit (110) comprises a carrier signal source (116) for outputting a carrier signal, a digital signal source (112) for outputting a binary signal level, and a logic component (118) for performing an AND operation on two input signals, the logic component having two logic inputs and a first logic output (130), the logic inputs being connected to the signal level output and the carrier signal source output, respectively. The second sub-circuit (150) comprises a signal input (154), a signal output (164), and a first RC element (160, 162), the signal input (154), the signal output (164), and the RC element (160, 162) being connected in parallel with respect to a second reference potential. A first isolation capacitor (202) is connected between the first logic output and the signal input for galvanic isolation. A second isolation capacitor (204) is connected between a first reference potential and the second reference potential for galvanic isolation.

The present application relates to a duty cycle imbalance correction circuit and an optoelectronic terminal device. The duty cycle imbalance correction circuit is used to connect to the front-stage circuit of the optical receiving end, and the front-stage circuit of the optical receiving end outputs an electrical signal according to the received optical signal. The duty cycle imbalance correction circuit includes a detection and correction module, a correction and adjustment module, and an output buffer processing module. The detection and correction module is connected to the front-stage circuit of the optical receiving end, and is used to receive the electrical signal and output a correction current that matches the power of the optical signal according to the electrical signal. The correction and adjustment module is connected to the front-stage circuit of the optical receiving end and the detection and correction module, and is used to receive the electrical signal and output an adjusted signal after duty cycle imbalance correction according to the electrical signal and the correction current. The output buffer processing module is connected to the correction and adjustment module, and is used to perform shaping processing on the adjusted signal to obtain a processed output signal. The duty cycle imbalance correction circuit is applicable to application scenarios where optical signals quickly switch between different optical powers in burst mode.