31 results about "Glitch removal" patented technology

A method and apparatus for canceling noise from track cross signal includes binarizing the track cross signal with reference to at least two reference values, and removing noise from the binarized track cross signal based on a command speed according to which a tracking actuator moves a pickup. Accordingly, it is possible to remove noise from a track cross signal so as to obtain information regarding precise speed of track searching or position on the track, irrespective of the searching speed.

The invention relates to a PWM (Pulse-Width Modulation) complementary output method of inserting variable dead zone time, which belongs to a control technology of a three-phase bridge type inverter circuit and is realized by three groups of same control circuits. Each group of circuit comprises an edge detecting unit, a dead zone time setting register, a counting unit, a dead zone time inserting unit and two D triggers for outputting complementary signals. The edge detecting unit firstly detects a PWM input signal, and generates an edge change mark signal CF when the waveform changes. A 'or' relation is established among phases of an output value of a counter, and then a 'or' relation is established with the CF to obtain an enabling control signal of the counter. In the counter unit, whena counted value is equal to a set value, the counted value is synchronized and reset to 0. The dead zone time inserting unit modifies the PWM input signal according to EN (European Norm), the dead zone is inserted into the PWM input signal, and burr is eliminated by the D trigger to obtain a complementary PWM signal to output. The invention has simple circuit, and is suitable to be integrated to a microcontroller provided with a PWM waveform generator, and the dead zone time can be adjusted in a wide range.

The present invention provides a system for eliminating a burr phenomenon of a magnetic displacement sensor during rail state monitoring. The entire system can be integrated on an FPGA chip; each magnetic displacement sensor is controlled by a clock pulse generation module to carry out data collection in different monitoring periods, and convert the format and complete data output in the next monitoring period. Through the above design, the delay and synchronization in the measurement engineering can be strictly controlled, so that the magnetic displacement measurement accuracy only depends onthe high-speed, high-stability, high-precision clock reference and design algorithm, thereby avoiding the problems of complexity, instability, temperature drift and requirement for calibration when the traditional analog magnetic displacement sensor processes the low-level signals, and greatly improving the measurement precision. Since the whole system is synchronized to one clock, the logic timing sequences in the system are synchronized, thereby realizing time-sharing serial output of multichannel data in different measurement periods, which can prevent logic competition and remove the burrs.

The invention provides a glitch removal circuit and an electronic device. The glitch removal circuit can remove glitch noise contained in a Power-on reset signal. The glitch removal circuit removes glitch noise contained in a Power-good signal and a Power-on Reset signal, and includes: a first glitch removal unit that operates according to a first clock signal, and removes glitch noise from a Power-good signal; and a second glitch removal unit that operates according to a second clock signal, and removes glitch noise from a Power-on Reset signal, in which the first glitch removal unit is configured so as to be initialized according to an output signal of the second glitch removal unit, and the second glitch removal unit is configured so as to be initialized according to an output signal ofthe first glitch removal unit.

The invention relates to a serially cascaded single-bit filter structure for eliminating spur signals, comprising: a serially cascaded single-bit filter module, a loop counter circuit, a metastable elimination circuit; a serially cascaded single-bit filter module The filter module further includes a first-level single-bit filtering module, a second-level single-bit filtering module, a third-level single-bit filtering module... an nth-level single-bit filtering module; The original data disturbed by the glitch signal is recovered from each sampled data, and the design of eliminating glitch signals of different widths is realized by cascading single-bit filters in series, and the pulse signals of different sampling clock widths are filtered out step by step; The traditional equal time interval sampling scheme cannot correctly restore the insufficiency of the equal time interval glitch signal, and a general glitch signal elimination circuit is realized.

The present invention discloses a burr eliminating circuit which comprises a delay module which is used for detecting the width of the burr and a delay output module for eliminating the burr problem generated in specific condition. The delay module is connected with a feedback control circuit module. The delay module controls the feedback control circuit module to reset with an accelerated speed when the burr is detected and sets with an accelerated speed when the valid data is detected. The circuit of the invention totally satisfies the functions of determining and eliminating the burr and can expands the width of the valid narrow pulsewidth signal to a safe width for securing the safe operation.

A glitch removal circuit removes glitch noise contained in a Power-good signal and a Power-on Reset signal, and includes: a first glitch removal unit that operates according to a first clock signal, and removes glitch noise from a Power-good signal; and a second glitch removal unit that operates according to a second clock signal, and removes glitch noise from a Power-on Reset signal, in which the first glitch removal unit is configured so as to be initialized according to an output signal of the second glitch removal unit, and the second glitch removal unit is configured so as to be initialized according to an output signal of the first glitch removal unit.

The invention relates to a vibration key-phase signal preprocessing method of a turbo generator set in a large-scale thermal power plant. The method comprises the following steps of: eliminating burr interference through voltage triggering; meanwhile, further eliminating the burr interference in key-phase pulses by means of the optoelectronic isolation of an integrated circuit; and finally shaping square waves. The processing method proposed by the invention can effectively eliminate various burr interferences, obtain accurate key-phase square-wave signals, achieve the aim of processing the key-phase signals of different kinds of sensors in different power plants and provide a site with key-phase signals which are more accurate and convenient to analyze.