8 results about "Glitch removal" patented technology

The invention provides a UCIe-based data transmission method, a storage medium and an artificial intelligence chip. The data transmission method comprises the following steps: communicating with a second core particle through a first core particle; receiving a bypass receive data signal and a bypass receive clock signal from the transmit module of the first core particle through the receive module of the second core particle; the serial-to-parallel conversion module is used for transmitting the bypass receiving data signal and the bypass receiving clock signal to the second core particle through the receiving module; counting the bypass receiving clock signal through a serial-to-parallel conversion module to obtain a bypass receiving frame count value, and sampling a bypass receiving data signal according to the bypass receiving frame count value; a serial-to-parallel conversion module decides to count a bypass burr removal count value according to a bypass burr removal counter starting signal; and when the bypass glitch removal count value is equal to the bypass glitch removal counter threshold value, resetting the bypass receiving frame count value through the serial-to-parallel conversion module. According to the invention, good data transmission quality among the core particles can be realized.

The present disclosure provides a digital display control buffer circuit and a digital display control buffer apparatus. The digital display control buffer circuit at least includes a glitch removal circuit, a first comparison unit, a second comparison unit and a first switch device; a first end of the first switch device and a first input end of the second comparison unit are used to input an upstream signal of the digital display control buffer circuit, a first input end of the first comparison unit is used to input a downstream signal of the digital display control buffer circuit; the glitch removal circuit is used to output a control signal to the control end of the first switch device when a first signal outputted by the output end of the second comparison unit is a falling edge, such that the first switch device is turned off.

A voltage regulator circuit for supplying a voltage to an input of a subsequent circuit element, the voltage regulator circuit comprising: a power supply, an output adapted to deliver a regulated output voltage, a first transistor connected between the power supply and the output for controlling the output voltage, a differential amplifier configured to provide a feedback to the first transistor, a protective circuit which is coupled to the gate of the first transistor and configured to control the first transistor, such that the turn-on of the first transistor is delayed and any overshoot output voltage is avoided at the output during an initial charging up phase after the power supply is turned on.

A glitch removal circuit is configured to receive a first voltage and a detection signal indicating the status of a second voltage that is lower than the first voltage. The glitch removal circuit outputs a missing low-voltage signal when the first voltage is present and the second voltage is absent. The glitch removal circuit may be incorporated into a power check circuit of a power supply independent sequence system, such as by modifying one or more power ok signals that are sent to an input / output circuit of the system. The input / output circuit may include a power mux circuit coupled to a selection signal generated by the power check circuit. The power mux circuit may be configured to output an intermediate voltage between the first voltage and a reference ground voltage generated from the first voltage of the second voltage according to the selection signal.

A glitch removal circuit is configured to receive a first voltage and a detection signal indicating the status of a second voltage that is lower than the first voltage. The glitch removal circuit outputs a missing low-voltage signal when the first voltage is present and the second voltage is absent. The glitch removal circuit may be incorporated into a power check circuit of a power supply independent sequence system, such as by modifying one or more power ok signals that are sent to an input / output circuit of the system. The input / output circuit may include a power mux circuit coupled to a selection signal generated by the power check circuit. The power mux circuit may be configured to output an intermediate voltage between the first voltage and a reference ground voltage generated from the first voltage of the second voltage according to the selection signal.

The example multi-path digital microphones described in this application can include example embodiments of adaptive ADC range multi-path digital microphones that allow for low power for the amplifier or gain stage and example adaptive ADCs in the example multi-path digital microphone arrangements described herein while still providing a high DR digital microphone system. Additional non-limiting embodiments can include example glitch removal components configured to minimize audible artifacts associated with changes in gain for the example adaptive ADCs.

The invention relates to a glitch optimization digital-to-analog converter and a slope compensation circuit. The glitch optimization digital-to-analog converter comprises a thermometer decoder, a synchronous circuit module, a bit control signal generation module, a pull-up or pull-down pulse generation module, a pull-up or pull-down circuit and an R2R circuit. A bit control signal generation module, a pull-up or pull-down pulse generation module and a pull-up circuit or a pull-down circuit are arranged in the digital-to-analog converter, so that the output burr directions of the digital-to-analog converter are uniformly upward or downward, and normal overturning of a first edge of a voltage comparator is ensured; the stable operation of the slope compensation system of the power supply can be ensured under the condition that burrs do not need to be eliminated.

This invention belongs to the field of key phase signal processing technology, specifically relating to a high-stability key phase signal conversion circuit. The circuit includes a signal conditioning and filtering unit, a threshold setting unit, a threshold comparison unit, and an output interface. The signal conditioning and filtering unit is equipped with an operational amplifier AU1 for adjusting amplitude, suppressing noise, and removing glitches, along with a resistor-capacitor filter circuit. The operational amplifier AU1 is connected to the resistor-capacitor filter circuit and to the threshold setting unit. The threshold setting unit is connected to the threshold comparison unit. The threshold comparison unit is connected to the output interface and to both the resistor-capacitor filter circuit and the operational amplifier AU1. This invention achieves the technical effects of amplitude adjustment, noise suppression, and glitches removal for key phase signals.