30 results about "Glitch removal" patented technology

A method and apparatus for design-for-low-power of register transfer level (RTL) controller/data path circuits that implement control-flow intensive specifications. The method of the invention focuses on multiplexer networks and registers which dominate the total circuit power consumption and reduces generation and propagation of glitches in both the control and data path parts of the circuit. Further the method reduces glitching power consumption by minimizing propagation of glitches in the RTL circuit through restructuring multiplexer networks (to enhance data correlations and eliminate glitchy control signals), clocking control signals, and inserting selective rising/falling delays, in order to kill the propagation of glitches from control as well as data signals. To reduce power consumption in registers, the clock inputs to registers are gated with conditions derived by an analysis of the RTL circuit, ensuring that glitches are not introduced on the clock signals.

The invention discloses a method and device for eliminating signal noise, the device includes a backward-forward counter and a signal output circuit; the method for eliminating signal noise has the following steps: 1) setting valid and invalid level counting thresholds; 2) receiving the signal with signal noise needed to be eliminated by the backward-forward counter and beginning to count; when the rising edge of each clock arrives, if the signal is an valid electrical level, adding one on the current counting value, otherwise subtracting one; and the counting value does not increase/decrease until it reaches to a valid/invalid level counting threshold; meanwhile, the signal output circuit outputs signal without noise according to the counting value: when the rising edge of each clock arrives, if the counting value is a valid/invalid level counting threshold, then outputting valid/invalid level; if the counting value is between the valid and invalid level counting threshold, keeping the output equal to the output of the previous clock. The device provided by the invention can thoroughly eliminate wide noise, stably output signal without noise, and which is simple to be realized, thereby improving reliability of the system.

More accurate signal detection circuitry in serial interfaces, particularly on a programmable integrated circuit device, such as a PLD, includes a high-speed, high-resolution, high-bandwidth comparator, along with digital filtering, to reduce the effect of process, temperature or supply variations. The comparator is used to compare a direct input signal with a programmable reference voltage, and, in a preferred embodiment, can detect the signal level within 8 mV accuracy. The output of the comparator may then be digitally filtered. Preferably, both a high-pass digital filter and a low-pass analog filter may be used to eliminate glitches and low-frequency noise. Preferably, the digital filters are programmable to adjust the sensitivity to noise. The filtered output is then latched and output to indicate receipt or loss of signal. This signal detect circuitry can operate reliably at data rates as high as 7 Gbps.

A method for removing bur off includes automatically closing turnover function by turnover follow-up circuit when turnover output level is turned over, having a preset time delay under control of turnover control circuit then starting turnover function of turnover follow-up circuit. The device for realizing said method is also disclosed.

Provided are a method and apparatus for canceling noise from a track cross signal, a method for controlling an optical disc drive, an optical disc drive, and an optical disc reproducing apparatus. The method for removing noise from a track cross signal includes (a) removing noise from the track cross signal by binarizing the track cross signal with reference to hysteresis set values that are determined according to a command speed for a tracking actuator; and (b) removing glitch noise from the binarized track cross signal based on a predetermined time value. Accordingly, it is possible to effective remove noise to obtain information regarding the precise speed and position of a desired track.

The invention provides a novel transient response enhanced LDO. The novel transient response enhanced LDO comprises an error amplifier EA, an adjusting tube MP, feedback resistor networks RA and RB, a feedback capacitor CA, a load capacitor CL and a load resistor Rout. A transient response enhancement circuit TRANSIENT ENHANGCE is connected between the error amplifier EA and the grid electrode of the adjusting tube MP, and the TRANSIENT ENHANGCE comprises a hysteresis comparator, an ONE_SHOT and two NMOS tubes MN1 and MN2. The hysteresis comparator is used for collecting and comparing the drain voltage of the input differential pair transistor of the error amplifier EA, burrs of the obtained comparison result are eliminated through the ONESHOT, and the anti-noise performance of transient enhancement is improved. And the grid voltage of the adjusting tube MP is adjusted through the NMOS tube, so that the effect of enhancing the transient response of the load is achieved.

A glitch removal circuit removes glitch noise contained in a Power-good signal and a Power-on Reset signal, and includes: a first glitch removal unit that operates according to a first clock signal, and removes glitch noise from a Power-good signal; and a second glitch removal unit that operates according to a second clock signal, and removes glitch noise from a Power-on Reset signal, in which the first glitch removal unit is configured so as to be initialized according to an output signal of the second glitch removal unit, and the second glitch removal unit is configured so as to be initialized according to an output signal of the first glitch removal unit.

Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.

When a signal glitches, logic receiving the signal may change in response, thereby charging and/or discharging nodes within the logic and dissipating power. Providing a glitch-free signal may reduce the number of times the nodes are charged and/or discharged, thereby reducing the power dissipation. A technique for eliminating glitches in a signal is to insert a storage element that samples the signal after it is done changing to produce a glitch-free output signal. The storage element is enabled by a 'ready' signal having a delay that matches the delay of circuitry generating the signal. The technique prevents the output signal from changing until the final value of the signal is achieved. The output signal changes only once, typically reducing the number of times nodes in the logic receiving the signal are charged and/or discharged so that power dissipation is also reduced.

The invention discloses a high-precision clock phase control circuit, relating to the field of electronic circuits. The high-precision clock phase control circuit comprises a multi-phase clock generation circuit module and a programmable phase selection circuit module, wherein the clock generation circuit module comprises a plurality of phase selection circuits, and each phase selection circuit comprises at least one selection unit and at least one protection unit; the programmable phase selection circuit module comprises a plurality of many-way selection units and phase combination circuits, and each many-way selection unit is respectively communicated with each phase combination circuit. According to the high-precision clock phase control circuit, the multi-phase clock generation circuit module and the programmable phase selection circuit module are combined, so that the high-precision clock phase control circuit has the advantages of simple structure, low cost, high sensitivity and higher precision, and the specific clock switching method can be used for eliminating burr phenomena, and the signal quality and precision are improved.

The invention relates to a clock detection circuit and method, and the circuit comprises a glitch elimination unit, a first counter, a second counter, and a detection unit, and the glitch elimination unit is used for inputting a to-be-detected clock signal, and eliminating the glitch of the to-be-detected clock signal, so as to obtain a first signal; the first counter records a first jump edge parameter of the first signal; the second counter records a second jump edge parameter, with the same type as the first jump edge parameter, of the second signal; the second signal is synchronized with the first signal after being synchronized; the detection unit judges whether the first jump edge parameter and the second jump edge parameter are the same or not and outputs a signal used for detecting whether burrs exist in the to-be-detected clock signal or not according to the judgment result. Whether burrs exist in the clock signal to be detected or not is detected by comparing the jump edge parameters of the clock signal without the burrs and the original clock signal without the burrs, the clock signal to be detected can be used for detection, an external clock is not needed, and the detection precision is improved.

An electronic device according to the present disclosure is an electronic device having a function of removing glitches contained in a signal, and includes a glitch removal circuit which removes glitches from an inputted signal, and a count unit which counts a number of times removing glitches.