97 results about "Register-transfer level" patented technology

The invention discloses a memory combination screening method, device and equipment and a medium, and relates to the technical field of computers, and the method comprises the following steps: generating all memory files of a system-on-chip according to a preset memory naming rule; storing each memory file to a target memory library, obtaining all memory names based on the register transfer level code and a preset memory naming rule, and generating a memory list based on each memory name; acquiring corresponding physical parameter information from a target memory library based on each memory name in the memory list, and determining target physical parameter information of each memory split combination corresponding to each memory according to the physical parameter information; and screening the memory split combination based on a preset physical information threshold and the target physical parameter information to obtain a screened memory combination. According to the method and the device, the memory list can be quickly and accurately generated, and all combinations meeting constraints are screened out.

The embodiment of the invention discloses a chip verification environment generation method and system, electronic equipment and a storage medium, relates to the technical field of integrated circuit verification, can adapt to verification environments with different configurations, and improves verification efficiency. The method comprises the following steps: constructing or calling a verification environment template; analyzing the initial configuration information and the routing topology information, and generating a target configuration file according to an interface protocol and an interconnection rule of a register transfer level and a model; the routing topology information indicates an interconnection link topology structure between the devices, and the target configuration file indicates a component type corresponding to each device required by simulation forming of each interconnection link and a matched verification component type; loading and instantiating the register transfer level component and the model component based on the verification environment template according to the component type; and according to the verification component type, interconnection is carried out between the register transfer level component and the model component through the verification component, and a chip executable verification environment is generated. The method and the device are suitable for a scene for constructing a chip verification environment.

The invention relates to a training method and device of a binary neural network model and computer equipment. The method comprises the steps that enhanced thermometer coding is introduced into an input layer of a small sample image recognition model, and a binary neural network model is designed by adopting a batch-free normalized convolutional layer; inputting a to-be-predicted picture to the binarization neural network model to extract to-be-predicted features, performing first-stage training on the to-be-predicted features by using the original activation function and the weight, and performing second-stage training on the predicted picture input to the trained binarization neural network model by using the binarized original activation function and the weight, and obtaining an optimal binary neural network model. And deploying the optimal binary neural network model into a C language reasoning framework, completing system module development, and obtaining edge device adaptation information. And designing a register transfer level process of the target edge device. By adopting the method, the efficient and lightweight performance of deep learning of the resource-limited edge device can be improved.

The invention relates to the technical field of computers and provides a method for detecting a register transfer level code, electronic equipment and a medium. The method comprises the following steps: determining the code maturity of a first register transfer level code according to a code maturity index; determining a first chip development stage matched with the first register transfer level code based on the code maturity corresponding to each of the plurality of chip development stages; when the first chip development stage is an acceptance stage, carrying out the quality detection of the front-end design process through the comprehensive verification tool according to the quality detection item of the comprehensive verification tool; and when the first chip development stage is not the acceptance stage, configuring the comprehensive verification tool according to configuration environment input to obtain a configured comprehensive verification tool, and then performing quality detection of the front-end design process according to the quality detection items included in the rapid quality detection item set through the configured comprehensive verification tool. In this way, correctness is ensured, and iteration efficiency is improved.

Examples relate to an apparatus, a device, a method, and a computer program for generating a register transfer level (RTL) representation of a circuit. The apparatus comprises processing circuitry configured to generate a graph representation of the circuit, the graph representation comprising a first set of vertices representing operators and a second set of vertices representing operands of the RTL representation of the circuit. The processing circuitry is configured to determine, for one or more operators represented by the one or more vertices of the first set of vertices of the graph, one or more logically equivalent operators. The processing circuitry is configured to include the one or more logically equivalent operators in the graph representation, such that the graph representation comprises a plurality of logically equivalent representations of the circuit. The processing circuitry is configured to generate an RTL representation of the circuit based on one of the plurality of equivalent representations of the circuit.

The invention discloses a register model and register transfer level generation and test method, device, equipment and medium, and relates to the technical field of integrated circuit design verification, and the method comprises the following steps: analyzing a comma separation value table file by using a register generation platform to generate a register model, a register transfer level and a register test vector; the comma separation value table file is a file used for describing register information; generating a general verification methodology environment by using a test environment generation platform, and integrating the general verification methodology environment based on the register model, the register transfer level and the register test vector to obtain a corresponding integrated test environment; and compiling the integrated test environment, if the compiling is successful, running the register test vector in the integrated test environment which is successfully compiled, and outputting a corresponding test result. Therefore, the automation degree of register model verification can be improved, and the verification efficiency of front-end verification is improved.

The invention relates to the technical field of chip verification, in particular to a front-end low-power-consumption verification environment generation method, electronic equipment and a medium, and the method comprises the steps: S1, obtaining register transfer level code information An and unified power consumption format information Bn of a chip; s2, acquiring a target configuration file; s3, analyzing the target configuration file, if Cn is set as a first identifier, adding A1n and B1n into a target compiling file list, and if Cn is set as a second identifier, adding A2n and B2n into the target compiling file list; s4, screening the standard cell library information file corresponding to at least one process corner from each standard cell library information file, and adding the standard cell library information file into a target compiling file list; and S5, compiling and generating a front-end low-power-consumption verification environment based on the target compiling file list. According to the invention, the generation efficiency and accuracy of the front-end low-power-consumption verification environment are improved.

The invention provides a code processing method and device of an integrated circuit, electronic equipment and a storage medium. The method comprises the steps that a source code is obtained, the source code comprises parameter information of a sub-module in the integrated circuit, and the source code is a register transfer level code; constructing a structured encapsulation unit tree based on the source code; packaging the structured packaging unit tree according to a high-level hardware description language to obtain a structured object; instantiating the structured object to obtain a hardware description language module; and in response to the received connection instruction, code generation is performed based on the connection instruction and the hardware description language module to obtain a connection code, the connection instruction comprises a connection relationship between the sub-modules in the integrated circuit, the connection code indicates a signal transmission path between the sub-modules in the integrated circuit, and the connection code is a hardware description language code. According to the invention, the connection efficiency of signal transmission paths between modules in an integrated circuit design can be improved.

The invention discloses a method and a system for checking a time sequence path based on logic depth splitting. The method comprises the following steps: acquiring the logic depth of the time sequence path; splitting the logic depth to obtain a buffer and inverter level and a register transfer level (RTL) level; based on the logic depth, a buffer and inverter level, and a register transfer level (RTL) level, a timing problem source is located. According to the time sequence path inspection method and system provided by the invention, the logic depth is divided into the buffer and inverter level and the RTL level, and the source of the time sequence problem is accurately positioned, so that the time sequence convergence efficiency is improved, and the chip design complexity is reduced.

The invention provides a low-power-consumption simulation method and device, equipment, a storage medium and a program product, and relates to the technical field of integrated circuits. The method comprises the following steps: determining an initial comprehensive model of a register transfer level corresponding to a to-be-simulated chip; based on the initial comprehensive model, determining a target comprehensive model corresponding to the to-be-simulated chip; according to the initial gate-level netlist corresponding to the to-be-simulated chip, generating a target gate-level netlist corresponding to a power supply loop in low-power-consumption simulation; and based on a preset hardware simulation accelerator, performing low-power-consumption simulation including a power supply loop on the target synthesizable model and the target gate-level netlist. According to the method, the low-power-consumption simulation convergence time is greatly shortened, and the simulation efficiency is improved.

The invention provides a post-simulation method of an integrated circuit, electronic equipment and a storage medium, and relates to the technical field of chip design. The method comprises the following steps: based on a static time sequence analysis STA environment, obtaining a static time sequence analysis result of a physical implementation PR netlist corresponding to a register transfer level RTL module in a target integrated circuit; according to a static time sequence analysis result, obtaining an average clock network delay corresponding to an interface register in the PR netlist, a target establishment time and a target retention time of each input interface signal and a target output delay of each output interface signal, and constructing an interface signal delay model corresponding to the RTL module according to the average clock network delay, the target establishment time and the target retention time of each input interface signal and the target output delay of each output interface signal; according to the interface signal delay model and the RTL module, post-simulation processing is carried out, the interface signal delay model matched with the RTL module in time sequence can be constructed, in addition, the interface signal delay model can be combined with the RTL module to reduce the verification scale of a whole chip, the verification efficiency is improved, and the verification process is simplified.

The embodiments described herein implement a protocol decoder tool designed by a hardware engineer in a hardware description language (HDL) in a simulator tool for testing and / or in a signal analysis system for decoding protocols in real-time. For example, a user (e.g., hardware engineer, hardware designer, protocol designer) may design a protocol using an HDL and design a protocol decoder tool for decoding the protocol in the HDL. Register transfer level (RTL) files with protocol decoder logic in the HDL may be converted from the HDL to a second language by a converter, compiled into a decoder module by a compiler, and executed in a signal analysis system as the protocol decoder tool. As such, errors in misinterpretation of protocol specifications may be reduced.

The invention relates to the technical field of integrated circuits and provides a chip verification method, computer equipment, a medium and a chip verification platform. The method comprises the following steps: based on test content of a first test point, selecting a necessary subsystem module associated with the first test point in a plurality of subsystem modules which are designed by a first chip and are integrated on a system top layer; identifying other subsystem modules except the necessary subsystem module associated with the first test point in the plurality of subsystem modules as unnecessary subsystem modules associated with the first test point; performing register transfer level compilation and emulation verification of test content for a first test point, including instantiating a chip top layer control module integrated on a chip top layer of a first chip design, instantiating a necessary subsystem module associated with the first test point, and performing a first test point design; and performing virtual module replacement operation on the unnecessary subsystem module associated with the first test point. In this way, compiling and simulation time is shortened, and verification efficiency is improved.

The present application relates to the technical field of field programmable gate array circuits, and discloses a method and system for optimizing FPGA technology mapping. The method first divides the input register transfer level circuit into several sub-circuits, and then transmits the user-specified original circuit input and output timing constraints to the input and output ends of each sub-circuit according to the "basic logic gate delay model", and performs technology mapping on each sub-circuit under this constraint. Then, the mapped sub-circuit is recalculated and its timing constraints are updated according to the "lookup table delay model", and technology mapping is performed again after adjustment. The two steps of updating the sub-circuit timing constraints and re-technology mapping are repeated until the timing constraints on all sub-circuits converge numerically. The present application can obtain an FPGA circuit with more optimized timing performance.

According to one example of the present disclosure, a post-processing unit may be provided. The post-processing unit may be implemented in register transfer level (RTL) code and designed to interface with a neural processing unit (NPU) configured for object detection computations of a neural network model. The post-processing unit may include a processing unit configured to filter a plurality of bounding boxes transmitted from the NPU and output only those that satisfy a particular condition and one or more input registers configured to store data output from the processing unit.

The invention relates to a simulation method, device, system and equipment of a digital circuit and a medium. Comprising the steps that description information for the same digital circuit is obtained, and the description information comprises at least one of register transfer level description and gate level description; generating a primary circuit model based on the description information; the primary circuit model is converted into a middle layer circuit model connected with a preset basic logic unit, the basic logic unit is single-bit or multi-bit, each basic logic unit is provided with a corresponding model level attribute and a bit width attribute, and the model level attribute is a register transmission level or a gate level; and calling a simulation algorithm based on the intermediate layer circuit model to carry out circuit simulation to obtain a simulation result. By adopting the method, the simulation efficiency can be improved.

Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Methods and systems for simulating RTL models in combination with behavioral models involve generating an overall simulation model from a circuit design by a simulation tool of an EDA system. The overall simulation model includes respective behavioral simulation models of components of the circuit design. A register transfer level (RTL) simulation model of a particular component of the components of the circuit design is generated by an extractor tool of the EDA system. The respective behavioral simulation model of the particular component in the overall simulation model is replaced with the RTL simulation model, and a simulation that executes the overall simulation model and the RTL simulation model in place of the behavioral simulation model of the particular component is performed.

The present invention relates to a system and method for queuing in custom instruction extension of a hardened processor (203) such as a RISC-V processor implemented on a System-on-Chip (SoC) fabric; which enables high performance for said RISC-V processor (203) when interacting with any custom accelerator (205) via custom instruction extension (207) due to the reduced latency in waiting for a response from said custom accelerator (205). The system and method of the present invention also facilities clock domain crossing between the high frequency hardened processor (203) and the lower frequency custom accelerator (205), thus simplifying the design requirements for the custom accelerator (205) to close the timing gap. Besides that, the system and method of the present invention also supports blocking and non-blocking implementations of the queueing capability without needing for updates to the register transfer level (RTL) design.

A preferably computer-implemented method of prioritizing test cases, the method comprising: obtaining a test case coverage for each of a plurality of test cases for testing an integrated circuit, for example in a hardware description language, preferably on a register transfer level; the priority of each test case is determined based on the corresponding test case coverage rate, and the priorities indicate the execution sequence of the test cases.

According to one example of the present disclosure, a post-processing unit may be provided. The post-processing unit may be implemented in register transfer level (RTL) code and designed to interface with a neural processing unit (NPU) configured for object detection computations of a neural network model. The post-processing unit may include a processing unit configured to filter a plurality of bounding boxes transmitted from the NPU and output only those that satisfy a particular condition and one or more input registers configured to store data output from the processing unit.

The invention discloses a clock simulation method and device, equipment and a medium, relates to the technical field of integrated circuits, is applied to a prototype verification platform, and comprises the following steps: analyzing an original design file corresponding to a register transfer level circuit to obtain file topology information of an instantiated clock module; determining a to-be-adjusted clock module selected by the user side from the instantiated clock modules, and acquiring clock configuration information input by the user side, so as to generate a clock constraint file according to the clock configuration information; replacing a to-be-adjusted clock module in the original design file with a target clock module corresponding to the clock configuration information based on the file topology information to obtain an updated design file; and inputting the clock constraint file and the updated design file into a preset prototype development tool, and outputting a time sequence report after finishing time sequence analysis by utilizing the prototype development tool. Clock simulation under different scenes can be realized in an FPGA prototype verification platform, and the robustness of cross-clock domain transmission is verified.

A data storage device and a bridge device are provided. The data storage device includes a data storage medium, a processor including a plurality of processor cores, a plurality of application acceleration black box slots, a host interface to receive host commands from a remote application running on a remote host computer, the host commands including an image file, the image file including a register transfer level bitstream and a firmware driver image, and a configuration controller to download the register transfer level bitstream to the application acceleration black box slots and reconfigure the application acceleration black box slots, and load the firmware driver image to the processor cores of the processor. The processor cores run data acceleration processes of the remote application to access data stored in the data storage medium and process the data stored in the data storage medium using the register transfer level bitstream. The present invention can provide an efficient data processing solution while reducing the total cost of computing and storage infrastructure.

The application provides a code processing method and device of an integrated circuit, electronic equipment and a storage medium. The method comprises: obtaining source code, wherein the source code contains parameter information of a sub-module in the integrated circuit, and the source code is register transfer level code; constructing a structured packaging unit tree based on the source code; performing packaging processing on the structured packaging unit tree according to a high-level hardware description language to obtain a structured object; instantiating the structured object to obtain a hardware description language module; and in response to receiving a connection instruction, performing code generation based on the connection instruction and the hardware description language module to obtain connection code, wherein the connection instruction comprises a connection relationship between the sub-modules in the integrated circuit, the connection code indicates a signal transmission path between the sub-modules in the integrated circuit, and the connection code is hardware description language code. Through the application, the efficiency of connecting the signal transmission path between the modules in the integrated circuit design can be improved.

Embodiments of the present application disclose a reorganization method of a system on chip and a reorganization device of the system on chip. Embodiments of the present application determine a combination of intellectual property cores to be logically reorganized and a topological connection relationship of each functional module in the combination of the intellectual property cores based on a reorganization scheme of the system on chip, determine a reorganized register transfer level after logical reorganization based on the topological connection relationship and the reorganization scheme, and then perform logical verification on the register transfer level after the logical reorganization. In the embodiments of the present application, the reorganization scheme of the system on chip is used to modify the logical attribution of a specified functional module from a source intellectual property core in the combination of the intellectual property cores to a target intellectual property core, so that the embodiments of the present application can improve the performance of the system on chip through logical reorganization while guaranteeing the running stability of the system on chip after the logical reorganization through logical verification.

The present application relates to chip verification technical field, especially to a kind of front-end low-power verification environment generation method, electronic equipment and medium, method includes steps S1, the register transfer level code information A of chip is obtained n And unified power consumption format information B n ;Step S2, target configuration file is obtained;Step S3, the target configuration file is parsed, if C n It is set to first identification, then A1 n And B1 n Join target compilation file list, if C n It is set to second identification, then A2 n And B2 n Join target compilation file list;Step S4, at least one process angle corresponding standard cell library information file is screened from each standard cell library information file and joined target compilation file list;Step S5, based on the target compilation file list compiles and generates front-end low-power verification environment.The present application improves the generation efficiency and accuracy of front-end low-power verification environment.

The application discloses a simulation verification system and method supporting multiple verification scenes, and relates to the technical field of chip design verification.The system comprises: a unified verification environment, which is constructed based on the same verification methodology, is connected with design code through an interface, and provides test excitation; a mode configuration module, which is used for receiving user instructions, controls the simulation verification system to switch between register transfer level function simulation mode, zero-delay gate level simulation mode and gate level post-simulation mode with timing reverse markers, and realizes mode switching through predefined macro definition; an environment reuse module, which is used for reusing the verification environment and test cases in different simulation modes; and a result analysis and comparison module, which is used for collecting and comparing simulation results in different simulation modes.The application can integrate multiple simulation modes, realize seamless switching and high reuse of the verification environment, simultaneously consider simulation speed and timing accuracy, and significantly improve the verification efficiency and quality of complex chip design.

Various aspects of the present disclosed technology relate to techniques for test point insertion at register transfer level for a circuit design. A quick logic synthesis process is performed on an RTL circuit design to generate a gate-level netlist. Gate-level nodes in the gate-level netlist are back-annotated to corresponding locations in the RTL circuit design. Editable areas in the gate-level netlist are determined based on the back-annotation. A test point analysis process is performed on the gate-level netlist to determine gate-level locations for test point insertion in the editable areas. RTL locations for test point insertion in the RTL circuit design corresponding to the gate-level locations for test point insertion are determined based on the back-annotating result. Test points are inserted at the RTL locations for test point insertion to derive a modified RTL circuit design.

The application discloses a method and system for checking a timing path based on logical depth splitting, and the method comprises the following steps: acquiring a logical depth of a timing path; splitting the logical depth to obtain a buffer and inverter level and a register transfer level (RTL) level; and locating a timing problem source based on the logical depth, the buffer and inverter level and the RTL level. The timing path checking method and system provided by the application can locate the timing problem source accurately by splitting the logical depth into the buffer and inverter level and the RTL level, thereby improving timing convergence efficiency and reducing chip design complexity.

The embodiment of the invention discloses a verification method and device of a cache system, electronic equipment and a storage medium, relates to the technical field of chip verification, and aims to improve verification efficiency while ensuring verification accuracy of the cache system. The method comprises the steps that a cache verification model is constructed for a to-be-verified cache system, the cache verification model comprises a cache circuit model of the cache system and a universal verification assembly, and the cache circuit model is a register transfer level circuit model of the cache system; and running the cache verification model to enable the cache circuit model to interact with a transaction-level simulation model for simulating a memory system based on the universal verification component and a preset shared memory. The embodiment of the invention is used for verifying the chip cache system.