16 results about "Register-transfer level" patented technology

The embodiments described herein implement a protocol decoder tool designed by a hardware engineer in a hardware description language (HDL) in a simulator tool for testing and / or in a signal analysis system for decoding protocols in real-time. For example, a user (e.g., hardware engineer, hardware designer, protocol designer) may design a protocol using an HDL and design a protocol decoder tool for decoding the protocol in the HDL. Register transfer level (RTL) files with protocol decoder logic in the HDL may be converted from the HDL to a second language by a converter, compiled into a decoder module by a compiler, and executed in a signal analysis system as the protocol decoder tool. As such, errors in misinterpretation of protocol specifications may be reduced.

Embodiments of the present application disclose a reorganization method of a system on chip and a reorganization device of the system on chip. Embodiments of the present application determine a combination of intellectual property cores to be logically reorganized and a topological connection relationship of each functional module in the combination of the intellectual property cores based on a reorganization scheme of the system on chip, determine a reorganized register transfer level after logical reorganization based on the topological connection relationship and the reorganization scheme, and then perform logical verification on the register transfer level after the logical reorganization. In the embodiments of the present application, the reorganization scheme of the system on chip is used to modify the logical attribution of a specified functional module from a source intellectual property core in the combination of the intellectual property cores to a target intellectual property core, so that the embodiments of the present application can improve the performance of the system on chip through logical reorganization while guaranteeing the running stability of the system on chip after the logical reorganization through logical verification.

Disclosed subject matter relates to verification and debugging tool and method for providing sensitive regions around and in Register Transfer Level (RTL) code objects. The verification and debugging tool includes input interface configured to receive RTL code in Hardware Description Language (HDL). Further, verification and debugging tool includes RTL parser configured to parse RTL code, and generate abstract syntax tree representing syntactic structure of RTL code. Thereafter, verification and debugging tool includes graph converter configured to convert abstract syntax tree into RTL directed graph. Furthermore, verification and debugging tool includes visual display configured to display code blocks, each exhibiting sensitive regions. Finally, verification and debugging tool includes objects extractor configured to detect user actions related to sensitive regions. The sensitive regions are provided around and in each of RTL code objects to facilitate extraction and display of relevant information regarding dependencies and operations of RTL code upon user interactions.

The application provides a metastable state simulation method in pre-silicon simulation and electronic equipment, and relates to the chip design technical field. The method comprises the following steps: locating first-stage registers of each asynchronous flip-flop in a register transfer level code. The sampling exception probability value and the probability adjustment strategy of each first-stage register are configured, and a loop process is executed until the pre-silicon simulation is finished, so as to obtain a simulation result. The loop process comprises the following steps: in each clock cycle, it is judged whether the current input value of the first-stage register is same as the current output value; if yes, the current output value of the first-stage register is updated to the current input value; if not, it is randomly determined according to the sampling exception probability value whether the current sampling is normal updating or keeping the current output value, and the random result is recorded, and the sampling exception probability value is updated according to the random result and the probability adjustment strategy, and is used for next sampling. The technical scheme can improve the detection coverage and verification efficiency of the asynchronous path defects.

This invention belongs to the field of AI algorithm optimization technology for chip back-end component placement. It discloses a chip thermal placement method based on reinforcement learning. The method includes: obtaining the chip's register transfer level description file and electronic design automation tool output file; mapping the chip's three-dimensional thermal field onto a two-dimensional plane, pre-setting the chip's boundary conditions, initially analyzing the chip's temperature distribution and determining the rectangular shape of each macrocell and the heat source intensity function, further determining the chip's thermal field distribution and performing key optimizations using finite element analysis; modeling the chip placement process, processing the mask based on a policy network, obtaining macrocell placement actions, and determining the optimal thermal placement of the chip. This invention effectively ensures chip performance by simultaneously optimizing heat dissipation and line length, and avoids the local optima and non-convergence problems of traditional algorithms through reinforcement learning algorithms.

The application relates to the chip design technical field, in particular to a method for optimizing generation of a gate-level netlist. The method comprises the following steps: obtaining a standard cell library file and a user configuration file; obtaining preset performance parameter information of each standard cell of each standard cell type to be evaluated under each process angle to be evaluated according to the standard cell library file and the user configuration file; obtaining a comprehensive performance value of each standard cell under a process angle combination to be evaluated according to the preset performance parameter information and evaluation weights of the preset performance parameters; generating a standard cell disabling list according to the comprehensive performance value; converting the standard cell disabling list into a constraint script of a comprehensive tool, and loading the constraint script into a comprehensive environment as a hard constraint, so that the standard cells in the standard cell disabling list are avoided by the comprehensive tool in the process of mapping RTL (Register Transfer Level) code to the gate-level netlist. The application can solve the problems of low chip design efficiency and high cost.

This disclosure provides a method, apparatus, and computer device for generating register transfer level (RTL) codes. The method includes: parsing a target document according to a target document format to locate a register mapping table for one or more registers in the target document; traversing the contents of each cell in the register mapping table to parse out the names of one or more registers and one or more addresses associated with each register; for each register, searching at a specified location in the target document based on the register name to locate the register bit field description table corresponding to the register, obtaining the register bit field information by traversing the register bit field description table, and associating the bit field information with the register name; forming a register configuration dictionary based on the register name and the addresses and bit field information associated with each register name; and generating a register configuration file and the corresponding RTL code based on the register configuration dictionary.

The present application provides a system and method for predicting power consumption of an integrated circuit and a method for designing an integrated circuit. The system for predicting power consumption includes a simulator configured to generate vector data by verifying a functionality of a target circuit implemented with register transfer level (RTL) design data, and a power prediction circuit configured to predict power consumption by having the target circuit implemented with the RTL design data process a plurality of requests within a preset prediction time using the vector data as input vectors before the RTL design data is synthesized to a gate level.

The present disclosure provides a register transfer level encoding generation method, device and computer equipment. The method comprises: parsing a target document according to a target document format to locate a register mapping table of one or more registers in the target document; traversing the content in each unit in the register mapping table to parse to obtain the name of the one or more registers and one or more addresses respectively associated with each register; for each register, searching at a specified position of the target document based on the name of the register to locate a register bit field description table corresponding to the register, obtaining the bit field information of the register by traversing the register bit field description table, and associating the bit field information with the name of the register; forming a register configuration dictionary based on the name of the register and the addresses and bit field information respectively associated with the name of each register; and generating a register configuration file and a corresponding register transfer level encoding based on the register configuration dictionary.

Embodiments of the present application disclose a signal recovery method and system, electronic equipment and storage medium, and relate to the technical field of integrated circuit verification, which can improve verification efficiency. The method comprises: determining a plurality of scattered unit signals corresponding to a multi-bit-width signal in a netlist level based on a target signal list and a signal naming mapping table, the target signal list comprising a multi-bit-width signal to be processed, and the signal naming mapping table being used to record a mapping relationship between a hierarchical path from a register transfer level to the netlist level and a signal name; performing operation on a reset initial value of each bit-width signal at the register transfer level and a waveform initial value corresponding to the netlist level to generate a logic polarity correction sequence; and generating a debugging configuration file according to the logic polarity correction sequence, the debugging configuration file being used to instruct recovery of the plurality of scattered unit signals into the multi-bit-width signal consistent with the register transfer level logic. The present application is applicable to a scenario of netlist timing simulation debugging.

Embodiments of the present application provide a hardware design method and device. The method comprises: obtaining a design task and design specification; if the proportion of description information of graphical hardware with specific spatial or timing semantics in the design specification does not exceed a preset proportion threshold, determining that the design task is a text dominant task, and generating register transfer level code through a large language model according to the text dominant task and the corresponding design specification; otherwise, determining that the design task is a component dominant task, calling a tool through a large language model according to the component dominant task and the corresponding design specification; and generating register transfer level code according to the tool; the tool comprises a retrieval enhanced knowledge base, a rule type script and an electronic design automation simulation verification tool. The scheme of the present application improves the accuracy of hardware design.

Disclosed subject matter relates to verification and debugging tool and method for providing Register Transfer Level (RTL) code block storage and analysis. Verification and debugging tool includes input interface configured to receive RTL code in Hardware Description Language (HDL). Further, verification and debugging tool includes RTL parser configured to parse RTL code, and generate abstract syntax tree representing syntactic structure of RTL code. Thereafter, verification and debugging tool includes graph converter adapted to convert abstract syntax tree into RTL directed graph. Furthermore, verification and debugging tool includes memory configured to store node block structures. Each node block structure includes at least one of pointers to fan-in nodes, fanout nodes and one or more custom fields indicating behavior description of node. Finally, verification and debugging tool includes visual display configured to display RTL directed graph. Directional links indicate signal flow both upstream and downstream, enabling simultaneous visualization.

Disclosed subject matter relates to verification and debugging tool and method for providing spatial display of Register Transfer Level (RTL) code on a visual display. The verification and debugging tool includes an input interface configured to receive RTL code in a Hardware Description Language (HDL). Further, the verification and debugging tool includes an RTL parser configured to parse the RTL code, and generate an abstract syntax tree representing the syntactic structure of the RTL code. Thereafter, the verification and debugging tool includes a graph converter adapted to convert the abstract syntax tree into an RTL directed graph. Finally, the verification and debugging tool includes a visual display configured to display the RTL directed graph. The visual display simultaneously allows visualization of multiple code blocks and corresponding interconnections.

The application discloses a chip hardware code generation method based on large model code enhancement and self-reflection, designs a code enhancement method, re-describes open source code and generates register transfer level code, and verifies through an open source hardware compiler; error samples in the code generation process are collected and screened to construct an error correction dataset, which is used for enabling the model to learn strong self-reflection capability; through an iterative self-reflection process, including a closed-loop code generation-verification-correction process, the large language model continuously improves the generated code according to the feedback of the hardware compiler; a benchmark test set is created, benchmark testing is performed, and the self-reflection and improvement capability of the model register transfer level code is evaluated; the chip hardware code generation based on large model code enhancement and self-reflection is realized, and the quality and reliability of the generated code are improved.