70 results about "Register-transfer level" patented technology

The embodiment of the invention discloses a chip verification environment generation method and system, electronic equipment and a storage medium, relates to the technical field of integrated circuit verification, can adapt to verification environments with different configurations, and improves verification efficiency. The method comprises the following steps: constructing or calling a verification environment template; analyzing the initial configuration information and the routing topology information, and generating a target configuration file according to an interface protocol and an interconnection rule of a register transfer level and a model; the routing topology information indicates an interconnection link topology structure between the devices, and the target configuration file indicates a component type corresponding to each device required by simulation forming of each interconnection link and a matched verification component type; loading and instantiating the register transfer level component and the model component based on the verification environment template according to the component type; and according to the verification component type, interconnection is carried out between the register transfer level component and the model component through the verification component, and a chip executable verification environment is generated. The method and the device are suitable for a scene for constructing a chip verification environment.

The invention relates to the technical field of computers and provides a method for detecting a register transfer level code, electronic equipment and a medium. The method comprises the following steps: determining the code maturity of a first register transfer level code according to a code maturity index; determining a first chip development stage matched with the first register transfer level code based on the code maturity corresponding to each of the plurality of chip development stages; when the first chip development stage is an acceptance stage, carrying out the quality detection of the front-end design process through the comprehensive verification tool according to the quality detection item of the comprehensive verification tool; and when the first chip development stage is not the acceptance stage, configuring the comprehensive verification tool according to configuration environment input to obtain a configured comprehensive verification tool, and then performing quality detection of the front-end design process according to the quality detection items included in the rapid quality detection item set through the configured comprehensive verification tool. In this way, correctness is ensured, and iteration efficiency is improved.

The invention provides a code processing method and device of an integrated circuit, electronic equipment and a storage medium. The method comprises the steps that a source code is obtained, the source code comprises parameter information of a sub-module in the integrated circuit, and the source code is a register transfer level code; constructing a structured encapsulation unit tree based on the source code; packaging the structured packaging unit tree according to a high-level hardware description language to obtain a structured object; instantiating the structured object to obtain a hardware description language module; and in response to the received connection instruction, code generation is performed based on the connection instruction and the hardware description language module to obtain a connection code, the connection instruction comprises a connection relationship between the sub-modules in the integrated circuit, the connection code indicates a signal transmission path between the sub-modules in the integrated circuit, and the connection code is a hardware description language code. According to the invention, the connection efficiency of signal transmission paths between modules in an integrated circuit design can be improved.

The invention discloses a method and a system for checking a time sequence path based on logic depth splitting. The method comprises the following steps: acquiring the logic depth of the time sequence path; splitting the logic depth to obtain a buffer and inverter level and a register transfer level (RTL) level; based on the logic depth, a buffer and inverter level, and a register transfer level (RTL) level, a timing problem source is located. According to the time sequence path inspection method and system provided by the invention, the logic depth is divided into the buffer and inverter level and the RTL level, and the source of the time sequence problem is accurately positioned, so that the time sequence convergence efficiency is improved, and the chip design complexity is reduced.

The invention provides a low-power-consumption simulation method and device, equipment, a storage medium and a program product, and relates to the technical field of integrated circuits. The method comprises the following steps: determining an initial comprehensive model of a register transfer level corresponding to a to-be-simulated chip; based on the initial comprehensive model, determining a target comprehensive model corresponding to the to-be-simulated chip; according to the initial gate-level netlist corresponding to the to-be-simulated chip, generating a target gate-level netlist corresponding to a power supply loop in low-power-consumption simulation; and based on a preset hardware simulation accelerator, performing low-power-consumption simulation including a power supply loop on the target synthesizable model and the target gate-level netlist. According to the method, the low-power-consumption simulation convergence time is greatly shortened, and the simulation efficiency is improved.

The embodiments described herein implement a protocol decoder tool designed by a hardware engineer in a hardware description language (HDL) in a simulator tool for testing and / or in a signal analysis system for decoding protocols in real-time. For example, a user (e.g., hardware engineer, hardware designer, protocol designer) may design a protocol using an HDL and design a protocol decoder tool for decoding the protocol in the HDL. Register transfer level (RTL) files with protocol decoder logic in the HDL may be converted from the HDL to a second language by a converter, compiled into a decoder module by a compiler, and executed in a signal analysis system as the protocol decoder tool. As such, errors in misinterpretation of protocol specifications may be reduced.

The invention relates to the technical field of integrated circuits and provides a chip verification method, computer equipment, a medium and a chip verification platform. The method comprises the following steps: based on test content of a first test point, selecting a necessary subsystem module associated with the first test point in a plurality of subsystem modules which are designed by a first chip and are integrated on a system top layer; identifying other subsystem modules except the necessary subsystem module associated with the first test point in the plurality of subsystem modules as unnecessary subsystem modules associated with the first test point; performing register transfer level compilation and emulation verification of test content for a first test point, including instantiating a chip top layer control module integrated on a chip top layer of a first chip design, instantiating a necessary subsystem module associated with the first test point, and performing a first test point design; and performing virtual module replacement operation on the unnecessary subsystem module associated with the first test point. In this way, compiling and simulation time is shortened, and verification efficiency is improved.

The present application relates to the technical field of field programmable gate array circuits, and discloses a method and system for optimizing FPGA technology mapping. The method first divides the input register transfer level circuit into several sub-circuits, and then transmits the user-specified original circuit input and output timing constraints to the input and output ends of each sub-circuit according to the "basic logic gate delay model", and performs technology mapping on each sub-circuit under this constraint. Then, the mapped sub-circuit is recalculated and its timing constraints are updated according to the "lookup table delay model", and technology mapping is performed again after adjustment. The two steps of updating the sub-circuit timing constraints and re-technology mapping are repeated until the timing constraints on all sub-circuits converge numerically. The present application can obtain an FPGA circuit with more optimized timing performance.

According to one example of the present disclosure, a post-processing unit may be provided. The post-processing unit may be implemented in register transfer level (RTL) code and designed to interface with a neural processing unit (NPU) configured for object detection computations of a neural network model. The post-processing unit may include a processing unit configured to filter a plurality of bounding boxes transmitted from the NPU and output only those that satisfy a particular condition and one or more input registers configured to store data output from the processing unit.

The invention relates to a simulation method, device, system and equipment of a digital circuit and a medium. Comprising the steps that description information for the same digital circuit is obtained, and the description information comprises at least one of register transfer level description and gate level description; generating a primary circuit model based on the description information; the primary circuit model is converted into a middle layer circuit model connected with a preset basic logic unit, the basic logic unit is single-bit or multi-bit, each basic logic unit is provided with a corresponding model level attribute and a bit width attribute, and the model level attribute is a register transmission level or a gate level; and calling a simulation algorithm based on the intermediate layer circuit model to carry out circuit simulation to obtain a simulation result. By adopting the method, the simulation efficiency can be improved.

Methods and systems for simulating RTL models in combination with behavioral models involve generating an overall simulation model from a circuit design by a simulation tool of an EDA system. The overall simulation model includes respective behavioral simulation models of components of the circuit design. A register transfer level (RTL) simulation model of a particular component of the components of the circuit design is generated by an extractor tool of the EDA system. The respective behavioral simulation model of the particular component in the overall simulation model is replaced with the RTL simulation model, and a simulation that executes the overall simulation model and the RTL simulation model in place of the behavioral simulation model of the particular component is performed.

A preferably computer-implemented method of prioritizing test cases, the method comprising: obtaining a test case coverage for each of a plurality of test cases for testing an integrated circuit, for example in a hardware description language, preferably on a register transfer level; the priority of each test case is determined based on the corresponding test case coverage rate, and the priorities indicate the execution sequence of the test cases.

According to one example of the present disclosure, a post-processing unit may be provided. The post-processing unit may be implemented in register transfer level (RTL) code and designed to interface with a neural processing unit (NPU) configured for object detection computations of a neural network model. The post-processing unit may include a processing unit configured to filter a plurality of bounding boxes transmitted from the NPU and output only those that satisfy a particular condition and one or more input registers configured to store data output from the processing unit.

A data storage device and a bridge device are provided. The data storage device includes a data storage medium, a processor including a plurality of processor cores, a plurality of application acceleration black box slots, a host interface to receive host commands from a remote application running on a remote host computer, the host commands including an image file, the image file including a register transfer level bitstream and a firmware driver image, and a configuration controller to download the register transfer level bitstream to the application acceleration black box slots and reconfigure the application acceleration black box slots, and load the firmware driver image to the processor cores of the processor. The processor cores run data acceleration processes of the remote application to access data stored in the data storage medium and process the data stored in the data storage medium using the register transfer level bitstream. The present invention can provide an efficient data processing solution while reducing the total cost of computing and storage infrastructure.

The application provides a code processing method and device of an integrated circuit, electronic equipment and a storage medium. The method comprises: obtaining source code, wherein the source code contains parameter information of a sub-module in the integrated circuit, and the source code is register transfer level code; constructing a structured packaging unit tree based on the source code; performing packaging processing on the structured packaging unit tree according to a high-level hardware description language to obtain a structured object; instantiating the structured object to obtain a hardware description language module; and in response to receiving a connection instruction, performing code generation based on the connection instruction and the hardware description language module to obtain connection code, wherein the connection instruction comprises a connection relationship between the sub-modules in the integrated circuit, the connection code indicates a signal transmission path between the sub-modules in the integrated circuit, and the connection code is hardware description language code. Through the application, the efficiency of connecting the signal transmission path between the modules in the integrated circuit design can be improved.

Embodiments of the present application disclose a reorganization method of a system on chip and a reorganization device of the system on chip. Embodiments of the present application determine a combination of intellectual property cores to be logically reorganized and a topological connection relationship of each functional module in the combination of the intellectual property cores based on a reorganization scheme of the system on chip, determine a reorganized register transfer level after logical reorganization based on the topological connection relationship and the reorganization scheme, and then perform logical verification on the register transfer level after the logical reorganization. In the embodiments of the present application, the reorganization scheme of the system on chip is used to modify the logical attribution of a specified functional module from a source intellectual property core in the combination of the intellectual property cores to a target intellectual property core, so that the embodiments of the present application can improve the performance of the system on chip through logical reorganization while guaranteeing the running stability of the system on chip after the logical reorganization through logical verification.

The present application relates to chip verification technical field, especially to a kind of front-end low-power verification environment generation method, electronic equipment and medium, method includes steps S1, the register transfer level code information A of chip is obtained n And unified power consumption format information B n ;Step S2, target configuration file is obtained;Step S3, the target configuration file is parsed, if C n It is set to first identification, then A1 n And B1 n Join target compilation file list, if C n It is set to second identification, then A2 n And B2 n Join target compilation file list;Step S4, at least one process angle corresponding standard cell library information file is screened from each standard cell library information file and joined target compilation file list;Step S5, based on the target compilation file list compiles and generates front-end low-power verification environment.The present application improves the generation efficiency and accuracy of front-end low-power verification environment.

The application discloses a simulation verification system and method supporting multiple verification scenes, and relates to the technical field of chip design verification.The system comprises: a unified verification environment, which is constructed based on the same verification methodology, is connected with design code through an interface, and provides test excitation; a mode configuration module, which is used for receiving user instructions, controls the simulation verification system to switch between register transfer level function simulation mode, zero-delay gate level simulation mode and gate level post-simulation mode with timing reverse markers, and realizes mode switching through predefined macro definition; an environment reuse module, which is used for reusing the verification environment and test cases in different simulation modes; and a result analysis and comparison module, which is used for collecting and comparing simulation results in different simulation modes.The application can integrate multiple simulation modes, realize seamless switching and high reuse of the verification environment, simultaneously consider simulation speed and timing accuracy, and significantly improve the verification efficiency and quality of complex chip design.

Various aspects of the present disclosed technology relate to techniques for test point insertion at register transfer level for a circuit design. A quick logic synthesis process is performed on an RTL circuit design to generate a gate-level netlist. Gate-level nodes in the gate-level netlist are back-annotated to corresponding locations in the RTL circuit design. Editable areas in the gate-level netlist are determined based on the back-annotation. A test point analysis process is performed on the gate-level netlist to determine gate-level locations for test point insertion in the editable areas. RTL locations for test point insertion in the RTL circuit design corresponding to the gate-level locations for test point insertion are determined based on the back-annotating result. Test points are inserted at the RTL locations for test point insertion to derive a modified RTL circuit design.

The application discloses a method and system for checking a timing path based on logical depth splitting, and the method comprises the following steps: acquiring a logical depth of a timing path; splitting the logical depth to obtain a buffer and inverter level and a register transfer level (RTL) level; and locating a timing problem source based on the logical depth, the buffer and inverter level and the RTL level. The timing path checking method and system provided by the application can locate the timing problem source accurately by splitting the logical depth into the buffer and inverter level and the RTL level, thereby improving timing convergence efficiency and reducing chip design complexity.

The embodiment of the invention discloses a verification method and device of a cache system, electronic equipment and a storage medium, relates to the technical field of chip verification, and aims to improve verification efficiency while ensuring verification accuracy of the cache system. The method comprises the steps that a cache verification model is constructed for a to-be-verified cache system, the cache verification model comprises a cache circuit model of the cache system and a universal verification assembly, and the cache circuit model is a register transfer level circuit model of the cache system; and running the cache verification model to enable the cache circuit model to interact with a transaction-level simulation model for simulating a memory system based on the universal verification component and a preset shared memory. The embodiment of the invention is used for verifying the chip cache system.

The invention provides a field programmable memory array, a writing method and a reading method. The field programmable memory array comprises a single readable and writable memory array, an addressing circuit and an access circuit. The readable and writable memory array includes m memory cells in 2i rows and 2j columns to perform a digital circuit function, and has a plurality of digital inputs and a plurality of digital outputs. The addressing circuit is configured to receive an n-bit input vector and is coupled between the readable and writable memory array and the access circuit. The n-bit input vectors are selected from a register conversion layer logic table, and the logic table comprises a plurality of n-bit input vectors and a plurality of m-bit output vectors. The FPMA utilizes the character line / bit line multiplexer characteristics of the memory array to realize the operation of a plurality of binary inputs and any number of binary outputs. The FPMA has the advantages that the connection complexity is reduced, the number of repeated flip-flops is reduced, and the grain area in an integrated circuit chip is saved.

The invention specifically discloses an AES encrypted circuit-oriented anti-radiation soft error analysis method based on CVPI, and relates to the technical field of integrated circuit reliability testing. The method comprises the following steps: S1, inputting single-particle soft error simulation parameters; s2, synthesizing a register transfer level RTL code of the AES encryption circuit into a netlist; s3, the RTL and the gate-level netlist of the AES encrypted circuit are analyzed, and RTL instance representation information and netlist unit information are extracted; s4, constructing a single-particle soft error database; s5, based on the upset section model and Poisson distribution time modeling, generating a single-particle soft error injection list; s6, performing batch single-particle soft error injection on the AES encrypted circuit based on the user-defined CVPI interface; and S7, generating an AES encrypted circuit single-particle soft error analysis report. According to the method, the precision and efficiency of anti-radiation soft error analysis of the AES encryption circuit are improved, and support is provided for design of a high-reliability encryption chip.

According to one example of the present disclosure, a post-processing unit may be provided. The post-processing unit may be implemented in register transfer level (RTL) code and designed to interface with a neural processing unit (NPU) configured for object detection computations of a neural network model. The post-processing unit may include a processing unit configured to filter a plurality of bounding boxes transmitted from the NPU and output only those that satisfy a particular condition and one or more input registers configured to store data output from the processing unit.

Various embodiments of the present disclosure provide a multi-layered framework for security of integrated circuits. In one example, an embodiment provides for removing one or more routing tables in a Register Transfer Level (RTL) source code that models a design for an SoC via a hardware description language, comprising replacing the one or more routing tables in the RTL source code with respective programmable memory, transforming a state space of one or more embedded state machines in the RTL source code, transforming one or more portions of combinational logic in the RTL source code, and / or removing one or more portions of security-critical logic in the RTL source code, comprising replacing the one or more portions of security-critical logic in the RTL source code with respective lookup tables.

The invention discloses an RISC-V processor verification method and system and a storage medium. The method comprises the following steps: monitoring version change of a register transfer level hardware circuit code of the RISC-V processor to establish a change influence domain; and constructing an inter-module relationship graph according to the change influence domain, and positioning a verification scene based on the inter-module relationship graph. And generating a test case in the verification scene, and performing RISC-V processor verification according to the test case. The modification points in iterative development are determined based on the version evolution trajectory, and the change influence domain is established according to the modification points, so that a basis is provided for limiting a verification scene; and a clear boundary is provided for the generation of the test case through the establishment of the verification scene, so that the problem of fuzzy verification range in the development iteration of the processor is effectively solved, the consumption of test resources is greatly reduced, the full-chip simulation is avoided, the feedback period is shortened, the verification efficiency is improved, and a reliable guarantee is provided for the rapid iterative optimization of the processor.

A power consumption analysis method and device for the design of an integrated circuit chip, a power integrity design method of the integrated circuit chip, an electronic device, and a storage medium. The power consumption analysis method comprises: performing a mapping operation on a register transfer level simulation waveform file of the integrated circuit chip to obtain a gate level netlist waveform file corresponding to the register transfer level simulation waveform file; performing a power consumption analysis operation on the integrated circuit chip according to the gate level netlist waveform file to obtain a power consumption waveform file of the integrated circuit chip; and obtaining a current characteristic file representing a current characteristic of the integrated circuit chip according to the power consumption waveform file of the integrated circuit chip. The power consumption analysis method can obtain the power consumption and the current characteristic of the integrated circuit chip at an early stage of the design process of the integrated circuit chip, which helps to reduce the power consumption of the integrated circuit chip at an early stage, solve the voltage drop problem of the integrated circuit chip, optimize chip design, and reduce design cost.

Disclosed subject matter relates to verification and debugging tool and method for providing sensitive regions around and in Register Transfer Level (RTL) code objects. The verification and debugging tool includes input interface configured to receive RTL code in Hardware Description Language (HDL). Further, verification and debugging tool includes RTL parser configured to parse RTL code, and generate abstract syntax tree representing syntactic structure of RTL code. Thereafter, verification and debugging tool includes graph converter configured to convert abstract syntax tree into RTL directed graph. Furthermore, verification and debugging tool includes visual display configured to display code blocks, each exhibiting sensitive regions. Finally, verification and debugging tool includes objects extractor configured to detect user actions related to sensitive regions. The sensitive regions are provided around and in each of RTL code objects to facilitate extraction and display of relevant information regarding dependencies and operations of RTL code upon user interactions.

The application provides a metastable state simulation method in pre-silicon simulation and electronic equipment, and relates to the chip design technical field. The method comprises the following steps: locating first-stage registers of each asynchronous flip-flop in a register transfer level code. The sampling exception probability value and the probability adjustment strategy of each first-stage register are configured, and a loop process is executed until the pre-silicon simulation is finished, so as to obtain a simulation result. The loop process comprises the following steps: in each clock cycle, it is judged whether the current input value of the first-stage register is same as the current output value; if yes, the current output value of the first-stage register is updated to the current input value; if not, it is randomly determined according to the sampling exception probability value whether the current sampling is normal updating or keeping the current output value, and the random result is recorded, and the sampling exception probability value is updated according to the random result and the probability adjustment strategy, and is used for next sampling. The technical scheme can improve the detection coverage and verification efficiency of the asynchronous path defects.

This invention belongs to the field of AI algorithm optimization technology for chip back-end component placement. It discloses a chip thermal placement method based on reinforcement learning. The method includes: obtaining the chip's register transfer level description file and electronic design automation tool output file; mapping the chip's three-dimensional thermal field onto a two-dimensional plane, pre-setting the chip's boundary conditions, initially analyzing the chip's temperature distribution and determining the rectangular shape of each macrocell and the heat source intensity function, further determining the chip's thermal field distribution and performing key optimizations using finite element analysis; modeling the chip placement process, processing the mask based on a policy network, obtaining macrocell placement actions, and determining the optimal thermal placement of the chip. This invention effectively ensures chip performance by simultaneously optimizing heat dissipation and line length, and avoids the local optima and non-convergence problems of traditional algorithms through reinforcement learning algorithms.