38 results about "Register-transfer level" patented technology

The invention provides a code processing method and device of an integrated circuit, electronic equipment and a storage medium. The method comprises the steps that a source code is obtained, the source code comprises parameter information of a sub-module in the integrated circuit, and the source code is a register transfer level code; constructing a structured encapsulation unit tree based on the source code; packaging the structured packaging unit tree according to a high-level hardware description language to obtain a structured object; instantiating the structured object to obtain a hardware description language module; and in response to the received connection instruction, code generation is performed based on the connection instruction and the hardware description language module to obtain a connection code, the connection instruction comprises a connection relationship between the sub-modules in the integrated circuit, the connection code indicates a signal transmission path between the sub-modules in the integrated circuit, and the connection code is a hardware description language code. According to the invention, the connection efficiency of signal transmission paths between modules in an integrated circuit design can be improved.

The embodiments described herein implement a protocol decoder tool designed by a hardware engineer in a hardware description language (HDL) in a simulator tool for testing and / or in a signal analysis system for decoding protocols in real-time. For example, a user (e.g., hardware engineer, hardware designer, protocol designer) may design a protocol using an HDL and design a protocol decoder tool for decoding the protocol in the HDL. Register transfer level (RTL) files with protocol decoder logic in the HDL may be converted from the HDL to a second language by a converter, compiled into a decoder module by a compiler, and executed in a signal analysis system as the protocol decoder tool. As such, errors in misinterpretation of protocol specifications may be reduced.

The invention relates to the technical field of integrated circuits and provides a chip verification method, computer equipment, a medium and a chip verification platform. The method comprises the following steps: based on test content of a first test point, selecting a necessary subsystem module associated with the first test point in a plurality of subsystem modules which are designed by a first chip and are integrated on a system top layer; identifying other subsystem modules except the necessary subsystem module associated with the first test point in the plurality of subsystem modules as unnecessary subsystem modules associated with the first test point; performing register transfer level compilation and emulation verification of test content for a first test point, including instantiating a chip top layer control module integrated on a chip top layer of a first chip design, instantiating a necessary subsystem module associated with the first test point, and performing a first test point design; and performing virtual module replacement operation on the unnecessary subsystem module associated with the first test point. In this way, compiling and simulation time is shortened, and verification efficiency is improved.

A preferably computer-implemented method of prioritizing test cases, the method comprising: obtaining a test case coverage for each of a plurality of test cases for testing an integrated circuit, for example in a hardware description language, preferably on a register transfer level; the priority of each test case is determined based on the corresponding test case coverage rate, and the priorities indicate the execution sequence of the test cases.

The application provides a code processing method and device of an integrated circuit, electronic equipment and a storage medium. The method comprises: obtaining source code, wherein the source code contains parameter information of a sub-module in the integrated circuit, and the source code is register transfer level code; constructing a structured packaging unit tree based on the source code; performing packaging processing on the structured packaging unit tree according to a high-level hardware description language to obtain a structured object; instantiating the structured object to obtain a hardware description language module; and in response to receiving a connection instruction, performing code generation based on the connection instruction and the hardware description language module to obtain connection code, wherein the connection instruction comprises a connection relationship between the sub-modules in the integrated circuit, the connection code indicates a signal transmission path between the sub-modules in the integrated circuit, and the connection code is hardware description language code. Through the application, the efficiency of connecting the signal transmission path between the modules in the integrated circuit design can be improved.

Embodiments of the present application disclose a reorganization method of a system on chip and a reorganization device of the system on chip. Embodiments of the present application determine a combination of intellectual property cores to be logically reorganized and a topological connection relationship of each functional module in the combination of the intellectual property cores based on a reorganization scheme of the system on chip, determine a reorganized register transfer level after logical reorganization based on the topological connection relationship and the reorganization scheme, and then perform logical verification on the register transfer level after the logical reorganization. In the embodiments of the present application, the reorganization scheme of the system on chip is used to modify the logical attribution of a specified functional module from a source intellectual property core in the combination of the intellectual property cores to a target intellectual property core, so that the embodiments of the present application can improve the performance of the system on chip through logical reorganization while guaranteeing the running stability of the system on chip after the logical reorganization through logical verification.

The application discloses a simulation verification system and method supporting multiple verification scenes, and relates to the technical field of chip design verification.The system comprises: a unified verification environment, which is constructed based on the same verification methodology, is connected with design code through an interface, and provides test excitation; a mode configuration module, which is used for receiving user instructions, controls the simulation verification system to switch between register transfer level function simulation mode, zero-delay gate level simulation mode and gate level post-simulation mode with timing reverse markers, and realizes mode switching through predefined macro definition; an environment reuse module, which is used for reusing the verification environment and test cases in different simulation modes; and a result analysis and comparison module, which is used for collecting and comparing simulation results in different simulation modes.The application can integrate multiple simulation modes, realize seamless switching and high reuse of the verification environment, simultaneously consider simulation speed and timing accuracy, and significantly improve the verification efficiency and quality of complex chip design.

Various aspects of the present disclosed technology relate to techniques for test point insertion at register transfer level for a circuit design. A quick logic synthesis process is performed on an RTL circuit design to generate a gate-level netlist. Gate-level nodes in the gate-level netlist are back-annotated to corresponding locations in the RTL circuit design. Editable areas in the gate-level netlist are determined based on the back-annotation. A test point analysis process is performed on the gate-level netlist to determine gate-level locations for test point insertion in the editable areas. RTL locations for test point insertion in the RTL circuit design corresponding to the gate-level locations for test point insertion are determined based on the back-annotating result. Test points are inserted at the RTL locations for test point insertion to derive a modified RTL circuit design.

The embodiment of the invention discloses a verification method and device of a cache system, electronic equipment and a storage medium, relates to the technical field of chip verification, and aims to improve verification efficiency while ensuring verification accuracy of the cache system. The method comprises the steps that a cache verification model is constructed for a to-be-verified cache system, the cache verification model comprises a cache circuit model of the cache system and a universal verification assembly, and the cache circuit model is a register transfer level circuit model of the cache system; and running the cache verification model to enable the cache circuit model to interact with a transaction-level simulation model for simulating a memory system based on the universal verification component and a preset shared memory. The embodiment of the invention is used for verifying the chip cache system.

The invention provides a field programmable memory array, a writing method and a reading method. The field programmable memory array comprises a single readable and writable memory array, an addressing circuit and an access circuit. The readable and writable memory array includes m memory cells in 2i rows and 2j columns to perform a digital circuit function, and has a plurality of digital inputs and a plurality of digital outputs. The addressing circuit is configured to receive an n-bit input vector and is coupled between the readable and writable memory array and the access circuit. The n-bit input vectors are selected from a register conversion layer logic table, and the logic table comprises a plurality of n-bit input vectors and a plurality of m-bit output vectors. The FPMA utilizes the character line / bit line multiplexer characteristics of the memory array to realize the operation of a plurality of binary inputs and any number of binary outputs. The FPMA has the advantages that the connection complexity is reduced, the number of repeated flip-flops is reduced, and the grain area in an integrated circuit chip is saved.

The invention specifically discloses an AES encrypted circuit-oriented anti-radiation soft error analysis method based on CVPI, and relates to the technical field of integrated circuit reliability testing. The method comprises the following steps: S1, inputting single-particle soft error simulation parameters; s2, synthesizing a register transfer level RTL code of the AES encryption circuit into a netlist; s3, the RTL and the gate-level netlist of the AES encrypted circuit are analyzed, and RTL instance representation information and netlist unit information are extracted; s4, constructing a single-particle soft error database; s5, based on the upset section model and Poisson distribution time modeling, generating a single-particle soft error injection list; s6, performing batch single-particle soft error injection on the AES encrypted circuit based on the user-defined CVPI interface; and S7, generating an AES encrypted circuit single-particle soft error analysis report. According to the method, the precision and efficiency of anti-radiation soft error analysis of the AES encryption circuit are improved, and support is provided for design of a high-reliability encryption chip.

According to one example of the present disclosure, a post-processing unit may be provided. The post-processing unit may be implemented in register transfer level (RTL) code and designed to interface with a neural processing unit (NPU) configured for object detection computations of a neural network model. The post-processing unit may include a processing unit configured to filter a plurality of bounding boxes transmitted from the NPU and output only those that satisfy a particular condition and one or more input registers configured to store data output from the processing unit.

Various embodiments of the present disclosure provide a multi-layered framework for security of integrated circuits. In one example, an embodiment provides for removing one or more routing tables in a Register Transfer Level (RTL) source code that models a design for an SoC via a hardware description language, comprising replacing the one or more routing tables in the RTL source code with respective programmable memory, transforming a state space of one or more embedded state machines in the RTL source code, transforming one or more portions of combinational logic in the RTL source code, and / or removing one or more portions of security-critical logic in the RTL source code, comprising replacing the one or more portions of security-critical logic in the RTL source code with respective lookup tables.

The invention discloses an RISC-V processor verification method and system and a storage medium. The method comprises the following steps: monitoring version change of a register transfer level hardware circuit code of the RISC-V processor to establish a change influence domain; and constructing an inter-module relationship graph according to the change influence domain, and positioning a verification scene based on the inter-module relationship graph. And generating a test case in the verification scene, and performing RISC-V processor verification according to the test case. The modification points in iterative development are determined based on the version evolution trajectory, and the change influence domain is established according to the modification points, so that a basis is provided for limiting a verification scene; and a clear boundary is provided for the generation of the test case through the establishment of the verification scene, so that the problem of fuzzy verification range in the development iteration of the processor is effectively solved, the consumption of test resources is greatly reduced, the full-chip simulation is avoided, the feedback period is shortened, the verification efficiency is improved, and a reliable guarantee is provided for the rapid iterative optimization of the processor.

Disclosed subject matter relates to verification and debugging tool and method for providing sensitive regions around and in Register Transfer Level (RTL) code objects. The verification and debugging tool includes input interface configured to receive RTL code in Hardware Description Language (HDL). Further, verification and debugging tool includes RTL parser configured to parse RTL code, and generate abstract syntax tree representing syntactic structure of RTL code. Thereafter, verification and debugging tool includes graph converter configured to convert abstract syntax tree into RTL directed graph. Furthermore, verification and debugging tool includes visual display configured to display code blocks, each exhibiting sensitive regions. Finally, verification and debugging tool includes objects extractor configured to detect user actions related to sensitive regions. The sensitive regions are provided around and in each of RTL code objects to facilitate extraction and display of relevant information regarding dependencies and operations of RTL code upon user interactions.

The application provides a metastable state simulation method in pre-silicon simulation and electronic equipment, and relates to the chip design technical field. The method comprises the following steps: locating first-stage registers of each asynchronous flip-flop in a register transfer level code. The sampling exception probability value and the probability adjustment strategy of each first-stage register are configured, and a loop process is executed until the pre-silicon simulation is finished, so as to obtain a simulation result. The loop process comprises the following steps: in each clock cycle, it is judged whether the current input value of the first-stage register is same as the current output value; if yes, the current output value of the first-stage register is updated to the current input value; if not, it is randomly determined according to the sampling exception probability value whether the current sampling is normal updating or keeping the current output value, and the random result is recorded, and the sampling exception probability value is updated according to the random result and the probability adjustment strategy, and is used for next sampling. The technical scheme can improve the detection coverage and verification efficiency of the asynchronous path defects.

This invention belongs to the field of AI algorithm optimization technology for chip back-end component placement. It discloses a chip thermal placement method based on reinforcement learning. The method includes: obtaining the chip's register transfer level description file and electronic design automation tool output file; mapping the chip's three-dimensional thermal field onto a two-dimensional plane, pre-setting the chip's boundary conditions, initially analyzing the chip's temperature distribution and determining the rectangular shape of each macrocell and the heat source intensity function, further determining the chip's thermal field distribution and performing key optimizations using finite element analysis; modeling the chip placement process, processing the mask based on a policy network, obtaining macrocell placement actions, and determining the optimal thermal placement of the chip. This invention effectively ensures chip performance by simultaneously optimizing heat dissipation and line length, and avoids the local optima and non-convergence problems of traditional algorithms through reinforcement learning algorithms.

The application relates to the chip design technical field, in particular to a method for optimizing generation of a gate-level netlist. The method comprises the following steps: obtaining a standard cell library file and a user configuration file; obtaining preset performance parameter information of each standard cell of each standard cell type to be evaluated under each process angle to be evaluated according to the standard cell library file and the user configuration file; obtaining a comprehensive performance value of each standard cell under a process angle combination to be evaluated according to the preset performance parameter information and evaluation weights of the preset performance parameters; generating a standard cell disabling list according to the comprehensive performance value; converting the standard cell disabling list into a constraint script of a comprehensive tool, and loading the constraint script into a comprehensive environment as a hard constraint, so that the standard cells in the standard cell disabling list are avoided by the comprehensive tool in the process of mapping RTL (Register Transfer Level) code to the gate-level netlist. The application can solve the problems of low chip design efficiency and high cost.

This disclosure provides a method, apparatus, and computer device for generating register transfer level (RTL) codes. The method includes: parsing a target document according to a target document format to locate a register mapping table for one or more registers in the target document; traversing the contents of each cell in the register mapping table to parse out the names of one or more registers and one or more addresses associated with each register; for each register, searching at a specified location in the target document based on the register name to locate the register bit field description table corresponding to the register, obtaining the register bit field information by traversing the register bit field description table, and associating the bit field information with the register name; forming a register configuration dictionary based on the register name and the addresses and bit field information associated with each register name; and generating a register configuration file and the corresponding RTL code based on the register configuration dictionary.

The present application provides a system and method for predicting power consumption of an integrated circuit and a method for designing an integrated circuit. The system for predicting power consumption includes a simulator configured to generate vector data by verifying a functionality of a target circuit implemented with register transfer level (RTL) design data, and a power prediction circuit configured to predict power consumption by having the target circuit implemented with the RTL design data process a plurality of requests within a preset prediction time using the vector data as input vectors before the RTL design data is synthesized to a gate level.

The invention discloses a solver scheduling method and a form verification method. The solver scheduling method comprises the steps that register transfer level description of a hardware circuit is input into a form verification application containing task modules corresponding to different verification scenes, and an SMT file corresponding to each verification scene is generated; combining each SMT file with the hardware description associated with the corresponding verification scene, and extracting grammar-level features and hardware domain features to form a comprehensive feature vector; storing the comprehensive feature vector and a historical solution time label corresponding to the verification scene as training data; performing training and parameter tuning on the plurality of candidate models based on a preset number of training data, and selecting an optimal prediction model suitable for different verification scenes and solver configurations; and acquiring a comprehensive feature vector of a to-be-verified hardware circuit, and inputting the comprehensive feature vector into the optimal prediction model to predict the solving duration so as to select a proper SMT solver. According to the method, the solving duration can be accurately predicted, and a proper solver can be selected.

The invention discloses a bidirectional data synthesis method based on register transfer level codes, and the method comprises the steps: collecting a register transfer level RTL code data set in a real world, analyzing a signal in each piece of RTL data, decomposing each verification specification in the RTL data into a plurality of natural language properties, inputting each natural language property and the corresponding RTL code into a large language model to generate an assertion SVA corresponding to the natural language property; the method comprises the steps that two-way screening is used for strengthening the nature of a natural language and semantic consistency between the SVA, two translations from the SVA to the natural language and then to the SVA are executed, for the translated two-way language, based on formalized equivalence check, the logic equivalence of the two translated SVA is verified, non-equivalent data are filtered out, and a natural language and SVA pair with corresponding RTL codes is generated. According to the method, a large number of high-quality SVA data sets conforming to real world distribution are obtained, and semantic consistency between natural language properties and SVA in the data sets is improved.

The invention relates to the technical field of integrated circuit hardware security, in particular to an interpretable hardware Trojan horse detection method based on an attention mechanism, and the method comprises the steps: obtaining a to-be-detected integrated circuit design, and carrying out the flattening processing; converting the flattened integrated circuit design to be tested into an abstract syntax tree; extracting paths from all leaf nodes to leaf nodes in the to-be-tested integrated circuit design based on the abstract syntax tree; inputting all the extracted paths into a code2vec model, and carrying out binary classification on the integrated circuit design to be detected to realize hardware Trojan horse detection; and sorting the attention scores of the paths obtained by the attention layer calculation of the code2vec model in the classification process according to a descending order, selecting a plurality of important paths with the highest attention score, and providing explanation for a detection result based on code information contained in the important paths. According to the method, automatic detection of the hardware Trojan horse in register transfer level integrated circuit design is realized, a decision mechanism of the model can be obtained based on an attention mechanism, and a detection result is explained.

The present disclosure presents systems and methods performing a simulation on a hybrid virtual system-on-chip (SoC) model. One such method comprises receiving a configuration file that identifies register transfer level (RTL) abstractions; virtual prototype abstractions; unit-level testbenches; place holder variables; and a shared interface among one or more hardware circuitry blocks designed as RTL abstractions and one or more hardware circuitry blocks designed as virtual prototype abstractions; creating the hybrid virtual SoC model based on the configuration file by instantiating the one or more hardware circuitry blocks designed as RTL abstractions and a stub hardware circuitry block for each of the one or more hardware circuitry blocks designed as virtual prototype abstractions; and integrating unit-level testbenches for the one or more hardware circuitry blocks represented as RTL abstractions.

The embodiment of the invention discloses a chip verification method and device, electronic equipment and a storage medium, relates to the technical field of semiconductors, and can effectively improve the chip verification efficiency. The method comprises the steps that a chip simulation model of a to-be-verified chip is acquired, the to-be-verified chip comprises at least two circuit modules which are mutually connected, and the at least two circuit modules comprise a first circuit module and a second circuit module; the chip simulation model comprises a first simulation model, a first interface function, a second simulation model and a second interface function; wherein the first simulation model is a register transfer level simulation model of the first circuit module, and the second simulation model is a transaction level simulation model of the second circuit module; the first interface function is used for being called by the first simulation model to access a target memory; the second interface function is used for being called by a second simulation model to access the target memory; and running the chip simulation model to verify the to-be-verified chip. The method can be applied to chip verification.

The present disclosure provides a register transfer level encoding generation method, device and computer equipment. The method comprises: parsing a target document according to a target document format to locate a register mapping table of one or more registers in the target document; traversing the content in each unit in the register mapping table to parse to obtain the name of the one or more registers and one or more addresses respectively associated with each register; for each register, searching at a specified position of the target document based on the name of the register to locate a register bit field description table corresponding to the register, obtaining the bit field information of the register by traversing the register bit field description table, and associating the bit field information with the name of the register; forming a register configuration dictionary based on the name of the register and the addresses and bit field information respectively associated with the name of each register; and generating a register configuration file and a corresponding register transfer level encoding based on the register configuration dictionary.

The application relates to an RTL level splitting method and system for multiple FPGAs, which are applied to the technical field of FPGAs, wherein FPGA refers to Field-Programmable Gate Array, and RTL level refers to Register Transfer Level; the method comprises the following steps: receiving and statically and exhaustively analyzing an RTL design file to obtain an RTL design processing file and an RTL tree structure file; splitting the RTL design processing file to obtain a splitting result file comprising a plurality of splitting areas; performing RTL splitting on the RTL tree structure file to obtain a plurality of RTL file lists corresponding to the plurality of splitting areas and boundary interconnection information; performing parallel synthesis according to the plurality of RTL file lists to obtain a plurality of synthesized netlist Verilog files; binding the plurality of synthesized netlist Verilog files according to the boundary interconnection information by using time division multiplexing channels to obtain a plurality of bound netlist Verilog files and constraint files; and performing top constraint and layout wiring according to the plurality of bound netlist Verilog files and the constraint files, and then performing multiple FPGA verification. The application has the technical effect that design codes can be better verified on multiple FPGAs.

Design metrics from the physical design of an integrated circuit are made available to the front end designer. Physical design metrics are computed for sub-circuits from the physical design of an integrated circuit. Examples of physical design metrics include metrics for timing, congestion, power consumption and other metrics that depend on physical aspects of the circuit. Correspondence between the sub-circuits and register transfer level (RTL) source elements from RTL source code for the integrated circuit are determined. Examples of RTL source elements include individual lines of RTL source code, modules in the RTL source code, and user-defined constructs in the RTL source code. For different RTL source elements, the physical design metrics for the corresponding sub-circuits are aggregated. These aggregated physical design metrics, including the associations to the corresponding RTL source elements, are made available to users, for example front end designers.

Embodiments of the present application disclose a signal recovery method and system, electronic equipment and storage medium, and relate to the technical field of integrated circuit verification, which can improve verification efficiency. The method comprises: determining a plurality of scattered unit signals corresponding to a multi-bit-width signal in a netlist level based on a target signal list and a signal naming mapping table, the target signal list comprising a multi-bit-width signal to be processed, and the signal naming mapping table being used to record a mapping relationship between a hierarchical path from a register transfer level to the netlist level and a signal name; performing operation on a reset initial value of each bit-width signal at the register transfer level and a waveform initial value corresponding to the netlist level to generate a logic polarity correction sequence; and generating a debugging configuration file according to the logic polarity correction sequence, the debugging configuration file being used to instruct recovery of the plurality of scattered unit signals into the multi-bit-width signal consistent with the register transfer level logic. The present application is applicable to a scenario of netlist timing simulation debugging.

Embodiments of the present application provide a hardware design method and device. The method comprises: obtaining a design task and design specification; if the proportion of description information of graphical hardware with specific spatial or timing semantics in the design specification does not exceed a preset proportion threshold, determining that the design task is a text dominant task, and generating register transfer level code through a large language model according to the text dominant task and the corresponding design specification; otherwise, determining that the design task is a component dominant task, calling a tool through a large language model according to the component dominant task and the corresponding design specification; and generating register transfer level code according to the tool; the tool comprises a retrieval enhanced knowledge base, a rule type script and an electronic design automation simulation verification tool. The scheme of the present application improves the accuracy of hardware design.