To efficiently use resources in FPGA by eliminating auxiliary
processing circuits that are provided in an FPGA circuit in preparation for
software error and do not operate in normal
processing.SOLUTION: A
data processing system includes a computing unit comprising a programmable device, and an
arithmetic processing unit connected to the computing unit. The computing unit includes: a plurality of
processing circuits that executes, in parallel,
data processing instructions provided from the
arithmetic processing unit; an error detection unit which detects
software error generated in a processing circuit executing a
data processing instruction; and a processing circuit selection unit which selects a processing circuit to execute the data
processing instruction from among the plurality of processing circuits. The processing circuit selection unit identifies a processing circuit in which the
software error occurred, on the basis of the
software error detected by the error detection unit, and selects a processing circuit to execute the data
processing instruction, excluding the processing circuit in which the
software error occurred, out of the plurality of processing circuits.SELECTED DRAWING: Figure 1