41141results about How to "Increase speed" patented technology

The invention relates to the discovery of novel soluble neutral active Hyaluronidase Glycoproteins (sHASEGPs), methods of manufacture, and their use to facilitate administration of other molecules or to alleviate glycosaminoglycan associated pathologies. Minimally active polypeptide domains of the soluble, neutral active sHASEGP domains are described that include asparagine-linked sugar moieties required for a functional neutral active hyaluronidase domain. Included are modified amino-terminal leader peptides that enhance secretion of sHASEGP. The invention further comprises sialated and pegylated forms of a recombinant sHASEGP to enhance stability and serum pharmacokinetics over naturally occurring slaughterhouse enzymes. Further described are suitable formulations of a substantially purified recombinant sHASEGP glycoprotein derived from a eukaryotic cell that generate the proper glycosylation required for its optimal activity.

The invention relates to the discovery of novel soluble neutral active Hyaluronidase Glycoproteins (sHASEGPs), methods of manufacture, and their use to facilitate administration of other molecules or to alleviate glycosaminoglycan associated pathologies. Minimally active polypeptide domains of the soluble, neutral active sHASEGP domains are described that include asparagine-linked sugar moieties required for a functional neutral active hyaluronidase domain. Included are modified amino-terminal leader peptides that enhance secretion of sHASEGP. The invention further comprises sialated and pegylated forms of a recombinant sHASEGP to enhance stability and serum pharmacokinetics over naturally occurring slaughterhouse enzymes. Further described are suitable formulations of a substantially purified recombinant sHASEGP glycoprotein derived from a eukaryotic cell that generate the proper glycosylation required for its optimal activity.

A runtime adaptable search processor is disclosed. The search processor provides high speed content search capability to meet the performance need of network line rates growing to 1 Gbps, 10 Gbps and higher. he search processor provides a unique combination of NFA and DFA based search engines that can process incoming data in parallel to perform the search against the specific rules programmed in the search engines. The processor architecture also provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also provide packet inspection through Layer 7. Further, a runtime adaptable processor is coupled to the protocol processing hardware and may be dynamically adapted to perform hardware tasks as per the needs of the network traffic being sent or received and/or the policies programmed or services or applications being supported. A set of engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A high performance content search and rules processing security processor is disclosed which may be used for application layer and network layer security. scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through RDMA data transfer. A security system is also disclosed that enables a new way of implementing security capabilities inside enterprise networks in a distributed manner using a protocol processing hardware with appropriate security features.

A method and system of inputting alphabetic text having a virtual keyboard on a touch sensitive screen. The virtual keyboard includes a set of keys where an each letter of alphabet is associated with at least one key. The present invention allows someone to use the virtual keyboard with continuous contact of the touch sensitive screen. The user traces an input pattern for word by starting at or near the first letter in a decided word and then tracing through or near each letter in sequence. The present invention then generates a list of possible words associated with the entered part and presents it to user for selection.

An Internet-based server with speech support for enhanced interactivity is disclosed. This server hosts a server-side speech recognition engine and additional linguistic and database functions that cooperate to provide enhanced interactivity for clients so that their browsing experience is more satisfying, efficient and productive. This human-like interactivity which allows the user to ask queries about topics that range from customer delivery, product descriptions, payment details, is facilitated by the allowing the user to articulate the his or her questions directly in his or her natural language. The answer typically provided in real-time, can also be interfaced and integrated with existing telephone, e-mail and other mixed media services to provide a single point of interactivity for the user when browsing at a web-site.

A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (i.e., B and P) into the body. The invention reduces the problem of short channel effects such as drain induced barrier lowering and the leakage current from the source to drain regions via the hetero-junction and while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. The problem of scalability of the gate length below 100 nm is overcome by the heterojunction between the source and body regions.