89 results about "Gate length" patented technology

The present application provides an all-digital multi-phase DC-DC controller. The digital DC-DC controller includes time-based analog-to-digital converters (ADCs) for converting analog voltage signals into digital-domain signals so as to benefit from gate length scaling without limited by the low voltage swing. Also, the DC-DC controller further includes a digital control circuit and a time-based modulator. The digital control circuit can control the time-based modulator in a digital domain, thereby reducing the affection caused by process, voltage and temperature (PVT) variation. Also, the time-based modulator can adjust the timing of the PWM signals and avoid the performance degradation caused by circuit mismatch. Since the digital control circuit can be fully synthesizable, it allows implementations in all kinds of digital CMOS processes with a small chip area.

Device structures and fabrication methods for MOSFETs having a novel multiple-conductive layer “T”-shaped gate (as viewed in cross-section). The novel “T-gate” significantly decreases the gate resistance RG of a MOSFET device and thus increases the figure-of-merit fMAX (the maximum device oscillation frequency, or the frequency at which the maximum power gain equals unity) and reduces the noise factor (NF) of the device. Fabrication of the novel MOSFET devices may be readily integrated into existing IC fabrication processes, and such MOSFETs may have gate lengths Lg scaled below the lithographic capabilities of the fabrication process. Some embodiments include conformal gate side-spacers. Some embodiments include non-conformal air-gapped gate side-spacers that result in reduced parasitic gate-to-source capacitance CGS and gate-to-drain capacitance CGD, with concomitant improved performance at high radio frequencies (RF). Embodiments of the novel MOSFET device enable RF circuits, such as low-noise amplifiers (LNAs), to exhibit a better noise figure parameter, NFmin.

The embodiment of the invention provides a parameter space degree of freedom determination method and device, electronic equipment and a storage medium, and the scheme is as follows: according to a first working frequency and a second working frequency corresponding to a first quantum bit and a second quantum bit under the condition that the frequency detuning is 0, and a third working frequency of an adjustable coupler under a preset gate length, determining the degree of freedom of a parameter space; calculating target coupling strength; according to periodic quantum logic gate operations on the first quantum bit and the second quantum bit under different frequency detuning conditions, obtaining a first corresponding relation between frequency detuning and a leakage rate, and obtaining a second corresponding relation between frequency detuning and a preset condition phase; and based on the first corresponding relation and the second corresponding relation, obtaining first detuning and second detuning corresponding to the lowest leakage rate under the target phase as target detuning parameters. According to the technical scheme provided by the embodiment of the invention, the influence of the distortion of the residual short time scale on the magnetic flux control line on the quantum calculation process can be avoided, so that the fidelity of quantum calculation is improved.

A semiconductor device 1 comprises: a collector layer 5; a drift layer 4 stacked on the collector layer 5; a base layer 32 stacked on the drift layer 4; first gates 21 arranged side by side on the drift layer 4 in the gate length direction; and second gates 22 which are arranged side by side with some of the first gates 21 and which can be driven independently of the first gates 21. The semiconductor device is partitioned into a first region Hc and a third region Ts where the first gates 21 are disposed, and a second region Hs where the first gates 21 and the second gates 22 are disposed. The semiconductor device is disposed such that the third region Ts is disposed between the first region Hc and the second region Hs in the gate length direction. In the collector layer 5, the carrier concentration in the second region Hs and the third region Ts is lower than the carrier concentration in the first region Hc.

A semiconductor device includes a dual-stage Schottky barrier. The dual-stage Schottky barrier includes a first stage and a second stage. The first stage is formed over a substrate stack and includes an upper layer having a length corresponding to a gate length for the device. The second stage is formed at least partially over the first stage and includes a contact segment having a length less than the gate length.

The application relates to the technical field of field effect transistor devices, and discloses a two-dimensional material field effect transistor and a preparation method thereof. The two-dimensional material field effect transistor comprises a substrate insulating layer, a gate layer, a gate contact electrode, a vertical electric field shielding structure, a second insulating layer and a conductive channel film which are arranged in a stack. A second step and a third step are formed on the side of the conductive channel film away from the second insulating layer; the second step and the third step are arranged along the stacking direction. A first contact electrode is formed on the second step surface through oblique angle deposition, and a second contact electrode is formed on the third step surface through oblique angle deposition; the side surface of the first contact electrode facing the third step is aligned with the end of the second step surface facing the third step. The first contact electrode and the second contact electrode are deposited through the oblique angle deposition mode, the dependence on a photoetching device and a overlay process precision in the development process of the existing field effect transistor is reduced, and the channel length and the gate length are simultaneously micronized.

A semiconductor device includes a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate. A passivation layer covers the semiconductor barrier layer. A first gate electrode and a second gate electrode are laterally separated from each other and at least partially disposed in the passivation layer respectively. Along a first direction, a first gate length of the first gate electrode is less than a second gate length of the second gate electrode. A source electrode and a drain electrode are disposed on the semiconductor channel layer. The second gate electrode is electrically connected to the source electrode. The first gate electrode and the second gate electrode are electrically isolated from each other.

A gate electrode (107) comprises: a leg part (107a); a first head part (107b); a second head part (107c); a first lateral part (107d); and a second lateral part (107e). The first head part (107b) is continuously formed above the leg part (107a), and is longer in length than the leg part (107a) in the gate length direction. The first lateral part (107d) and the second lateral part (107e) are continuously formed at both ends in the gate length direction of the first head part (107b). The second head part (107c) is continuously formed above at least one of the first lateral part (107d) and the second lateral part (107e), and is longer in length than the leg part (107a) in the gate length direction. In this example, the second head part (107c) is continuously formed above both the first lateral part (107d) and the second lateral part (107e).

A field effect transistor (FET) transconductance device with varying gate lengths is disclosed. In one aspect, the varying effective gate lengths are used in a differential architecture to obtain linear even and odd order operation simultaneously. In a particular aspect, the effective gate lengths may be varied according to a differential Multi-Tanh-like architecture. This variation of effective gate lengths enables a compact implementation particularly as compared to varying gate width or emitter areas while also providing linear even and odd order operation simultaneously.

A semiconductor device includes an offset drain region and a p-type well. In a gate length direction of a gate electrode, a first distance between the offset drain region and a first portion of the p-type well is larger than a second distance between the offset drain region and a second portion of the p-type well. The semiconductor device includes an n-type semiconductor region formed in a portion of an epitaxial layer located between the offset drain region and a source region.

A transistor structure includes a substrate and an active area defined by a trench isolation region on the substrate. The active area includes a source region, a drain region spaced apart from the source region, and a channel region between the source region and the drain region. A gate is disposed on the channel region. The gate has a gate length that is in parallel with a source-to-drain direction and a gate width that is smaller than a width of the active area.

A method for manufacturing a semiconductor-on-insulator (SeOI) chip comprises: a) providing a SeOI structure, b) building a plurality of isolated field effect transistors (FET) each comprising: —a preliminary gate above a channel region, the FETs from a first group having a first preliminary gate length and the FETs from a second group having a smaller second preliminary gate length, —a source region and a drain region, and —a source electrode and a drain electrode, c) removing at least the preliminary gates of the FETs from the second group, leaving access to channel regions of the FETs, d) thinning a top layer in channel regions of the FETs from the second group, the top layer in channel regions of the first group of FETs having a different thickness, and e) forming functional gates simultaneously on channel regions of the FETs whose preliminary gates were removed.

Disclosed is a structure including a field effect transistor (FET). The FET includes, on an insulator layer above a substrate, source / drain regions and a section of a semiconductor layer extending laterally between the source / drain regions. A primary gate structure is made of the insulator layer and a well region in the substrate opposite at least the section of the semiconductor layer extending laterally between the source / drain regions. One or two secondary gate structures are on the semiconductor layer between and near one or both of the source / drain regions, respectively. The FET can further include a patterned conformal dielectric layer, which is on the center of the semiconductor layer between the source / drain regions, and which extends onto the secondary gate structure(s). Also disclosed are methods of operating the structure by biasing the secondary gate structure(s) to adjust the effective gate length of the FET and methods of forming the structure.

The present invention provides a reference voltage generation device which includes a constant current circuit outputting a constant current in response to an input voltage; a voltage generation circuit connected in series to the constant current circuit, using the constant current as an input current, and generating an output voltage based on the input current; and a reference voltage output port outputting the output voltage. In the constant current circuit, multiple depletion type MOS transistors are connected in series, the gate widths are the same, and the sum of the gate lengths is the total gate length of the constant current circuit. In the voltage generation circuit, multiple enhancement type MOS transistors are connected in series, the gate widths are the same, and the sum of the gate lengths is the total gate length of the voltage generation circuit.

Circuits and methods for integrated circuits particularly useful in high-quality low-noise amplifiers (LNA) that are sensitive, provide good amplification, are physically compact, and can withstand relatively high drain-to-source voltages. LNA embodiments include an N-type MOSFET (NFET) or P-type MOSFET (PFET) device co-fabricated with one or more serially-coupled asymmetric PFET devices of several types. The asymmetry of the novel asymmetric PFET device provides a shorter gate length (LG) and thus a higher transconductance (gm). In addition, the inventive asymmetric PFET device has a higher hole mobility brought about by introducing strain in the conduction channel (especially at or near the source of the device) and / or by use of silicon germanium (SiGe) regions within the asymmetric PFET structure. The resulting asymmetric PFET devices have higher Vtsat and lower built-in voltage Vbi (thus higher IDS) characteristics than conventional symmetric PFET devices.

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a fin-shaped active region over a substrate and comprising a number of channel layers interleaved by a number of sacrificial layers, removing a source / drain region of the fin-shaped active region to form a source / drain opening, forming a source / drain feature in the source / drain opening, selectively removing the number of sacrificial layers to form a number of gate openings, and forming a gate structure in the number of gate openings, where the gate structure includes a first portion formed in a first gate opening of the number of gate openings and a second portion formed in a second gate opening of the number of gate openings, a gate length of the first portion is different from a gate length of the second portion.

This invention discloses a method for establishing and extracting a charge model for HEMT transistors based on GaN technology, comprising: obtaining the gate-channel voltage based on externally input gate voltage, drain potential, and source potential; obtaining the gate charge based on gate charge density, number of gate elements, gate length, and width of a single gate element; obtaining the drain-source potential difference based on the drain potential and source potential; establishing a charge model based on the gate-channel voltage, gate charge, and drain-source potential difference to characterize the correlation between charge value and drain-source voltage after the transistor device is turned on; and differentiating the charge value of the charge model to establish a capacitance model to characterize the correlation between gate-source capacitance, gate-source voltage, and drain-source voltage. This invention supports the charge / capacitance description of HEMT transistors based on GaN technology, especially the description of the relationship between gate-source capacitance, gate-source voltage, and drain-source voltage after the channel is turned on, with high model accuracy.

The invention provides a semiconductor device and a manufacturing method thereof. Embodiments of the present disclosure provide a method for manufacturing a semiconductor device having a long gate length. A patterned photoresist layer is formed over a device region having a long gate length to achieve process uniformity and improve device density.

The invention discloses a low-temperature transistor modeling gold sample screening method. Firstly, a transistor test structure is designed; secondly, simulating the series of transistors with specific gate lengths and gate widths to obtain a simulation result of a business model under a type corner, and counting a median value used for determining a parameter of a gold sample; and testing the plurality of transistor test structures die at room temperature, comparing the simulation result of each parameter with the actual measurement result, and obtaining an alternative sample of the gold sample according to the standard that each parameter meets the screening criterion. The method is suitable for the gold sample selection process before the low-temperature integrated circuit establishes the intensive model, the gold sample screening efficiency can be greatly improved, and a large amount of manpower and material resources and time cost are saved.

The utility model provides a semiconductor assembly which comprises a memory unit structure. The memory unit structure comprises a transistor structure and a storage structure. The gate of the transistor structure extends in a direction substantially perpendicular to the substrate surface of the semiconductor component, which enables the gate length to increase without increasing or minimizing the horizontal or lateral dimensions of the memory cell structure. The channel layer may be a U-shaped layer in that the channel layer is included on at least two of a sidewall and a bottom surface of the gate. This design increases the channel area of the transistor structure, enabling low current leakage of the memory cell structure, and enabling high lateral density of the memory cell structure in the semiconductor device.

The invention relates to the technical field of field effect transistor devices, and discloses a two-dimensional material field effect transistor and a preparation method thereof. The two-dimensional material field effect transistor comprises a substrate insulating layer, a gate layer, a gate contact electrode, a vertical electric field shielding structure, a second insulating layer and a conductive channel film which are arranged in a stacked mode. A second step and a third step are formed on one side, far away from the second insulating layer, of the conductive channel film; the second step and the third step are arranged in the stacking direction. Forming a first contact electrode on the second step surface through oblique angle deposition, and forming a second contact electrode on the third step surface through oblique angle deposition; one side surface of the first contact electrode facing the third step is aligned with one end of the second step surface facing the third step. The first contact electrode and the second contact electrode are deposited in an oblique angle deposition mode, the dependence on photoetching equipment and overlay process precision in the development process of an existing field effect transistor is reduced, and synchronous miniaturization of the channel length and the grid electrode length is achieved.

A gate-all-around transistor includes a gate structure having sidewalls; a first and a second gate spacer positioned laterally on each sidewall, wherein the gate structure has a gate length between the sidewalls of the gate structure, the gate length having a midpoint; a first inner spacer under the first gate spacer; and a second inner spacer under the second gate spacer. A channel layer extends from below the first inner spacer, across the gate length to below the second inner spacer. The channel layer includes a first region having a first thickness and located below each of the gate spacers; and a second region having a continuously variable thickness, the second region located laterally between the first regions and being symmetrical in reference to the midpoint of the gate length.

Embodiments with present disclosure provide a method for fabricating a semiconductor device with long gate lengths. A patterned photoresist layer is formed over device areas with long gate lengths to enable process uniformity and improve device density.

Semiconductor devices and methods of forming the same are provided. An exemplary method includes forming a first fin and a second fin, each of the first fin and the second fin including a plurality of channel layers interleaved with a plurality of sacrificial layers; forming a first gate stack and a second gate stack over the first fin and the second fin, respectively, the first gate stack and the second gate stack having different gate lengths; forming a first source / drain feature adjacent to the first gate stack and a second source / drain feature adjacent to the second gate stack; after forming the second source / drain feature, an ion implantation process is performed to increase a dopant concentration of an upper portion of the second source / drain feature.

The present disclosure provides a semiconductor device and a manufacturing method therefor. The method includes: providing a semiconductor structure, the semiconductor structure including a semiconductor substrate, a gate disposed on the semiconductor substrate, and an interlayer dielectric layer covering the semiconductor substrate and the gate; wherein the semiconductor structure further includes a first source / drain region and a second source / drain region; defining first connecting holes and at least one first air hole on the first source / drain region and / or the second source / drain region; wherein at least one first air hole is arranged between each adjacent two first connecting holes in an X direction and / or a Y direction, the X direction being a gate length direction, the X direction being perpendicular to the Y direction; sealing each first air hole to define a first cavity in the first air hole; and filling each first connecting hole with a conductive material.

The transistor includes one or more tapered inner spacers. The tapered inner spacer may include a base region that extends or protrudes beyond a plane coplanar with the first sidewall of the gate. The base region may reduce a gate length of the gate adjacent the base region. When the two base regions are associated with the same gate, the two base regions may merge and may be between and / or isolated from the underlying substrate. The tapered inner spacers may reduce parasitic capacitance between the gate and the substrate and / or between the gate and adjacent source / drain regions, and / or may reduce current leakage from the gate into the substrate or other underlying structures.

A method, system and computer program product for calibrating a quantum operation. Layers of two qubit gates that operate in parallel are defined. A gate length for each two qubit gate in a layer of the defined layers is calibrated to correspond to the same gate length, such as the gate length of the two qubit gate in that layer with the slowest operation speed. A portion of the quantum operation is performed by the two qubit gates in the layer with the calibrated gate length. In this manner, two qubit gates that operate in parallel are effectively calibrated in a manner that results in better gate fidelities, fewer frequency collisions and fewer undesirable transitions.

The application provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprising: a substrate, a source, a drain, a gate and a channel structure arranged on one side of the substrate, the channel structure comprising a plurality of nanosheet formed stacks, and the gate surrounding the nanosheet. In the application, the substrate can comprise a first substrate and a second substrate arranged in sequence, wherein the first substrate is a semiconductor material, and the second substrate is an insulating material, that is, the substrate of the application is a semiconductor-on-insulator substrate, so that the performance of the GAAFET can be optimized. The semiconductor device provided by the application comprises an isolation structure arranged between the channel structure and the second substrate, and the isolation structure extends to the source and the drain in a direction parallel to the plane where the substrate is located, so that effective isolation is formed between the substrate, the gate, the drain and the source, and the parasitic channel leakage of the substrate is inhibited by using the isolation structure, thereby reducing the off-state leakage current of the device under a shorter gate length and improving the overall performance of the device.

Transistors, devices, systems, and methods are discussed related to transistors including 2D material channels and heterogeneous 2D materials on the 2D material channels and coupled to source and drain metals, and their fabrication. The 2D material channels of the transistor allow for gate length scaling, improved switching performance, and other advantages and the heterogeneous 2D materials improve contact resistance of the transistor devices.

A semiconductor device includes a field effect transistor (FET). The FET includes a gate electrode in a gate layer. The gate electrode has a first gate length and a second gate length. The second gate length is greater than the first gate length. The FET also includes an active region in a active region layer. The active region includes a source region and a drain region. The active region layer is beneath the gate layer. The FET has a first channel under the gate electrode having the first gate length and between the source region and the drain region. The FET also has a second channel under the gate electrode having the second gate length and between the source region and the drain region.