57 results about "Gate length" patented technology

Device structures and fabrication methods for MOSFETs having a novel multiple-conductive layer “T”-shaped gate (as viewed in cross-section). The novel “T-gate” significantly decreases the gate resistance RG of a MOSFET device and thus increases the figure-of-merit fMAX (the maximum device oscillation frequency, or the frequency at which the maximum power gain equals unity) and reduces the noise factor (NF) of the device. Fabrication of the novel MOSFET devices may be readily integrated into existing IC fabrication processes, and such MOSFETs may have gate lengths Lg scaled below the lithographic capabilities of the fabrication process. Some embodiments include conformal gate side-spacers. Some embodiments include non-conformal air-gapped gate side-spacers that result in reduced parasitic gate-to-source capacitance CGS and gate-to-drain capacitance CGD, with concomitant improved performance at high radio frequencies (RF). Embodiments of the novel MOSFET device enable RF circuits, such as low-noise amplifiers (LNAs), to exhibit a better noise figure parameter, NFmin.

The embodiment of the invention provides a parameter space degree of freedom determination method and device, electronic equipment and a storage medium, and the scheme is as follows: according to a first working frequency and a second working frequency corresponding to a first quantum bit and a second quantum bit under the condition that the frequency detuning is 0, and a third working frequency of an adjustable coupler under a preset gate length, determining the degree of freedom of a parameter space; calculating target coupling strength; according to periodic quantum logic gate operations on the first quantum bit and the second quantum bit under different frequency detuning conditions, obtaining a first corresponding relation between frequency detuning and a leakage rate, and obtaining a second corresponding relation between frequency detuning and a preset condition phase; and based on the first corresponding relation and the second corresponding relation, obtaining first detuning and second detuning corresponding to the lowest leakage rate under the target phase as target detuning parameters. According to the technical scheme provided by the embodiment of the invention, the influence of the distortion of the residual short time scale on the magnetic flux control line on the quantum calculation process can be avoided, so that the fidelity of quantum calculation is improved.

The application relates to the technical field of field effect transistor devices, and discloses a two-dimensional material field effect transistor and a preparation method thereof. The two-dimensional material field effect transistor comprises a substrate insulating layer, a gate layer, a gate contact electrode, a vertical electric field shielding structure, a second insulating layer and a conductive channel film which are arranged in a stack. A second step and a third step are formed on the side of the conductive channel film away from the second insulating layer; the second step and the third step are arranged along the stacking direction. A first contact electrode is formed on the second step surface through oblique angle deposition, and a second contact electrode is formed on the third step surface through oblique angle deposition; the side surface of the first contact electrode facing the third step is aligned with the end of the second step surface facing the third step. The first contact electrode and the second contact electrode are deposited through the oblique angle deposition mode, the dependence on a photoetching device and a overlay process precision in the development process of the existing field effect transistor is reduced, and the channel length and the gate length are simultaneously micronized.

A semiconductor device includes a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate. A passivation layer covers the semiconductor barrier layer. A first gate electrode and a second gate electrode are laterally separated from each other and at least partially disposed in the passivation layer respectively. Along a first direction, a first gate length of the first gate electrode is less than a second gate length of the second gate electrode. A source electrode and a drain electrode are disposed on the semiconductor channel layer. The second gate electrode is electrically connected to the source electrode. The first gate electrode and the second gate electrode are electrically isolated from each other.

A field effect transistor (FET) transconductance device with varying gate lengths is disclosed. In one aspect, the varying effective gate lengths are used in a differential architecture to obtain linear even and odd order operation simultaneously. In a particular aspect, the effective gate lengths may be varied according to a differential Multi-Tanh-like architecture. This variation of effective gate lengths enables a compact implementation particularly as compared to varying gate width or emitter areas while also providing linear even and odd order operation simultaneously.

A transistor structure includes a substrate and an active area defined by a trench isolation region on the substrate. The active area includes a source region, a drain region spaced apart from the source region, and a channel region between the source region and the drain region. A gate is disposed on the channel region. The gate has a gate length that is in parallel with a source-to-drain direction and a gate width that is smaller than a width of the active area.

A method for manufacturing a semiconductor-on-insulator (SeOI) chip comprises: a) providing a SeOI structure, b) building a plurality of isolated field effect transistors (FET) each comprising: —a preliminary gate above a channel region, the FETs from a first group having a first preliminary gate length and the FETs from a second group having a smaller second preliminary gate length, —a source region and a drain region, and —a source electrode and a drain electrode, c) removing at least the preliminary gates of the FETs from the second group, leaving access to channel regions of the FETs, d) thinning a top layer in channel regions of the FETs from the second group, the top layer in channel regions of the first group of FETs having a different thickness, and e) forming functional gates simultaneously on channel regions of the FETs whose preliminary gates were removed.

The present invention provides a reference voltage generation device which includes a constant current circuit outputting a constant current in response to an input voltage; a voltage generation circuit connected in series to the constant current circuit, using the constant current as an input current, and generating an output voltage based on the input current; and a reference voltage output port outputting the output voltage. In the constant current circuit, multiple depletion type MOS transistors are connected in series, the gate widths are the same, and the sum of the gate lengths is the total gate length of the constant current circuit. In the voltage generation circuit, multiple enhancement type MOS transistors are connected in series, the gate widths are the same, and the sum of the gate lengths is the total gate length of the voltage generation circuit.

Circuits and methods for integrated circuits particularly useful in high-quality low-noise amplifiers (LNA) that are sensitive, provide good amplification, are physically compact, and can withstand relatively high drain-to-source voltages. LNA embodiments include an N-type MOSFET (NFET) or P-type MOSFET (PFET) device co-fabricated with one or more serially-coupled asymmetric PFET devices of several types. The asymmetry of the novel asymmetric PFET device provides a shorter gate length (LG) and thus a higher transconductance (gm). In addition, the inventive asymmetric PFET device has a higher hole mobility brought about by introducing strain in the conduction channel (especially at or near the source of the device) and / or by use of silicon germanium (SiGe) regions within the asymmetric PFET structure. The resulting asymmetric PFET devices have higher Vtsat and lower built-in voltage Vbi (thus higher IDS) characteristics than conventional symmetric PFET devices.

This invention discloses a method for establishing and extracting a charge model for HEMT transistors based on GaN technology, comprising: obtaining the gate-channel voltage based on externally input gate voltage, drain potential, and source potential; obtaining the gate charge based on gate charge density, number of gate elements, gate length, and width of a single gate element; obtaining the drain-source potential difference based on the drain potential and source potential; establishing a charge model based on the gate-channel voltage, gate charge, and drain-source potential difference to characterize the correlation between charge value and drain-source voltage after the transistor device is turned on; and differentiating the charge value of the charge model to establish a capacitance model to characterize the correlation between gate-source capacitance, gate-source voltage, and drain-source voltage. This invention supports the charge / capacitance description of HEMT transistors based on GaN technology, especially the description of the relationship between gate-source capacitance, gate-source voltage, and drain-source voltage after the channel is turned on, with high model accuracy.

The invention discloses a low-temperature transistor modeling gold sample screening method. Firstly, a transistor test structure is designed; secondly, simulating the series of transistors with specific gate lengths and gate widths to obtain a simulation result of a business model under a type corner, and counting a median value used for determining a parameter of a gold sample; and testing the plurality of transistor test structures die at room temperature, comparing the simulation result of each parameter with the actual measurement result, and obtaining an alternative sample of the gold sample according to the standard that each parameter meets the screening criterion. The method is suitable for the gold sample selection process before the low-temperature integrated circuit establishes the intensive model, the gold sample screening efficiency can be greatly improved, and a large amount of manpower and material resources and time cost are saved.

The utility model provides a semiconductor assembly which comprises a memory unit structure. The memory unit structure comprises a transistor structure and a storage structure. The gate of the transistor structure extends in a direction substantially perpendicular to the substrate surface of the semiconductor component, which enables the gate length to increase without increasing or minimizing the horizontal or lateral dimensions of the memory cell structure. The channel layer may be a U-shaped layer in that the channel layer is included on at least two of a sidewall and a bottom surface of the gate. This design increases the channel area of the transistor structure, enabling low current leakage of the memory cell structure, and enabling high lateral density of the memory cell structure in the semiconductor device.

The invention relates to the technical field of field effect transistor devices, and discloses a two-dimensional material field effect transistor and a preparation method thereof. The two-dimensional material field effect transistor comprises a substrate insulating layer, a gate layer, a gate contact electrode, a vertical electric field shielding structure, a second insulating layer and a conductive channel film which are arranged in a stacked mode. A second step and a third step are formed on one side, far away from the second insulating layer, of the conductive channel film; the second step and the third step are arranged in the stacking direction. Forming a first contact electrode on the second step surface through oblique angle deposition, and forming a second contact electrode on the third step surface through oblique angle deposition; one side surface of the first contact electrode facing the third step is aligned with one end of the second step surface facing the third step. The first contact electrode and the second contact electrode are deposited in an oblique angle deposition mode, the dependence on photoetching equipment and overlay process precision in the development process of an existing field effect transistor is reduced, and synchronous miniaturization of the channel length and the grid electrode length is achieved.

Embodiments with present disclosure provide a method for fabricating a semiconductor device with long gate lengths. A patterned photoresist layer is formed over device areas with long gate lengths to enable process uniformity and improve device density.

Semiconductor devices and methods of forming the same are provided. An exemplary method includes forming a first fin and a second fin, each of the first fin and the second fin including a plurality of channel layers interleaved with a plurality of sacrificial layers; forming a first gate stack and a second gate stack over the first fin and the second fin, respectively, the first gate stack and the second gate stack having different gate lengths; forming a first source / drain feature adjacent to the first gate stack and a second source / drain feature adjacent to the second gate stack; after forming the second source / drain feature, an ion implantation process is performed to increase a dopant concentration of an upper portion of the second source / drain feature.

The present disclosure provides a semiconductor device and a manufacturing method therefor. The method includes: providing a semiconductor structure, the semiconductor structure including a semiconductor substrate, a gate disposed on the semiconductor substrate, and an interlayer dielectric layer covering the semiconductor substrate and the gate; wherein the semiconductor structure further includes a first source / drain region and a second source / drain region; defining first connecting holes and at least one first air hole on the first source / drain region and / or the second source / drain region; wherein at least one first air hole is arranged between each adjacent two first connecting holes in an X direction and / or a Y direction, the X direction being a gate length direction, the X direction being perpendicular to the Y direction; sealing each first air hole to define a first cavity in the first air hole; and filling each first connecting hole with a conductive material.

The transistor includes one or more tapered inner spacers. The tapered inner spacer may include a base region that extends or protrudes beyond a plane coplanar with the first sidewall of the gate. The base region may reduce a gate length of the gate adjacent the base region. When the two base regions are associated with the same gate, the two base regions may merge and may be between and / or isolated from the underlying substrate. The tapered inner spacers may reduce parasitic capacitance between the gate and the substrate and / or between the gate and adjacent source / drain regions, and / or may reduce current leakage from the gate into the substrate or other underlying structures.

A method, system and computer program product for calibrating a quantum operation. Layers of two qubit gates that operate in parallel are defined. A gate length for each two qubit gate in a layer of the defined layers is calibrated to correspond to the same gate length, such as the gate length of the two qubit gate in that layer with the slowest operation speed. A portion of the quantum operation is performed by the two qubit gates in the layer with the calibrated gate length. In this manner, two qubit gates that operate in parallel are effectively calibrated in a manner that results in better gate fidelities, fewer frequency collisions and fewer undesirable transitions.

The application provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprising: a substrate, a source, a drain, a gate and a channel structure arranged on one side of the substrate, the channel structure comprising a plurality of nanosheet formed stacks, and the gate surrounding the nanosheet. In the application, the substrate can comprise a first substrate and a second substrate arranged in sequence, wherein the first substrate is a semiconductor material, and the second substrate is an insulating material, that is, the substrate of the application is a semiconductor-on-insulator substrate, so that the performance of the GAAFET can be optimized. The semiconductor device provided by the application comprises an isolation structure arranged between the channel structure and the second substrate, and the isolation structure extends to the source and the drain in a direction parallel to the plane where the substrate is located, so that effective isolation is formed between the substrate, the gate, the drain and the source, and the parasitic channel leakage of the substrate is inhibited by using the isolation structure, thereby reducing the off-state leakage current of the device under a shorter gate length and improving the overall performance of the device.

Transistors, devices, systems, and methods are discussed related to transistors including 2D material channels and heterogeneous 2D materials on the 2D material channels and coupled to source and drain metals, and their fabrication. The 2D material channels of the transistor allow for gate length scaling, improved switching performance, and other advantages and the heterogeneous 2D materials improve contact resistance of the transistor devices.

A semiconductor device includes a field effect transistor (FET). The FET includes a gate electrode in a gate layer. The gate electrode has a first gate length and a second gate length. The second gate length is greater than the first gate length. The FET also includes an active region in a active region layer. The active region includes a source region and a drain region. The active region layer is beneath the gate layer. The FET has a first channel under the gate electrode having the first gate length and between the source region and the drain region. The FET also has a second channel under the gate electrode having the second gate length and between the source region and the drain region.

This invention discloses a storage-computing-display driving array of sub-10 nanometer gate-length ferroelectric transistors and its fabrication method, relating to the field of display driving technology. The array structure includes a supporting substrate, vertical sub-10 nanometer gate-length ferroelectric transistors, and micro-light-emitting diodes (LEDs). The vertical sub-10 nanometer gate-length ferroelectric transistors serve as the driving units of the array, and the micro-LEDs serve as the light-emitting units. The light-emitting units and their corresponding driving units are directly stacked and integrated in the vertical direction. This invention natively integrates storage and computing functions into the display pixel unit, enabling in-situ data processing and feature extraction on the display module, thereby breaking through the physical bottleneck of data transport and opening up a new display strategy integrating storage, computing, and display.

A High Electron Mobility Transistor, HEMT, structure (1) having a gate (G), a source (S) and a drain (D), said HEMT structure comprising a depletion-mode transistor (3) having a breakdown voltage, current limiting means (9) arranged for ensuring that a drain source current of said HEMT structure, in an off-state of said HEMT structure, is at most 20 nA / mm, being a current per unit gate length of the depletion-mode transistor, wherein the HEMT structure may comprise a cascode configuration of said depletion-mode transistor with an enhancement mode transistor (6). The current limiting means may be embodied by a bleed resistor 9 that may additionally prevent the enhancement-mode transistor to enter avalanche. The bleed resistor may be connected between the gate terminal of the enhancement-mode transistor and the source terminal of the enhancement-mode transistor.

The invention belongs to a functional device, discloses a wide bandgap semiconductor device, and particularly relates to a high-linearity GaN HEMT (High Electron Mobility Transistor) device based on channel resistance modulation, the gate-source spacing is 0.1-10 microns, the gate length is 0.5-10 microns, and the gate-drain spacing is 0.1-10 microns. From the perspective of the device, the concentration of current carriers in a region between a gate and a source of the device is improved through the design of an epitaxial structure, the linearity is improved on the premise of ensuring wide-range gate-source voltage (Vgs), and the complexity of circuit design is not increased. According to the invention, parameters such as Al components and heights of barrier layers in different regions are designed, and the characteristic that channel turn-on voltages in different regions under the gate are different is utilized, so that the transconductance flatness is increased from another dimension, and the linearity of the device is further improved.

A high electron mobility transistor (HEMT) structure having a gate, a source, and a drain, the HEMT structure comprising: a depletion mode transistor having a breakdown voltage; a current limiting member arranged to ensure that a drain-source current of the HEMT structure is a maximum of 20 nA / mm in an off state of the HEMT structure, the drain-source current being a current per unit gate length of the depletion mode transistor, wherein the HEMT structure may include only the depletion mode transistor, or a cascode configuration of a depletion mode transistor and an enhancement mode transistor.

The application discloses a T-shaped gate preparation method based on electron beam exposure, which comprises the following steps: covering two layers of photoresists with different sensitivities on a substrate, exposing and developing to obtain a gate leg photoetching mask structure; depositing metal on the substrate with the gate leg photoetching mask structure; stripping the gate leg metal structure formed by the two layers of photoresist masks to obtain the gate leg attached to the substrate; spin-coating three layers of photoresists on the substrate with the gate leg; forming a gate cap photoetching mask structure for forming a gate cap through the second upper layer of photoresist and the middle layer of photoresist, and forming a gate cap support layer through the second lower layer of photoresist; depositing metal on the substrate with the gate cap photoetching mask and the gate cap support layer mask to obtain a gate cap metal structure; and stripping the gate cap metal structure to obtain a complete T-shaped gate attached to the substrate. The application reduces process damage, avoids the problem that the foot cap dose influences each other when the T-shaped gate is prepared, and is beneficial to the preparation of a T-shaped gate with a shorter gate length.

This application provides a semiconductor radio frequency (RF) device and its fabrication method. The semiconductor RF device includes, from bottom to top, a substrate and an n-type source doped layer; a ridge channel structure located in the middle, a first heterostructure layer disposed on one side of the ridge channel structure, and a second heterostructure layer disposed on the other side of the ridge channel structure; a drain electrode disposed on the ridge channel structure; a gate dielectric and a gate electrode disposed on the first and second heterostructure layers; a back hole structure disposed on the side of the substrate away from the n-type source doped layer, exposing the n-type source doped layer; a source electrode disposed in the back hole structure of the substrate; and a two-dimensional electron gas on the sidewall of the ridge channel structure of the first heterostructure layer. The above device is a vertical structure design, which can achieve higher device density compared to a horizontal structure. The gate length and channel size can be controlled by the film thickness, which reduces the precision requirements of the photolithography equipment and makes manufacturing easier.

Device structures and fabrication methods for MOSFETs having a novel multiple-conductive layer "T"-shaped gate (as viewed in cross-section). The novel "T-gate" significantly decreases the gate resistance RG of a MOSFET device and thus increases the figure-of-merit f MAX (the maximum device oscillation frequency, or the frequency at which the maximum power gain equals unity) and reduces the noise factor (NF) of the device. Fabrication of the novel MOSFET devices may be readily integrated into existing IC fabrication processes, and such MOSFETs may have gate lengths Lg scaled below the lithographic capabilities of the fabrication process. Some embodiments include conformal gate side-spacers. Some embodiments include non-conformal air-gapped gate side-spacers that result in reduced parasitic gate-to-source capacitance CGS and gate-to-drain capacitance CGD, with concomitant improved performance at high radio frequencies (RF). Embodiments of the novel MOSFET device enable RF circuits, such as low-noise amplifiers (LNAs), to exhibit a better noise figure parameter, NFmin.

Embodiments of the disclosure provide a structure with a back-gate having oppositely doped semiconductor regions. The structure may include a transistor over a substrate. The transistor includes a gate structure having a gate length. A back-gate region is within the substrate below the gate structure of the transistor. The back-gate region includes a pair of doped semiconductor regions with a P-N junction therebetween. Each of the pair of semiconductor materials has a length extending substantially in parallel with respect to the gate length.

Integrated circuit (IC) devices having isolation structures in metal gate cuts. An IC device may include first and second source-drain contacts in first and second transistor structures over a substrate, and a dielectric structure having first and second feet extending into the substrate, between the first and second source or drain contacts, and with a portion of the substrate between the first and second feet. The first and second feet may each have a width approximately equal to a gate length. The portion of the substrate between the first and second feet of the dielectric structure has a width approximately equal to a distance between adjacent gate electrodes. The dielectric structure may be formed in a gate cut by a self-aligned etch following a selective recess of source-drain contacts.