128 results about "Gate length" patented technology

The present application provides an all-digital multi-phase DC-DC controller. The digital DC-DC controller includes time-based analog-to-digital converters (ADCs) for converting analog voltage signals into digital-domain signals so as to benefit from gate length scaling without limited by the low voltage swing. Also, the DC-DC controller further includes a digital control circuit and a time-based modulator. The digital control circuit can control the time-based modulator in a digital domain, thereby reducing the affection caused by process, voltage and temperature (PVT) variation. Also, the time-based modulator can adjust the timing of the PWM signals and avoid the performance degradation caused by circuit mismatch. Since the digital control circuit can be fully synthesizable, it allows implementations in all kinds of digital CMOS processes with a small chip area.

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device which comprises an epitaxial structure, a first passivation layer, a second passivation layer and a gate metal structure, the first passivation layer is arranged on the epitaxial structure, the first passivation layer is provided with a through hole, and the through hole penetrates from the upper surface of the first passivation layer to the lower surface of the first passivation layer; the side wall, at the through hole, of the first passivation layer is a bent side wall, the second passivation layer is located in the through hole and covers the bent side wall of the first passivation layer, and the gate metal structure is connected with the epitaxial structure through the through hole. By means of the arrangement, the formed semiconductor device has smaller gate length, and the stability of the semiconductor device is improved.

Device structures and fabrication methods for MOSFETs having a novel multiple-conductive layer “T”-shaped gate (as viewed in cross-section). The novel “T-gate” significantly decreases the gate resistance RG of a MOSFET device and thus increases the figure-of-merit fMAX (the maximum device oscillation frequency, or the frequency at which the maximum power gain equals unity) and reduces the noise factor (NF) of the device. Fabrication of the novel MOSFET devices may be readily integrated into existing IC fabrication processes, and such MOSFETs may have gate lengths Lg scaled below the lithographic capabilities of the fabrication process. Some embodiments include conformal gate side-spacers. Some embodiments include non-conformal air-gapped gate side-spacers that result in reduced parasitic gate-to-source capacitance CGS and gate-to-drain capacitance CGD, with concomitant improved performance at high radio frequencies (RF). Embodiments of the novel MOSFET device enable RF circuits, such as low-noise amplifiers (LNAs), to exhibit a better noise figure parameter, NFmin.

A semiconductor device includes a memory cell structure that includes a transistor structure and a storage structure. A gate electrode of the transistor structure extends in a direction that is approximately perpendicular to a surface of a substrate of the semiconductor device, which enables the gate length to be increased with minimal to no increase in horizontal or lateral size of the memory cell structure. A channel layer wraps around the sidewalls and the bottom surface of the gate electrode to form a cylindrical channel. This increases the channel area of the transistor structure, which enables a low current leakage to be achieved for the memory cell structure, and enables a high lateral density of memory cell structures to be achieved in the semiconductor device.

A semiconductor structure is provided. The semiconductor structure includes a substrate, a well, a plurality of channel sheets, a source / drain region, a contact, a gate electrode, a gate dielectric layer and a spacer. The gate electrode includes at least one inner gate electrode and a top gate electrode. The inner gate electrode is located between the plurality of channel sheets. The top gate electrode is located upon a top of the plurality of channel sheets. The top gate electrode includes a first stage top gate and a second stage top gate. The first stage top gate is stacked on the second stage top gate, and a first gate length of the first stage top gate is less than a second gate length of the second stage top gate. The gate dielectric layer surrounds the gate electrode. The spacer includes at least one inner spacer and a top spacer.

Semiconductor structures having an increased gate length are provided by providing a vertical stack of suspended semiconductor channel material nanosheets that include a middle portion located between a first end portion and a second end portion. The middle portion of each suspended semiconductor channel material nanosheet is vertically offset from (i.e., higher or lower than) the first end portion and the second end portion of each suspended semiconductor channel material nanosheet.

The embodiment of the invention provides a parameter space degree of freedom determination method and device, electronic equipment and a storage medium, and the scheme is as follows: according to a first working frequency and a second working frequency corresponding to a first quantum bit and a second quantum bit under the condition that the frequency detuning is 0, and a third working frequency of an adjustable coupler under a preset gate length, determining the degree of freedom of a parameter space; calculating target coupling strength; according to periodic quantum logic gate operations on the first quantum bit and the second quantum bit under different frequency detuning conditions, obtaining a first corresponding relation between frequency detuning and a leakage rate, and obtaining a second corresponding relation between frequency detuning and a preset condition phase; and based on the first corresponding relation and the second corresponding relation, obtaining first detuning and second detuning corresponding to the lowest leakage rate under the target phase as target detuning parameters. According to the technical scheme provided by the embodiment of the invention, the influence of the distortion of the residual short time scale on the magnetic flux control line on the quantum calculation process can be avoided, so that the fidelity of quantum calculation is improved.

A semiconductor device 1 comprises: a collector layer 5; a drift layer 4 stacked on the collector layer 5; a base layer 32 stacked on the drift layer 4; first gates 21 arranged side by side on the drift layer 4 in the gate length direction; and second gates 22 which are arranged side by side with some of the first gates 21 and which can be driven independently of the first gates 21. The semiconductor device is partitioned into a first region Hc and a third region Ts where the first gates 21 are disposed, and a second region Hs where the first gates 21 and the second gates 22 are disposed. The semiconductor device is disposed such that the third region Ts is disposed between the first region Hc and the second region Hs in the gate length direction. In the collector layer 5, the carrier concentration in the second region Hs and the third region Ts is lower than the carrier concentration in the first region Hc.

A semiconductor device includes a dual-stage Schottky barrier. The dual-stage Schottky barrier includes a first stage and a second stage. The first stage is formed over a substrate stack and includes an upper layer having a length corresponding to a gate length for the device. The second stage is formed at least partially over the first stage and includes a contact segment having a length less than the gate length.

The application relates to the technical field of field effect transistor devices, and discloses a two-dimensional material field effect transistor and a preparation method thereof. The two-dimensional material field effect transistor comprises a substrate insulating layer, a gate layer, a gate contact electrode, a vertical electric field shielding structure, a second insulating layer and a conductive channel film which are arranged in a stack. A second step and a third step are formed on the side of the conductive channel film away from the second insulating layer; the second step and the third step are arranged along the stacking direction. A first contact electrode is formed on the second step surface through oblique angle deposition, and a second contact electrode is formed on the third step surface through oblique angle deposition; the side surface of the first contact electrode facing the third step is aligned with the end of the second step surface facing the third step. The first contact electrode and the second contact electrode are deposited through the oblique angle deposition mode, the dependence on a photoetching device and a overlay process precision in the development process of the existing field effect transistor is reduced, and the channel length and the gate length are simultaneously micronized.

Described herein are IC devices include patterned conductive layers, such as metal gratings and gate layers, and patterned layers formed over the patterned conductive layers using a directed self-assembly (DSA)-enabled process with DSA assisting features. A patterned conductive layer may have non-uniform features, such as large regions of insulator within a metal grating, or varying gate lengths across a gate layer. The DSA assisting features enable the formation of patterned layers, e.g., layers with different hard mask materials replicating the structure of the conductive layer below, even over non-uniform features.

A semiconductor device includes a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate. A passivation layer covers the semiconductor barrier layer. A first gate electrode and a second gate electrode are laterally separated from each other and at least partially disposed in the passivation layer respectively. Along a first direction, a first gate length of the first gate electrode is less than a second gate length of the second gate electrode. A source electrode and a drain electrode are disposed on the semiconductor channel layer. The second gate electrode is electrically connected to the source electrode. The first gate electrode and the second gate electrode are electrically isolated from each other.

A semiconductor device, a semiconductor device manufacturing method, and an image capturing device capable of suppressing variations in transistor characteristics. The semiconductor device includes a semiconductor substrate, and a field effect transistor. The field effect transistor includes a semiconductor region having a channel, a gate electrode covering the semiconductor region, and a gate insulating film. The semiconductor region has a top face, and a first side face at one side of the top face in a gate width direction of the gate electrode. The gate electrode has a first part facing the top face over the gate insulating film, and a second part facing the first side face over the gate insulating film. A first end face of the first part and a second end face of the second part are flush at at least one end of the gate electrode in a gate length direction.

Provided are: a light detection apparatus that is capable of reducing leakage current; a semiconductor device; and a manufacturing method for a semiconductor device. The light detection apparatus comprises: a photoelectric conversion element; and a semiconductor device for reading out an electrical charge obtained through photoelectric conversion performed in the photoelectric conversion element. The semiconductor device comprises: a semiconductor substrate; and a field effect transistor provided on the semiconductor substrate. The field effect transistor has: a semiconductor region in which a channel is formed; a gate insulation film which covers the semiconductor region; a gate electrode which covers the semiconductor region with the gate insulation film therebetween; a side wall which covers the side surface of the gate electrode; and a spacer which is insulative and is interposed between the side surface of the gate electrode and the side wall. At least one of the spacer and the gate insulation film has a film thickness which is different on one side compared to the other side in the gate length direction of the gate electrode.

An HEMT device includes a semiconductor epitaxial layer, a source electrode, a drain electrode, a gate electrode, a field plate structure, a first passivation layer, and a second passivation layer. The gate electrode includes a gate foot and a gate cap. The field plate structure includes a first portion, a second portion, a third portion, an extension portion. The second passivation layer has a first groove. The first groove has a first sidewall and a second sidewall. The first sidewall forms a first inclining angle with an imaginary line parallel to a gate length direction. The second sidewall and the imaginary line form a second inclining angle. Both of the first inclining angle and the second inclining angle are formed outside the first groove, and the first inclining angle is greater than the second inclining angle. A method for manufacturing the HEMT device is also provided.

The utility model provides a double-gate oxide MOS (Metal Oxide Semiconductor) structure, which comprises a substrate, a high-voltage well region and a low-voltage well region, the low-voltage well region comprises a thin gate oxide layer and a low-voltage side gate which are located on the surface of the low-voltage well region, and low-voltage side source / drain regions which are located in the low-voltage well region and located on the two sides of the low-voltage side gate, and the high-voltage well region comprises a high-voltage side gate oxide layer and a high-voltage side gate which are located on the surface, a drift region located in the high-voltage well region, and high-voltage side source / drain regions located on the two sides of the high-voltage side gate oxide layer; the high-voltage side gate oxide layer comprises a thick gate oxide layer and a first field oxide layer which are arranged in an overlapped mode in the gate length direction and only covers the high-voltage side gate instead of covering the whole high-voltage well region, so that a thick film layer exists in a region corresponding to the high-voltage side gate in the follow-up manufacturing process of the polycrystalline silicon gate, and when the polycrystalline silicon layer is etched to form the two gates, the high-voltage side gate oxide layer is formed. The residual film difference of other regions is small, so that LDD injection and the injection dose and depth of the source / drain region can be accurately controlled, and the electrical performance and reliability of the double-gate oxide MOS structure are further improved.

The utility model discloses a composite dielectric gate photosensitive detection unit and a detector, each unit comprises a composite dielectric gate photosensitive capacitor and a composite dielectric gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and the composite dielectric gate photosensitive capacitor and the composite dielectric gate MOSFET are formed above the same P-type semiconductor substrate. An active region of a P-type semiconductor substrate of the composite dielectric gate MOSFET adopts an L-shaped or U-shaped structure, the direction of an electric field between a source and a drain is arc-shaped, electron accelerated motion is restrained, channel hot electron injection is not easy to occur in electric field distribution, and the structure of the L-shaped or U-shaped active region enables the composite dielectric gate photosensitive detector to work at a higher drain terminal voltage, so that the reliability of the composite dielectric gate photosensitive detector is improved. And the working current of the photosensitive detector is larger under the same gate voltage, so that the readout noise of the photosensitive detector is further reduced. The P-type semiconductor substrate active region of the composite dielectric gate MOSFET adopts an annular structure, so that the layout in two dimensions of a two-dimensional plane is realized, the equivalent gate length of the composite dielectric gate MOSFET is increased, the channel area of a transistor is increased, and the random telegraph noise is reduced.

A gate electrode (107) comprises: a leg part (107a); a first head part (107b); a second head part (107c); a first lateral part (107d); and a second lateral part (107e). The first head part (107b) is continuously formed above the leg part (107a), and is longer in length than the leg part (107a) in the gate length direction. The first lateral part (107d) and the second lateral part (107e) are continuously formed at both ends in the gate length direction of the first head part (107b). The second head part (107c) is continuously formed above at least one of the first lateral part (107d) and the second lateral part (107e), and is longer in length than the leg part (107a) in the gate length direction. In this example, the second head part (107c) is continuously formed above both the first lateral part (107d) and the second lateral part (107e).

A field effect transistor (FET) transconductance device with varying gate lengths is disclosed. In one aspect, the varying effective gate lengths are used in a differential architecture to obtain linear even and odd order operation simultaneously. In a particular aspect, the effective gate lengths may be varied according to a differential Multi-Tanh-like architecture. This variation of effective gate lengths enables a compact implementation particularly as compared to varying gate width or emitter areas while also providing linear even and odd order operation simultaneously.

Structures, and methods for making such structures, for metal-oxide-semiconductor field-effect transistors (MOSFETs) that have gate structures having multiple work function regions. More specifically, within each MOSFET made in accordance with the present invention, the gate material above a gate oxide is differentially doped in vertically-striped regions so as to exhibit different work functions per region, resulting in a substantial improvement (over 20% in some embodiments) in the drain-to-source breakdown voltage VBD of the device. The higher VBD means that fewer multiple work function MOSFETs are needed in a series stack to withstand a specified voltage compared to a stack of conventional MOSFETs, allowing a reduction in IC size. Alternatively, a single multiple work function MOSFET may be designed with a shorter gate length LG to withstand the same voltage as a single conventional MOSFET, but should exhibit a lower RON due to the shorter gate length LG.

A semiconductor device includes an offset drain region and a p-type well. In a gate length direction of a gate electrode, a first distance between the offset drain region and a first portion of the p-type well is larger than a second distance between the offset drain region and a second portion of the p-type well. The semiconductor device includes an n-type semiconductor region formed in a portion of an epitaxial layer located between the offset drain region and a source region.

The wireless front-end can include multiple circuits such as a power amplifier (PA), a low-noise amplifier (LNA), and an RF switch. To reduce the size of the front-end and improve its performance, various circuits of the front-end can all be formed from the same epitaxial material structure and include N-polarity III-N transistors monolithically integrated on one chip. Since different performance requirements for different transistors exist among different circuits, parameters such as gate length, distance between the gate and the channel, and distance between the surface and the channel in the access region of the device can be varied to meet the required performance requirements.

A transistor structure includes a substrate and an active area defined by a trench isolation region on the substrate. The active area includes a source region, a drain region spaced apart from the source region, and a channel region between the source region and the drain region. A gate is disposed on the channel region. The gate has a gate length that is in parallel with a source-to-drain direction and a gate width that is smaller than a width of the active area.

A Super Short Channel NOR-type (SSC NOR) flash array is disclosed. Upon the new Channel Induced Ternary Electron programming scheme for resolving the punch-through issue caused by the gate short channel of NVM cell devices, the gate length of NVM cell devices can be further shrunk below 100 nm for NOR flash array. The cell device of SSC NOR flash can be then scaled down to achieve the minimum cell sizes between 4F2 to 5F2, where F is the minimum feature size of a process technology node below 100 nm. In comparison with conventional NOR flash, the SSC NOR flash improves memory density resulting in cost reduction per bit storage. While on the benefit of increasing memory density and storage cost reduction, the invention preserves the typical NOR-type flash advantages over NAND flash on fast nanosecond-range access time, low operating voltages, and high reliability.

A method for manufacturing a semiconductor-on-insulator (SeOI) chip comprises: a) providing a SeOI structure, b) building a plurality of isolated field effect transistors (FET) each comprising: —a preliminary gate above a channel region, the FETs from a first group having a first preliminary gate length and the FETs from a second group having a smaller second preliminary gate length, —a source region and a drain region, and —a source electrode and a drain electrode, c) removing at least the preliminary gates of the FETs from the second group, leaving access to channel regions of the FETs, d) thinning a top layer in channel regions of the FETs from the second group, the top layer in channel regions of the first group of FETs having a different thickness, and e) forming functional gates simultaneously on channel regions of the FETs whose preliminary gates were removed.

Disclosed is a structure including a field effect transistor (FET). The FET includes, on an insulator layer above a substrate, source / drain regions and a section of a semiconductor layer extending laterally between the source / drain regions. A primary gate structure is made of the insulator layer and a well region in the substrate opposite at least the section of the semiconductor layer extending laterally between the source / drain regions. One or two secondary gate structures are on the semiconductor layer between and near one or both of the source / drain regions, respectively. The FET can further include a patterned conformal dielectric layer, which is on the center of the semiconductor layer between the source / drain regions, and which extends onto the secondary gate structure(s). Also disclosed are methods of operating the structure by biasing the secondary gate structure(s) to adjust the effective gate length of the FET and methods of forming the structure.

The present invention provides a reference voltage generation device which includes a constant current circuit outputting a constant current in response to an input voltage; a voltage generation circuit connected in series to the constant current circuit, using the constant current as an input current, and generating an output voltage based on the input current; and a reference voltage output port outputting the output voltage. In the constant current circuit, multiple depletion type MOS transistors are connected in series, the gate widths are the same, and the sum of the gate lengths is the total gate length of the constant current circuit. In the voltage generation circuit, multiple enhancement type MOS transistors are connected in series, the gate widths are the same, and the sum of the gate lengths is the total gate length of the voltage generation circuit.

Circuits and methods for integrated circuits particularly useful in high-quality low-noise amplifiers (LNA) that are sensitive, provide good amplification, are physically compact, and can withstand relatively high drain-to-source voltages. LNA embodiments include an N-type MOSFET (NFET) or P-type MOSFET (PFET) device co-fabricated with one or more serially-coupled asymmetric PFET devices of several types. The asymmetry of the novel asymmetric PFET device provides a shorter gate length (LG) and thus a higher transconductance (gm). In addition, the inventive asymmetric PFET device has a higher hole mobility brought about by introducing strain in the conduction channel (especially at or near the source of the device) and / or by use of silicon germanium (SiGe) regions within the asymmetric PFET structure. The resulting asymmetric PFET devices have higher Vtsat and lower built-in voltage Vbi (thus higher IDS) characteristics than conventional symmetric PFET devices.

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a fin-shaped active region over a substrate and comprising a number of channel layers interleaved by a number of sacrificial layers, removing a source / drain region of the fin-shaped active region to form a source / drain opening, forming a source / drain feature in the source / drain opening, selectively removing the number of sacrificial layers to form a number of gate openings, and forming a gate structure in the number of gate openings, where the gate structure includes a first portion formed in a first gate opening of the number of gate openings and a second portion formed in a second gate opening of the number of gate openings, a gate length of the first portion is different from a gate length of the second portion.

A semiconductor device includes a memory cell structure that includes a transistor structure and a storage structure. A gate electrode of the transistor structure extends in a direction that is approximately perpendicular to a surface of a substrate of the semiconductor device, which enables the gate length to be increased with minimal to no increase in horizontal or lateral size of the memory cell structure. A channel layer may be a U-shaped layer in that the channel layer is included on at least two of the sidewalls and on the bottom surface of the gate electrode. This increases the channel area of the transistor structure, which enables a low current leakage to be achieved for the memory cell structure, and enables a high lateral density of memory cell structures to be achieved in the semiconductor device.