179 results about "Mask ROM" patented technology

There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and a second set of partially or totally disabled TFTs.

To improve reliability of FETs having element isolation regions for electrically isolating field effect transistors adjacent to each other in the gate length direction in a mask ROM region, the isolation regions are each constructed by field plate isolation formed simultaneously with gate electrodes of the field effect transistors. This relatively lessens a stress generated in an active region ACT sandwiched by the element isolation regions even if the isolation width of each element isolation region is made relatively small, specifically, less than 0.3 μm. It is therefore possible to relax or prevent the generation of crystal defects resulting from the stress, thereby reducing occurrence of an undesired leak current between the source and drain of each field effect transistor.

After a mask is carried into a reserve room for temporarily storing before carrying into a mask room filled with specific gas that has an impurity concentration lower than a first concentration (e.g. 1 ppb) and that has a characteristic of absorbing little exposure light, gas-replacement mechanisms replace gas in the reserve room with specific gas having an oxygen concentration not lower than the first concentration. Therefore, when subsequently carrying the mask into the mask room, impurities from the outside (including absorbent gas) can be substantially prevented from getting into the optical path inside the mask room. When replacing a wafer, gas in a reserve room is also replaced in the same way as the above.

A method for fabricating a type of Trench Mask ROM cell comprises steps including: providing a substrate doped lightly with p-type dopant, sequentially forming a pad oxide layer and a nitride layer on the substrate; etching back the pad oxide layer, the nitride layer and the substrate to form plural trenches; a gate oxide layer being formed on surfaces of each trench; then, implanting n+-type ions into the substrate beneath the pad oxide layer and between each two adjacent trenches; and, forming a polysilicon layer on the gate oxide and pad oxide; finally, implanting n+-type ions into the substrate beneath the gate oxide layer on bottoms of selected trenches. And, it is appreciated that the sequence of the formation of plural trenches and implanting n+-type ions into substrate between each trench can be reversed in the embodiment without affecting subsequent steps.

For improving performance of mask ROM, bit line is multi-divided for reducing capacitance, so that multi-stage sense amps are used for reading, wherein a local sense amp receives an output from a memory cell through the bit line, and a global sense amp receives the local sense amp output. By the sense amps, a voltage difference in the bit line is converted to a time difference for differentiating data “1” and data “0”. For example, data “1” is quickly transferred to an output latch circuit through the sense amps with high gain, but data “0” is rejected by a locking signal based on data “1” as a reference signal. Furthermore, a buffered data path is used for transferring data wherein the buffered data path includes a forwarding write line and a returning read line. Additionally, alternative circuits and memory cell structures for implementing the mask ROM are described.

A mask ROM stores information by selecting the work function of the gates of each FET in an array of FETs at a late stage in the manufacture of the ROM. The polysilicon gates of some of the FETs are doped N-type and the gates of the other FETs are doped P-type to form gates having different work functions, thereby forming FETs having different threshold voltages. The ROM consists of a parallel array of buried N+ bit lines formed in the substrate, a gate oxide layer deposited over the bit lines and a layer of polysilicon deposited on the gate oxide. The polysilicon is blanket doped N-type, gate electrodes are defined by photolithography, and then self-aligned silicide layers are formed on the gate electrodes. An insulating layer is then formed over the gate electrodes. Programming of the ROM is accomplished by forming a mask on the insulating layer and then implanting ions through openings in the mask, through the insulating layer and the silicide layer, and into the polysilicon layer. The implantation converts individual gate electrodes from N-type to P-type to alter the threshold voltage of the selected transistors. Relatively few additional processing steps are needed after the programming to complete the ROM.

In an RF tag, a mask ROM or a flash memory is used for storing data such as an ID number. Although the mask ROM can be realized at a low price, rewriting is not possible. In addition, in the flash memory, although electric rewriting is possible, production cost increases. Accordingly, it is difficult to provide an RF tag by which data rewriting is possible at a low price. An RF tag is provided with a power supply circuit having a function to generate a power supply voltage from a weak radio signal and a memory which can hold data stored in a data holding portion by the power supply voltage. With the above structure, a high-performance RF tag capable of rewriting data such as an ID number after production can be provided at a low price.

A portable device capable for providing navigation data and the method thereof. The portable device includes a mask ROM (Read Only Memory), an input unit, a RAM (Random Access Memory), a GPS (Global Positioning System) unit, a CPU (Central Processing Unit), and an output unit. First, an updated navigation map data is provided into the input unit of the portable device and stored in the RAM. Then, the CPU compares the updated navigation map data with an original navigation map data stored in the mask ROM to generate a revised navigation map data. Afterwards, the CPU calculates the position of the user on the revised navigation map data according to a positioning coordinate from the GPS unit.

A navigation device, programmable with map data and a navigation application that enables a route to be planned between two user-defined places; the device is operable to read a removable memory card storing the device operating system, the navigation application, and the map data. It does not need to store the operating system in mask ROM; hence, customisation for a specific country requires only that the appropriate memory card be inserted at the time of use.

There is provided a high-density mask ROM operable at a high speed. With the mask ROM, respective source lines are disposed so as to be shared by memory cells in respective columns adjacent to each other, and bit lines are disposed so as to correspond to the respective columns of the memory cells. Further, the dummy cells are disposed for the respective columns of the memory cells. The dummy cells are each made up of a series-circuit including a first switching transistor that is turned into the conducting state in response to a signal potential on a dummy word line (DWL), and a second switching transistor 17 for coupling an adjacent source line to the bit line corresponding thereto in response to a potential of the source line in a column corresponding thereto. The memory cells each are made up of one unit of a transistor and a data storage formed by mask wiring. At the time of reading data, a potential of the source line in a select column is caused to undergo a change, whereupon there occurs a potential difference between a pair made up of the bit line as selected to which the memory cells as selected are coupled, and a reference bit line with the dummy cells coupled thereto, so that it is possible to execute readout of data by detecting the potential difference.

A method for fabricating a mask read-only-memory with diode cells is provided. A doped conductive layer with a first conductivity is formed on bit lines. Then, a photoresist layer with a mask ROM pattern is formed on an interlayer dielectric layer on the doped conductive layer for serving as an etching mask, thereby forming openings in the interlayer dielectric layer unto the exposed regions of the doped conductive layer. Performing ion implantation to form a diffusion region with a second conductivity opposite to the first conductivity in each exposed region of the doped conductive layer, so that the doped conductive layer and the diffusion regions formed therein constitute diode cells that are served as memory cells. A contact plug is formed in each opening unto the diode cell and a conductive layer is formed on the contact plug for serving as word lines.

A method of fabricating a mask ROM includes forming a trench on a first conductivity type semiconductor substrate, implanting a second conductivity type impurity ion in at least a surface portion of the semiconductor substrate where the trench is formed, forming an insulating oxide layer on a surface of the semiconductor substrate, including a surface of the trench, forming gate oxide layers of both sides of the trench, forming first and second gates on the gate oxide layers and forming a first conductivity type channel by implanting a first conductivity type impurity ion in one side of the trench. As such, the resulting mask ROM includes two transistors on either side of a trench having channels along the side walls of the trench. The resulting mask ROM has a reduced surface width, enhancing integration.

A semiconductor memory device included in a system-on-chip (SOC) or a microcomputer chip. The semiconductor memory device may include a flash memory cell array unit and a mask read-only memory (ROM) cell array unit which are formed in a single memory block without an isolation layer for separating the two units. Transistors included in the flash memory unit and the mask ROM unit are the same type and may have two threshold voltages. The transistor in each memory cell unit may be a split gate transistor, a metal-oxide-nitride-oxide-silicon, or silicon-oxide-nitride-oxide-silicon transistor. Further, the transistor included in the mask ROM unit in the semiconductor memory device may include enhancement transistors or depletion transistors in which a dopant ion-implanted region is formed at channel portions.

In a state of a first semiconductor integrated circuit device on which a first semiconductor integrated circuit board including a first mask ROM and a programmable ROM are mounted, an ultimate program determined by using the programmable ROM is stored in a second ROM of a second semiconductor integrated circuit board which is substantially similar in structure to the first semiconductor integrated circuit board, thereby manufacturing a second semiconductor integrated circuit device as an ultimate product.

Semiconductor memory devices 10 are each furnished with a memory array 100 having an EEPROM array 101 and a mask ROM array 102. Identifying information for identifying each semiconductor memory device 10 is stored at the beginning three addresses of the EEPROM array 101. 8-bit data relating to ink level is stored at the ninth address to sixteenth address of the EEPROM array 101. The seventeenth address to the twenty-fourth address of the EEPROM array 101 is provided with a usage history information storage area for storing 8-bit usage history information that is rewriteable under certain conditions.

A mask read only memory (ROM) device includes a plurality of isolation patterns disposed at predetermined regions of a semiconductor substrate to define a plurality of active regions. The semiconductor substrate includes a mask ROM region where a plurality of on cells and a plurality of off-cells are disposed. The mask ROM further includes a plurality of gate lines disposed over the active regions, and which cross over the isolation patterns, a plurality of gate insulating layers interposed between the gate lines and the active regions and a floating conductive pattern and a inter-gate dielectric pattern located between the gate line and the gate insulating layer of the off-cell.