1587 results about "Controller (computing)" patented technology

Job clusters take time to instantiate. A computing system is provided comprising a plurality of non-interactive job clusters, a control database storing a task queue, and a controller. The controller instantiates one or more clusters of the plurality of non-interactive job clusters based on a size of the task queue and monitoring if the one or more clusters are successfully instantiated. Each of the one or more clusters, after successfully being instantiated by the controller, executes a dispatcher process that includes: querying the control database to identify an available task from the task queue; obtaining and processing the available task; and, after completion of the available task, further querying the control database prior to terminating.

The invention provides a complex scene-oriented AI large model lightweight deployment method, and relates to the technical field of edge computing, and the method comprises the steps: carrying out the structured pruning of a pre-trained Transform network based on the attention head importance score, carrying out the dynamic sparsification of the activation state of a feedforward network according to the input tensor entropy value, employing the dynamic mixing precision quantization, and carrying out the reconstruction of an AI large model. Obtaining network parameters after pruning quantization; deploying the pruned and quantized network parameters to an edge computing device, distributing a feature extraction operator to a neural network processor through a heterogeneous computing scheduler, and unloading a classification operator to a multi-core central processing unit; and managing an on-chip memory in combination with a virtual memory paging mechanism, realizing zero-copy data transmission by utilizing a direct memory access controller, and outputting a reasoning result tensor. According to the method, efficient and reliable operation of the large model at the resource-constrained edge node is realized.

An exemplary system and method that generate a finite state automaton of a controller for sequential decision-making of a computing device for a user-requested task, the generation using automaton-based representations derived from outputs of a large-scale generative language model. The exemplary system and method receive a user command and (i) construct the finite state automaton by parsing GLM responses to prompts / queries for candidate steps and sub-steps for the task, and (ii) verify the finite state automaton, e.g., for logical errors, safety specification, performance specification, and intent of the user, and / or update the finite state automaton to meet such specifications. The state machine can be synthesized on the fly for real-time operation via the GLM outputs and evaluated in the same pipeline operation against physical models, safety models, etc., that can be combined to iteratively modify the state machine until it meets the verification requirements.

A tree-of-thought (ToT) system is presented that improves problem-solving capabilities of machine learning models, such as auto-regressive large language models (LLMs). The TOT system can solve complex reasoning tasks through trial and error. In this process, the system explores the solution space through a tree-like thought process, allowing for backtracking when necessary. The system augments an LLM with additional modules including a prompter agent, a checker module, a memory module, and a ToT controller. These modules engage in a multi-round conversation with the LLM. The memory module records the conversation and state history of the problem-solving process, which allows the system to backtrack to the previous steps of the thought-process and explore other solution paths. This new system can be applied to a blockchain and / or a distributed computing system.

The invention relates to the technical field of large models, in particular to a large-model-oriented reasoning service system and an inter-stage resource adjustment method, and the system comprises a pre-filling processor and a decoding processor; a computing resource controller implementing computing resource control of the prefill processor and the decode processor based on a multi-process service, the multi-process service allowing a target number of streaming multiprocessors to be designated to a prefill process representing an entity of the prefill processor and a decode process representing an entity of the decode processor; and the unified storage manager is used for managing the storage utilization rate of the system and the storage access of the pre-filling processor and the decoding processor to the large model weight and the KV cache. Therefore, the problems of delay interference, low storage efficiency and the like between pre-filling and decoding in related technologies are solved.

Embodiments pertain to reducing power consumption in a computing system comprising one or more deterministic processors. A controller generates a plurality of control signals for a voltage regulator to regulate a supply voltage of a respective one of the one or more deterministic processors. A power management module determines an initial profile for power consumption and performance of an algorithm executed on the respective deterministic processor having an initial value for the supply voltage and an initial value for a clock frequency. The power management module further determines a target profile for power consumption and performance of the algorithm executed on the respective deterministic processor. The controller modifies the plurality of control signals based on the initial profile and the target profile. The respective deterministic processor executes the algorithm while the supply voltage is dynamically modified by the voltage regulator based on the modified plurality of control signals.

The invention discloses a multi-dimensional computing power dynamic perception routing decision-making method and system based on SRv6 driving. The method comprises the following steps: firstly, screening an optimal target computing power node based on a service demand and a node real-time load; and then, based on the dynamic network topological graph fusing the service sensitivity, calculating an optimal network path reaching the computing power node by using an improved SPFA algorithm, and realizing a global collaborative decision of selecting the most suitable computing point and searching the most efficient connection path. Meanwhile, based on an SRv6 driving service chain dynamic generation and closed loop execution method, a target computing power node and necessary network functions are abstracted into a programmable SID, an SID sequence (service chain) is dynamically constructed according to a double-stage decision result and is packaged in an SRH head, second-level path issuing and state monitoring are achieved through a programmable controller, and a real-time monitoring result is obtained. According to the method, the problems of poor real-time performance, single dimension, weak cooperative capability and the like in the prior art are solved, and efficient, stable and intelligent development of a future-oriented distributed intelligent computing network system can be promoted.

The invention discloses a computing node, a computing system, a control method, a control device, equipment and a medium, and relates to the technical field of computers, a plurality of acceleration cards are interconnected through an Ethernet switching module, and low-order channels of serializer / deserializer interfaces of the acceleration cards are connected with the Ethernet switching module through retimers. A high-order channel of at least one serializer / deserializer interface of each accelerator card is connected with the Ethernet switching module through a retimer, and the working mode of the retimer is configured through a first controller on a computing node according to the signal rate of the accelerator cards, so that a framework that communication interfaces between the accelerator cards are fully interconnected is realized. Any two acceleration cards can be directly connected, the communication bandwidth between the acceleration cards is improved, meanwhile, the number of the acceleration cards can be flexibly expanded, longitudinal expansion and transverse expansion of a computing system can be conveniently achieved, the problem that a traditional acceleration card interconnection scheme is not easy to expand is solved, and the method can adapt to service requirements and flexibly adjust working loads.

The invention provides a priority-based preemptive scheduling method and system in a computing power network. The method comprises the following steps: initializing a computing power network controller and parameters; and in the scheduling time slot, receiving a plurality of tasks, obtaining network and node information, generating a scheduling strategy by using a deep reinforcement learning algorithm, and issuing the scheduling strategy to each node. And the task is forwarded to a destination node through a default path and enters a cache queue to wait for calculation. And calculating the priority score of each global task, and sorting the tasks in the cache queue. The tasks with high priorities can preempt the tasks in the processing area or the suspended area, and whether preemption operation is carried out or not is determined according to the remaining execution time of the preempted tasks. And calculating a reward value according to the node resource occupation, the expected time delay and the task success rate, and updating controller parameters. And performing multiple rounds of scheduling training on the controller to maximize the reward value, forming an optimal scheduling strategy, and completing controller training. According to the method, the tasks scheduled to the nodes are subjected to priority ranking, load balancing can be achieved, and the task success rate is increased.

The invention relates to the field of energy-saving computing, and discloses a low-power-consumption control method and system of a controller, which are used for realizing prediction-sleep-wake-up-response full-link hardware in the controller. Time sequence state data of a controlled object is collected in real time, and a predictive sleep window value is dynamically generated by utilizing a predictive cooperative computing unit, so that intelligent scheduling of sleep and awakening is realized, and the power consumption of a controller is effectively reduced. Meanwhile, in combination with the technologies of threshold comparison, DMA data transmission optimization and the like, the data processing efficiency is improved, and invalid data transmission is reduced. And on the awakening mechanism, an asynchronous awakening circuit and an interrupt request mechanism are adopted to ensure that power supply is quickly recovered and control response is executed when an effective instruction is received, so that the real-time performance of the system is guaranteed. According to the invention, a prediction algorithm, hardware acceleration and an intelligent scheduling technology are fused, the performance of the controller is ensured, the power consumption is obviously reduced, and the endurance time of equipment is prolonged.

The invention discloses a large model calculation acceleration chip architecture, and relates to the field of large models. Comprising a normalized network-on-chip, an interconnection transmission system, a storage control system and a calculation acceleration core, the storage control system is connected with the Memory video memory group and the external SSD memory based on different built-in storage controllers; the normalized network-on-chip reads on-chip model parameters of a target position based on the storage control system, sends the on-chip model parameters to the calculation acceleration core for calculation, restores on-chip model data, carries out off-chip interaction with an external management server based on the interconnection transmission system, receives an instruction task, reads and restores external model parameters, and sends the external model parameters to the calculation acceleration core for calculation. And performing inter-chip interaction with other computing acceleration chips based on an interconnection transmission system, and reading and restoring inter-chip model parameters. According to the scheme, the hybrid video memory computing chip architecture supports multi-parallel SSD direct connection access, the capacity is expanded at low cost under the condition of keeping the bandwidth, and high cost performance is kept for both large-scale parallel tasks and small-sized low-cost all-in-one machines.

Systems and methods are disclosed that relate to applications and platforms for performing in-system testing for autonomous or semi-autonomous systems and applications. In some embodiments, resources of a computing system may be grouped into one or more subsets of system elements (e.g., “a chiplet”) and may be configured to be controlled via an associated local controller, which may enable and / or disable the chiplet as targeted. In embodiments, the local controllers may receive instructions from a central controller and, via the enabling and / or disabling of the chiplets, may maintain a number of resources consumed during system testing within a threshold. As a result, the system may be configured to perform system testing without additional resources and / or without redirecting resources that may be intended for other operations.

An example network system includes processing circuitry and one or more memories coupled to the processing circuitry. The one or more memories are configured to store instructions which, when executed by the processing circuitry, cause the network system to receive connection data related to an egress connection of an application service of an application. The instructions cause the network system to analyze the connection data to determine that the egress connection is an anomalous connection. The instructions cause the network system to generate a notification indicative of the egress connection being an anomalous connection and send the notification to a computing device.

Systems and methods for managing a computing task are provided. The system includes a controller configured to receive the computing task, present to a client a set of factors defining desired conditions related to executing the computing task, receive a demand computing strategy associated with the computing task indicating one or more factors selected by the client and a constraint and a weight related to each factor from the one or more selected factors, receive a plurality of supply computing strategies from a plurality of datacenters, each supply computing strategy corresponding to a datacenter from the plurality of datacenters, calculate a task scheduling strategy based at least on the demand computing strategy and a supply computing strategy, select a candidate datacenter from the plurality of datacenters according to a predetermined rule, and schedule the computing task for execution on the candidate datacenter according to the task scheduling strategy.

The invention discloses a memory data migration method and electronic equipment, and relates to the technical field of computers, and the method comprises the steps: determining the access heat of a storage device accepting the access of a computing node based on a memory access task executed by a switching controller and an address mapping table, so as to determine a source device and a candidate data unit, according to the access parameter of the candidate data unit and the state parameter of the storage device, calculating a performance score after the candidate data unit is stored in the storage device so as to determine the data unit to be migrated and the target device, so that cold and hot data identification from the perspective of a computer fast interconnection memory heterogeneous system is realized; the rationality of data migration is improved on the basis of quantitative performance scores; according to the method, the to-be-migrated data unit is controlled to be migrated from the source device to the target device, and the address mapping table is updated, so that the data migration task is prevented from influencing the host work of the computing node, and a cold and hot data migration scheme without being perceived by the host in the computer fast interconnection memory heterogeneous system is realized.

The invention provides a DCU-based high-performance sparse stiffness matrix vector multiplication method, which comprises the following steps of: according to a sparse stiffness matrix, dividing a non-zero element into a plurality of calculation unit blocks by rows, pre-loading non-zero element data to an L1 shared memory or a register file through an on-chip shared memory controller of the DCU, a high-bandwidth crossbar switch of the DCU is used for realizing data copying and transmission; starting multi-row fusion execution for a short row of which the row non-zero element is lower than a DCU single-instruction multi-data width threshold value; constructing a wavefront scheduler based on a DCU asynchronous computing engine: binding an independent instruction cache region for each wavefront, and loading a multiply-add operation instruction set in advance through a prefetch instruction queue; a calculation unit state register is established, and when a wavefront scheduler ready signal is triggered, a scalar unit of the DCU is activated to execute calculation; and realizing cross-thread block reduction by adopting a DCU atomic operation accelerator. According to the method, the calculation throughput and the memory bandwidth utilization rate of large-scale structural mechanics stiffness matrix vector multiplication are effectively improved.

The present application relates to the technical field of large-scale data processing, and particularly relates to a parallel computing method and system suitable for large-scale data processing. The system comprises a task management unit, a distributed load balancing module, an elastic expansion architecture, an intelligent communication optimization module, and a resource monitoring unit, wherein the task management unit divides large-scale data into a plurality of sub-tasks by means of a task decomposer, and distributes the sub-tasks to computing nodes by means of a task scheduler and a priority distributor; the distributed load balancing module achieves global load balancing by means of a load sensing unit, a dynamic adjustment unit and a balance optimization unit; the elastic expansion architecture dynamically adjusts system resources by means of a node manager, a resource pool controller and an expansion decision-making device; the intelligent communication optimization module optimizes inter-node communication by means of a communication path planning unit, a bandwidth distribution unit and a delay compensation unit; and the resource monitoring unit monitors the system performance in real time by means of a performance collector, a state analyzer and an anomaly detector.

The invention provides a PCIe equipment fault monitoring and dynamic processing method based on intelligent prediction, and the method comprises the steps: obtaining operation parameters from a BMC (baseboard management controller), an operation system and a PCIe equipment register, carrying out the processing and time sequence feature extraction, and inputting a lightweight long short-term memory network LSTM model deployed in the BMC for fault probability prediction. And combining the prediction result and the operation parameters to calculate an equipment health score, and triggering an alarm, bandwidth degradation or hardware isolation operation according to the score. And the hardware isolation module sends a control instruction to the complex programmable logic device CPLD through the IC bus to realize non-interruption power-off isolation of the target equipment. And uploading real-time data to a cloud server through encryption communication, executing fine adjustment of the model, and returning an update weight to realize continuous optimization and version control of the model. The method can be widely applied to computing equipment such as a server, and the availability and the fault-tolerant capability of the system are improved.

The invention discloses a virtual machine computing resource dynamic allocation method and system based on a PCIe card and a storage medium, and belongs to the field of virtualization technology and hardware resource management.The method comprises the steps that the computing unit resource utilization rate of the PCIe card is monitored in real time through a hardware abstraction layer; dynamically generating a resource allocation scheme based on an improved auction algorithm, wherein the algorithm optimizes a resource quota through a time attenuation factor and a resource reuse penalty term; utilizing a programmable register remapping technology to distribute independent VF equipment for the virtual machine and establish a direct access channel; realizing interruption isolation between virtual functions through an interruption redirection controller; and during resource redistribution, atomic migration of a calculation task is completed by adopting a check point migration mechanism, and the atomic migration comprises context preloading and PCIe link layer retraining. According to the method, the problems of hardware resource distribution rigidness, insufficient isolation and migration service interruption in the prior art are solved, and fine-grained control and service lossless switching of the heterogeneous computing units are realized.

In some embodiments, the disclosure provides a method that includes executing, by a processor of a computing device, application instructions to display an access controller interface element and an access code on a screen of the computing device, the access controller interface element operatively linked to an access restricted digital resource; transmitting, by the processor, an access request over the cellular network based on an activity performed using the access controller interface element, including an access code and an identity linked to the computing device; the processor receives an access program instruction through the Internet to respond to transmission of the access request and receive the access program instruction through the application program so as to unlock access to the limited digital resource for access through the computing device; and executing, by the processor, the access program instructions to unlock the access restricted digital resources for access by the computing device.

Methods and systems are provided for improving remote computing experiences. The methods leverage modified PC or console architectures, which enable both local and remote console connections. The systems operate with multiple devices through a peer-to-peer connection. In the context of gaming, the systems are engineered to address obstacles such as low upstream rates and limited bandwidth or quality of service. An AI trained on play style is used as a substitute for a low bandwidth client. Also, methods are provided for inviting remote players, transferring control to a remote user, managing controller connections, and addressing low bandwidth situations using adaptive bitrate. The enhancement of connection, single encoding, and transmission processes contributes to a superior computing and / or gaming experience for all players, irrespective of their bandwidth or quality of service. Related networks, models, apparatuses, devices, techniques, articles, architectures, packets, manifests, tables, data storages, and graphical user interfaces are provided.

An apparatus for facilitating support of 8-bit floating point format operands in a computing architecture is disclosed. In one embodiment, the apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, where the decoded instruction is a matrix instruction that operates on an 8-bit floating point operand to cause the processor to perform a parallel dot product operation; a controller to schedule the decoded instruction and provide input data for an 8-bit floating point operand according to an 8-bit floating point data format indicated by the decoded instruction; and a pulsation dot product circuit to execute the decoded instruction using pulsation layers, each pulsation layer comprising one or more sets of interconnected multipliers, shifters and adders, each set of multipliers, shifters and adders to generate a dot product of 8-bit floating point operands.

A method for detecting an anomaly, which is performed by a computing device including one or more processors according to some embodiments of the present disclosure may include: collecting a CAN message generated in a controller area network (CAN); generating first traffic time interval data and first payload data based on the CAN message; obtaining a first latent vector generated by inputting the first traffic time interval data into a first neural network model; obtaining a second latent vector generated by inputting the first payload data into a second neural network model; generating merged data in which the first latent vector and the second latent vector are merged; and determining whether the CAN message is anomalous by inputting the merged data into a third neural network model.

The invention discloses a K8s-based cluster computing power resource isolation and scheduling method and system. The method comprises the following steps: when creating a cluster account, dividing the cluster account according to resource groups; node Selector directional scheduling is combined to realize tenant cluster resource isolation; the custom controller monitors a cluster user binding resource group event; and the user-defined controller monitors the cluster node update event to modify the resource group. According to the method, the resource group can effectively divide the resources in the current cluster, corresponding tenants are provided according to different computing power requirements, and nodes, accounts, labels and the like in the resource group are effectively managed by relying on a K8s CRD self-defined resource mechanism; the characteristic that a daemon process set ensures that a Pod runs on all nodes under a cluster is utilized, a service runs on the Pod to execute a GPU script to read the card number, and a K8s API is called to create a tag marked by the card number, so that subsequent resource group division is facilitated.

The invention discloses a server and an equipment monitoring system and method thereof, and relates to the technical field of servers, the server comprises a first controller and a second controller, the first controller in an interconnection resource module interacts with firmware of an exchange component connected with an acceleration card in the interconnection resource module, and the first controller is connected with the second controller. The method comprises the following steps: acquiring identification information of acceleration cards connected under a plurality of switching ports of a switching component by a second controller, and determining monitoring modes of all local acceleration cards in a first computing resource module where the second controller is located by the second controller according to the identification information of all acceleration cards acquired by the first controller, the local acceleration cards are respectively monitored according to the corresponding monitoring modes, so that the technical problems that the undistributed acceleration cards cannot be identified by the system and the monitoring link cannot be established are solved; the technical effects of dynamically identifying the types of the acceleration cards under different heterogeneous acceleration card resource pool configurations and adopting corresponding monitoring logic to realize out-of-band monitoring are achieved.

The invention discloses a computing system and a control method, device, equipment, medium and product thereof, and relates to the technical field of computers.A host device, a first switch and an acceleration computing device are divided, the first switch comprises a plurality of interconnected switching controllers, and uplink ports of the switching controllers are connected with the host device; the downlink port is connected with the acceleration computing device, the binding relation of the physical link layer between the mainboard and the acceleration card is removed, the port configuration and the resource allocation path of the exchange controller can be flexibly adjusted, and the acceleration computing resources can be allocated according to needs. The first board card provided with the first slot and the cable adapter plate are arranged in the acceleration computing device, so that the acceleration computing device with high-density deployment is realized. Therefore, the method solves the problem that the expansion capability of acceleration computing resources of a multi-card system reaches a bottleneck, and lays a foundation for expanding large-scale computing power by a single host and constructing a multi-host shared large-scale computing resource pool.

The invention discloses a hardware accelerator and equipment oriented to triple sparse matrix multiplication and an application method thereof.The hardware accelerator comprises a high-bandwidth memory HBM, a crossbar switch network and an on-chip processing unit which are connected in sequence, and the on-chip processing unit comprises a hierarchical cache module, a global controller and a plurality of computing chips; each calculation piece comprises an RA calculation array, a TP calculation array and a local controller, wherein the RA calculation array and the TP calculation array are respectively used for executing front-end operation T = R * A and rear-end operation C = T * P in triple sparse matrix multiplication. The method aims at solving the problem that when a traditional universal processor processes triple sparse matrix multiplication, due to irregular memory access, uneven calculation load and sharp increase of middle parts and results, huge off-chip data carrying is confronted with serious performance and energy efficiency bottlenecks, and the calculation performance and energy efficiency of triple sparse matrix multiplication are improved.

The invention provides a storage and calculation integrated calculation module based on an OAM (Operation Administration and Maintenance) form, which is used for integrating a plurality of storage and calculation integrated chips of different types and realizing communication between a CPU (Central Processing Unit) and the storage and calculation integrated chips, and is characterized in that an external interface of the calculation module is connected with an external UBB (Universal Business Business) bottom plate by adopting an interface designed by an OAM protocol; the calculation module comprises a power supply interlayer card, a controller card and a memory operator card which are sequentially connected in a stacked mode, and the power supply interlayer card is configured in the mode that a power supply interface designed through an OAM protocol is used for conducting power supply conversion, supplying power to the controller card and the memory operator card and providing a path for data signal transmission between the controller card and a CPU on an external UBB bottom plate; the controller card is configured to perform conversion among different protocols, and communication and data signal transmission between the operator card and a CPU (Central Processing Unit) on the external UBB bottom plate; the storage operator card is configured to store a data signal and provide a chip connection interface for one or more storage and calculation integrated chips; and a data signal is transmitted to the storage and calculation integrated chip connected with the chip connecting interface through the chip connecting interface.

The invention discloses a hybrid expert model training system based on layer freezing, which relates to the field of model training and comprises an external memory, a freezing controller, a resource allocation controller and a plurality of computing devices. The external memory stores a data set for training the hybrid expert model; the freezing controller performs freezing decision making according to a path selected by an expert and sends the decision to the computing device for execution; the resource allocation controller executes a lexical grouping algorithm based on a frozen layer expert selection path to calculate expert popularity, and allocates computing resources according to the expert popularity; and the computing device stores the hybrid expert model, executes model training operation, executes a layer freezing task according to a layer freezing decision, and feeds back a freezing layer expert selection path and an expert selection path to the resource allocation controller and the freezing controller respectively. According to the method, training of the hybrid expert model is performed through a layer freezing technology, so that the training cost is reduced while the model precision is kept; computing resource allocation is carried out based on a word source grouping algorithm, and equipment load balancing is achieved.