1274 results about "Controller (computing)" patented technology

Job clusters take time to instantiate. A computing system is provided comprising a plurality of non-interactive job clusters, a control database storing a task queue, and a controller. The controller instantiates one or more clusters of the plurality of non-interactive job clusters based on a size of the task queue and monitoring if the one or more clusters are successfully instantiated. Each of the one or more clusters, after successfully being instantiated by the controller, executes a dispatcher process that includes: querying the control database to identify an available task from the task queue; obtaining and processing the available task; and, after completion of the available task, further querying the control database prior to terminating.

The invention provides a complex scene-oriented AI large model lightweight deployment method, and relates to the technical field of edge computing, and the method comprises the steps: carrying out the structured pruning of a pre-trained Transform network based on the attention head importance score, carrying out the dynamic sparsification of the activation state of a feedforward network according to the input tensor entropy value, employing the dynamic mixing precision quantization, and carrying out the reconstruction of an AI large model. Obtaining network parameters after pruning quantization; deploying the pruned and quantized network parameters to an edge computing device, distributing a feature extraction operator to a neural network processor through a heterogeneous computing scheduler, and unloading a classification operator to a multi-core central processing unit; and managing an on-chip memory in combination with a virtual memory paging mechanism, realizing zero-copy data transmission by utilizing a direct memory access controller, and outputting a reasoning result tensor. According to the method, efficient and reliable operation of the large model at the resource-constrained edge node is realized.

An exemplary system and method that generate a finite state automaton of a controller for sequential decision-making of a computing device for a user-requested task, the generation using automaton-based representations derived from outputs of a large-scale generative language model. The exemplary system and method receive a user command and (i) construct the finite state automaton by parsing GLM responses to prompts / queries for candidate steps and sub-steps for the task, and (ii) verify the finite state automaton, e.g., for logical errors, safety specification, performance specification, and intent of the user, and / or update the finite state automaton to meet such specifications. The state machine can be synthesized on the fly for real-time operation via the GLM outputs and evaluated in the same pipeline operation against physical models, safety models, etc., that can be combined to iteratively modify the state machine until it meets the verification requirements.

A tree-of-thought (ToT) system is presented that improves problem-solving capabilities of machine learning models, such as auto-regressive large language models (LLMs). The TOT system can solve complex reasoning tasks through trial and error. In this process, the system explores the solution space through a tree-like thought process, allowing for backtracking when necessary. The system augments an LLM with additional modules including a prompter agent, a checker module, a memory module, and a ToT controller. These modules engage in a multi-round conversation with the LLM. The memory module records the conversation and state history of the problem-solving process, which allows the system to backtrack to the previous steps of the thought-process and explore other solution paths. This new system can be applied to a blockchain and / or a distributed computing system.

The invention discloses a multi-dimensional computing power dynamic perception routing decision-making method and system based on SRv6 driving. The method comprises the following steps: firstly, screening an optimal target computing power node based on a service demand and a node real-time load; and then, based on the dynamic network topological graph fusing the service sensitivity, calculating an optimal network path reaching the computing power node by using an improved SPFA algorithm, and realizing a global collaborative decision of selecting the most suitable computing point and searching the most efficient connection path. Meanwhile, based on an SRv6 driving service chain dynamic generation and closed loop execution method, a target computing power node and necessary network functions are abstracted into a programmable SID, an SID sequence (service chain) is dynamically constructed according to a double-stage decision result and is packaged in an SRH head, second-level path issuing and state monitoring are achieved through a programmable controller, and a real-time monitoring result is obtained. According to the method, the problems of poor real-time performance, single dimension, weak cooperative capability and the like in the prior art are solved, and efficient, stable and intelligent development of a future-oriented distributed intelligent computing network system can be promoted.

The invention discloses a computing node, a computing system, a control method, a control device, equipment and a medium, and relates to the technical field of computers, a plurality of acceleration cards are interconnected through an Ethernet switching module, and low-order channels of serializer / deserializer interfaces of the acceleration cards are connected with the Ethernet switching module through retimers. A high-order channel of at least one serializer / deserializer interface of each accelerator card is connected with the Ethernet switching module through a retimer, and the working mode of the retimer is configured through a first controller on a computing node according to the signal rate of the accelerator cards, so that a framework that communication interfaces between the accelerator cards are fully interconnected is realized. Any two acceleration cards can be directly connected, the communication bandwidth between the acceleration cards is improved, meanwhile, the number of the acceleration cards can be flexibly expanded, longitudinal expansion and transverse expansion of a computing system can be conveniently achieved, the problem that a traditional acceleration card interconnection scheme is not easy to expand is solved, and the method can adapt to service requirements and flexibly adjust working loads.

The invention relates to the field of energy-saving computing, and discloses a low-power-consumption control method and system of a controller, which are used for realizing prediction-sleep-wake-up-response full-link hardware in the controller. Time sequence state data of a controlled object is collected in real time, and a predictive sleep window value is dynamically generated by utilizing a predictive cooperative computing unit, so that intelligent scheduling of sleep and awakening is realized, and the power consumption of a controller is effectively reduced. Meanwhile, in combination with the technologies of threshold comparison, DMA data transmission optimization and the like, the data processing efficiency is improved, and invalid data transmission is reduced. And on the awakening mechanism, an asynchronous awakening circuit and an interrupt request mechanism are adopted to ensure that power supply is quickly recovered and control response is executed when an effective instruction is received, so that the real-time performance of the system is guaranteed. According to the invention, a prediction algorithm, hardware acceleration and an intelligent scheduling technology are fused, the performance of the controller is ensured, the power consumption is obviously reduced, and the endurance time of equipment is prolonged.

The invention discloses a large model calculation acceleration chip architecture, and relates to the field of large models. Comprising a normalized network-on-chip, an interconnection transmission system, a storage control system and a calculation acceleration core, the storage control system is connected with the Memory video memory group and the external SSD memory based on different built-in storage controllers; the normalized network-on-chip reads on-chip model parameters of a target position based on the storage control system, sends the on-chip model parameters to the calculation acceleration core for calculation, restores on-chip model data, carries out off-chip interaction with an external management server based on the interconnection transmission system, receives an instruction task, reads and restores external model parameters, and sends the external model parameters to the calculation acceleration core for calculation. And performing inter-chip interaction with other computing acceleration chips based on an interconnection transmission system, and reading and restoring inter-chip model parameters. According to the scheme, the hybrid video memory computing chip architecture supports multi-parallel SSD direct connection access, the capacity is expanded at low cost under the condition of keeping the bandwidth, and high cost performance is kept for both large-scale parallel tasks and small-sized low-cost all-in-one machines.

An example network system includes processing circuitry and one or more memories coupled to the processing circuitry. The one or more memories are configured to store instructions which, when executed by the processing circuitry, cause the network system to receive connection data related to an egress connection of an application service of an application. The instructions cause the network system to analyze the connection data to determine that the egress connection is an anomalous connection. The instructions cause the network system to generate a notification indicative of the egress connection being an anomalous connection and send the notification to a computing device.

Systems and methods for managing a computing task are provided. The system includes a controller configured to receive the computing task, present to a client a set of factors defining desired conditions related to executing the computing task, receive a demand computing strategy associated with the computing task indicating one or more factors selected by the client and a constraint and a weight related to each factor from the one or more selected factors, receive a plurality of supply computing strategies from a plurality of datacenters, each supply computing strategy corresponding to a datacenter from the plurality of datacenters, calculate a task scheduling strategy based at least on the demand computing strategy and a supply computing strategy, select a candidate datacenter from the plurality of datacenters according to a predetermined rule, and schedule the computing task for execution on the candidate datacenter according to the task scheduling strategy.

The invention discloses a memory data migration method and electronic equipment, and relates to the technical field of computers, and the method comprises the steps: determining the access heat of a storage device accepting the access of a computing node based on a memory access task executed by a switching controller and an address mapping table, so as to determine a source device and a candidate data unit, according to the access parameter of the candidate data unit and the state parameter of the storage device, calculating a performance score after the candidate data unit is stored in the storage device so as to determine the data unit to be migrated and the target device, so that cold and hot data identification from the perspective of a computer fast interconnection memory heterogeneous system is realized; the rationality of data migration is improved on the basis of quantitative performance scores; according to the method, the to-be-migrated data unit is controlled to be migrated from the source device to the target device, and the address mapping table is updated, so that the data migration task is prevented from influencing the host work of the computing node, and a cold and hot data migration scheme without being perceived by the host in the computer fast interconnection memory heterogeneous system is realized.

The invention provides a DCU-based high-performance sparse stiffness matrix vector multiplication method, which comprises the following steps of: according to a sparse stiffness matrix, dividing a non-zero element into a plurality of calculation unit blocks by rows, pre-loading non-zero element data to an L1 shared memory or a register file through an on-chip shared memory controller of the DCU, a high-bandwidth crossbar switch of the DCU is used for realizing data copying and transmission; starting multi-row fusion execution for a short row of which the row non-zero element is lower than a DCU single-instruction multi-data width threshold value; constructing a wavefront scheduler based on a DCU asynchronous computing engine: binding an independent instruction cache region for each wavefront, and loading a multiply-add operation instruction set in advance through a prefetch instruction queue; a calculation unit state register is established, and when a wavefront scheduler ready signal is triggered, a scalar unit of the DCU is activated to execute calculation; and realizing cross-thread block reduction by adopting a DCU atomic operation accelerator. According to the method, the calculation throughput and the memory bandwidth utilization rate of large-scale structural mechanics stiffness matrix vector multiplication are effectively improved.

The present application relates to the technical field of large-scale data processing, and particularly relates to a parallel computing method and system suitable for large-scale data processing. The system comprises a task management unit, a distributed load balancing module, an elastic expansion architecture, an intelligent communication optimization module, and a resource monitoring unit, wherein the task management unit divides large-scale data into a plurality of sub-tasks by means of a task decomposer, and distributes the sub-tasks to computing nodes by means of a task scheduler and a priority distributor; the distributed load balancing module achieves global load balancing by means of a load sensing unit, a dynamic adjustment unit and a balance optimization unit; the elastic expansion architecture dynamically adjusts system resources by means of a node manager, a resource pool controller and an expansion decision-making device; the intelligent communication optimization module optimizes inter-node communication by means of a communication path planning unit, a bandwidth distribution unit and a delay compensation unit; and the resource monitoring unit monitors the system performance in real time by means of a performance collector, a state analyzer and an anomaly detector.

The invention provides a PCIe equipment fault monitoring and dynamic processing method based on intelligent prediction, and the method comprises the steps: obtaining operation parameters from a BMC (baseboard management controller), an operation system and a PCIe equipment register, carrying out the processing and time sequence feature extraction, and inputting a lightweight long short-term memory network LSTM model deployed in the BMC for fault probability prediction. And combining the prediction result and the operation parameters to calculate an equipment health score, and triggering an alarm, bandwidth degradation or hardware isolation operation according to the score. And the hardware isolation module sends a control instruction to the complex programmable logic device CPLD through the IC bus to realize non-interruption power-off isolation of the target equipment. And uploading real-time data to a cloud server through encryption communication, executing fine adjustment of the model, and returning an update weight to realize continuous optimization and version control of the model. The method can be widely applied to computing equipment such as a server, and the availability and the fault-tolerant capability of the system are improved.

The invention discloses a virtual machine computing resource dynamic allocation method and system based on a PCIe card and a storage medium, and belongs to the field of virtualization technology and hardware resource management.The method comprises the steps that the computing unit resource utilization rate of the PCIe card is monitored in real time through a hardware abstraction layer; dynamically generating a resource allocation scheme based on an improved auction algorithm, wherein the algorithm optimizes a resource quota through a time attenuation factor and a resource reuse penalty term; utilizing a programmable register remapping technology to distribute independent VF equipment for the virtual machine and establish a direct access channel; realizing interruption isolation between virtual functions through an interruption redirection controller; and during resource redistribution, atomic migration of a calculation task is completed by adopting a check point migration mechanism, and the atomic migration comprises context preloading and PCIe link layer retraining. According to the method, the problems of hardware resource distribution rigidness, insufficient isolation and migration service interruption in the prior art are solved, and fine-grained control and service lossless switching of the heterogeneous computing units are realized.

Methods and systems are provided for improving remote computing experiences. The methods leverage modified PC or console architectures, which enable both local and remote console connections. The systems operate with multiple devices through a peer-to-peer connection. In the context of gaming, the systems are engineered to address obstacles such as low upstream rates and limited bandwidth or quality of service. An AI trained on play style is used as a substitute for a low bandwidth client. Also, methods are provided for inviting remote players, transferring control to a remote user, managing controller connections, and addressing low bandwidth situations using adaptive bitrate. The enhancement of connection, single encoding, and transmission processes contributes to a superior computing and / or gaming experience for all players, irrespective of their bandwidth or quality of service. Related networks, models, apparatuses, devices, techniques, articles, architectures, packets, manifests, tables, data storages, and graphical user interfaces are provided.

The invention discloses a computing system and a control method, device, equipment, medium and product thereof, and relates to the technical field of computers.A host device, a first switch and an acceleration computing device are divided, the first switch comprises a plurality of interconnected switching controllers, and uplink ports of the switching controllers are connected with the host device; the downlink port is connected with the acceleration computing device, the binding relation of the physical link layer between the mainboard and the acceleration card is removed, the port configuration and the resource allocation path of the exchange controller can be flexibly adjusted, and the acceleration computing resources can be allocated according to needs. The first board card provided with the first slot and the cable adapter plate are arranged in the acceleration computing device, so that the acceleration computing device with high-density deployment is realized. Therefore, the method solves the problem that the expansion capability of acceleration computing resources of a multi-card system reaches a bottleneck, and lays a foundation for expanding large-scale computing power by a single host and constructing a multi-host shared large-scale computing resource pool.

The invention discloses a hardware accelerator and equipment oriented to triple sparse matrix multiplication and an application method thereof.The hardware accelerator comprises a high-bandwidth memory HBM, a crossbar switch network and an on-chip processing unit which are connected in sequence, and the on-chip processing unit comprises a hierarchical cache module, a global controller and a plurality of computing chips; each calculation piece comprises an RA calculation array, a TP calculation array and a local controller, wherein the RA calculation array and the TP calculation array are respectively used for executing front-end operation T = R * A and rear-end operation C = T * P in triple sparse matrix multiplication. The method aims at solving the problem that when a traditional universal processor processes triple sparse matrix multiplication, due to irregular memory access, uneven calculation load and sharp increase of middle parts and results, huge off-chip data carrying is confronted with serious performance and energy efficiency bottlenecks, and the calculation performance and energy efficiency of triple sparse matrix multiplication are improved.

In some implementations, a system includes a set of servers configured to establish a set of virtual machines to provide a computing environment; a set of compute express link (CXL) interface components configured to communicate with the set of servers via a set of CXL interconnects; and a controller configured to at least one of: encrypt protocol data against a CXL interposer security threat associated with the set of CXL interconnects or a malicious extension security threat, provide a secure handshake verification of an identity of the set of CXL interface components, enforce a chain of trust rooted in hardware of the set of CXL interface components; restrict access to an area of memory of the set of CXL interface components that stores security data for verified or secured processes; or perform a security check and set up a set of security features of the set of CXL interface components.

A controller can be used with a computing device to select and / or interact with content using user input devices on the controller. The content can be locally-stored on the computing device and / or streamed from a remote device. In one embodiment, a contextually-aware platform service switcher is provided. In another embodiment, a system and method for automatic content capability detection are provided. In yet another embodiment, a system and method for rich content browsing multitasking on device operating systems with multitasking limitations are provided. These embodiments can be used alone or in combination. Other embodiments are provided.

The invention discloses a computing power collaborative management method and system based on a cross-architecture state sensing engine, and relates to the technical field of GPU computing power pooling scheduling. The method comprises the following steps: establishing a communication link set between a plurality of GPU instances and a plurality of CPU controllers; collecting and analyzing indexes such as data throughput rate, queue length and communication time delay of each link in real time, and dynamically identifying a system bottleneck link; aiming at the detected bottleneck link, the fine granularity of the bottleneck link is split into a plurality of sub-links, and each sub-link is allocated with an independent cache queue and a flow control strategy, so that fine management and isolation of link resources are realized; furthermore, the scheduling priority is calculated according to the real-time state index of each sub-link, and the optimal sub-link is preferentially selected for task scheduling during task allocation. Therefore, the resource utilization rate and the task scheduling efficiency in the multi-tenant heterogeneous computing power pool environment are effectively improved, and the conditions of local link congestion and false idle / false busy of the computing power pool are remarkably relieved.

The invention relates to the technical field of computers, discloses a heterogeneous computing low-delay communication method and system, and aims to solve the problem of high delay caused by high communication protocol overhead, lack of dynamic scheduling collaboration, memory migration redundancy and non-uniform cross-node communication abstraction in existing heterogeneous computing. The method comprises the following steps: receiving a task scheduling request and analyzing a task dependency graph; tasks are dynamically allocated based on node loads and link states; rDMA, NVLink or PCIe straight-through protocols are adaptively selected according to node types to establish communication channels; zero-copy data exchange is realized through a shared memory mapping buffer area; hardware timestamps are utilized to synchronize feedback delays with PTP to optimize scheduling. The system comprises a heterogeneous computing node cluster, a unified communication scheduling controller, a low-delay communication protocol stack, a shared memory mapping buffer area and a communication delay sensing task distributor. According to the scheme, the communication delay is remarkably reduced, and the throughput and the task execution efficiency are improved.

A system, method, and computer-readable media for executing applications for radio interface controller (RIC) management are disclosed. The system includes far-edge datacenters configured to execute a radio access network (RAN) function and a real-time RIC; near-edge datacenters configured to execute a core network function and a near-real-time RIC or a non-real-time RIC; and a central controller. The central controller is configured to: receive inputs of application requirements, hardware constraints, and a capacity of first and second computing resources at the far-edge datacenters and near-edge datacenters; enumerate a plurality of feasible combinations of application locations and configurations that satisfy the application requirements and hardware constraints; incrementally allocate a quant of the first or second computing resources to a feasible combination that would produce a greatest utility from the quant based on a utility function; and deploy each of the plurality of applications.

The invention discloses a consistency interconnection control device and method, an electronic device, a product and a computing system, and relates to the technical field of computers, the consistency interconnection control device is provided and comprises a consistency interconnection network, a first controller and a first connector, the consistency interconnection network comprises a plurality of interconnected consistency interconnection nodes, the consistency interconnection node is connected with the first card slot for installing the acceleration card through the first connector, and the first controller manages the state of the cache line of the acceleration card and controls the consistency interconnection network to execute the consistency interconnection read-write task between different acceleration cards, so that the consistency interconnection system for the acceleration computing cluster is realized. By implementing the cache consistency between the acceleration cards, when the acceleration computing cluster executes distributed computing, the cache can be hit firstly, so that access to a local memory and memories of other acceleration cards is reduced, the problem of high time consumption of communication between different accelerators of the acceleration computing cluster is solved, and the efficiency of distributed computing is improved.

The present application provides a complex programmable logic device (CPLD)-based data processing method and system, and a computing device. The CPLD is arranged on a hard disk backplane of a server, and the hard disk backplane supports a universal backplane management (UBM) protocol; the hard disk backplane comprises an HFC connector for connecting to a RAID controller and a DFC connector for connecting to a hard disk slot, and the CPLD is connected to the HFC connector and the DFC connector, respectively. The method comprises: when a hard disk is inserted into the hard disk slot, determining an interface type of the hard disk according to a signal level transmitted by the DFC; processing interaction data between the RAID controller and the hard disk according to the hard disk interface type, wherein the interaction data comprises data indicating the hard disk interface type, data indicating a hard disk state and read / write operation command data; and transmitting the processed data to the RAID controller or the hard disk so as to achieve hard disk management, wherein the hard disk comprises a hard disk of an SAS / SATA / NVME interface type. In this way, new logic functionality is added to an existing logic chip of the hard disk backplane to achieve the functionality of the UBM protocol.

A computing system includes a computing device configured to execute a plurality of virtual machines, each virtual machine of the plurality of virtual machines configured to provide control plane functionality for at least a different respective subset of forwarding units of a network device, the computing device distinct from the network devices. The computing system also includes a policy agent configured to execute on the computing device. The agent is configured to determine that a particular virtual machine of the plurality of virtual machines provides control plane functionality for one or more forwarding units of the network device; determine control plane usage metrics for resources of the particular virtual machine; and output, to a policy controller, data associated with the control plane usage metrics and data associating the particular virtual machine with the one or more forwarding units for which the particular virtual machine provides control plane functionality.

The invention discloses a circuit, a data processing method, equipment, a medium and a program product in the technical field of computers. In the application, the three-dimensional heterogeneous computing body layer can adapt to diversified computing power requirements, and is beneficial to realizing higher routing and higher data transmission efficiency between nodes. The shared cache layer is beneficial to realizing cache consistency of different heterogeneous computing nodes, and the cache utilization rate is improved. The internal interconnection module and the external interconnection module provided by the interface layer are easy to realize internal and external efficient communication. A first channel controller provided by the control layer can realize direct connection of physical channels between the control layer and the three-dimensional heterogeneous computing body layer and direct connection of physical channels between the control layer and the shared cache layer; a second channel controller provided by the control layer can realize direct connection of physical channels between the control layer and the interface layer; therefore, the communication delay between different levels can be reduced, the data transmission efficiency between different levels can be improved, and a high-bandwidth application scene can be met.

The invention provides a solid state disk data reading method and device, equipment and a storage medium. Relates to the technical field of storage. The method comprises the steps of obtaining a historical read operation data set of the solid state disk; the method comprises the following steps: dividing a historical read operation data set according to a set time window to obtain a plurality of samples, and performing embedding processing on the samples to obtain a corresponding embedded time sequence; performing stacking processing on the embedded time sequence through N stacking layers to obtain a stacking enhanced time sequence; linear prediction is carried out based on the stacking strengthening time sequences corresponding to all the samples, and a pre-reading operation sequence is obtained; according to the pre-reading operation information, reading corresponding data from a flash memory of the solid state disk and storing the data in a memory buffer area of a controller of the solid state disk; and receiving a data reading command, determining that the data reading command hits the data in the memory buffer area, and reading the hit data from the memory buffer area through the PCIe bus. Therefore, low-computing-power model prediction is realized and resource consumption and access delay are reduced.

Methods and systems related to parallel computing using heterogeneous networks of computational nodes are disclosed herein. A method for executing a complex computation on a heterogeneous set of computational nodes linked together by a set of links in a network is disclosed. The method includes compiling, using a table of bandwidth values for the set of links in the network, a set of instructions for routing data for the execution of the complex computation. The method also includes configuring a set of programmable controllers on the heterogeneous set of computational nodes with the set of instructions. The method also includes executing the set of instructions using the set of programmable controllers. The method also includes routing data through the network to facilitate the execution of the complex computation by the heterogeneous set of computational nodes and in response to the execution of the instructions.

Embodiments provide solutions for establishing a secure communication channel between systems. A controller e.g. an administrator is able to construct a logical network of computing resources and define the relationships between those resources and the hierarchical structures that they are part of. Tags are used to label or identify the resources in accordance with their role or class within their network e.g. “staff laptop”, “guest laptop” etc., and multiple Tags can be assigned to a given resource. Policies (rules) associated with each tag provide a richness of functionality for each type of class as well as enabling constraints regarding use, security and / or user-related permissions to be applied across an entire group of network resources in a simple, efficient and secure manner. The controller can construct, define and control the resources within the connected environment. Embodiments provide solutions for preventing ARP poisoning attacks, and also improved approaches to DNS and PKI in an overlay network.