592 results about "Controller (computing)" patented technology

Some embodiments provide an elastic architecture for providing a service in a computing system. To perform a service on the data messages, the service architecture uses a service node (SN) group that includes one primary service node (PSN) and zero or more secondary service nodes (SSNs). The service can be performed on a data message by either the PSN or one of the SSN. However, in addition to performing the service, the PSN also performs a load balancing operation that assesses the load on each service node (i.e., on the PSN or each SSN), and based on this assessment, has the data messages distributed to the service node(s) in its SN group. Based on the assessed load, the PSN in some embodiments also has one or more SSNs added to or removed from its SN group. To add or remove an SSN to or from the service node group, the PSN in some embodiments directs a set of controllers to add (e.g., instantiate or allocate) or remove the SSN to or from the SN group. Also, to assess the load on the service nodes, the PSN in some embodiments receives message load data from the controller set, which collects such data from each service node. In other embodiments, the PSN receives such load data directly from the SSNs.

The Field Programmable Instrument Controller (FPIC) is a stand-alone low to high performance, clocked or unclocked multi-processor that operates as a microcontroller with versatile interface and operating options. The FPIC can also be used as a concurrent processor for a microcontroller or other processor. A tightly coupled Multiple Chip Module design incorporates non-volatile memories, a large field programmable gate array (FPGA), field programmable high precision analog to digital converters, field programmable digital to analog signal generators, and multiple ports of external mass data storage and control processors. The FPIC has an inherently open architecture with in-situ reprogrammability and state preservation capability for discontinuous operations. It is designed to operate in multiple roles, including but not limited to, a high speed parallel digital signal processing; co-processor for precision control feedback during analog or hybrid computing; high speed monitoring for condition based maintenance; and distributed real time process control. The FPIC is characterized by low power with small size and weight.

A system that facilitates concurrency control for a policy-based management system that controls resources in a distributed computing system. The system operates by receiving a request to perform an operation on a lockable resource from a controller in the distributed computing system. This controller sends the request in order to enforce a first policy for controlling resources in the distributed computing system. In response the request, the system determines whether the controller holds a lock on the lockable resource. If so, the system allows the controller to execute the operation on the lockable resource. If not, the system allows the controller an opportunity to acquire the lock. If the controller is able to acquire the lock, the system allows the controller to execute the operation on the lockable resource.

Methods and apparatus relating to network packet payload compression/decompression are described. In an embodiment, an uncompressed packet payload may be compressed before being transferred between various components of a computing system. For example, a packet payload may be compressed prior to transfer between network interface cards or controllers (NICs) and storage devices (e.g., including a main system memory and/or cache(s)), as well as between processors (or processor cores) and storage devices (e.g., including main system memory and/or caches). Other embodiments are also disclosed.

A method, system, and apparatus for performing computations.

In a method, arguments X and K are loaded into session memory, and X mod P and X mod Q are computed to give, respectively, X_P and X_Q. X_P and X_Q are exponentiated to compute, respectively, C_P and C_Q. C_P and C_Q are merged to compute C, which is then retrieved from the session memory.

A system includes a computing device and at least one computational apparatus, wherein the computing device is configured to use the computational apparatus to perform accelerated computations.

An apparatus includes a chaining controller and a plurality of computational devices. A first chaining subset of the plurality of computational devices includes at least two of the plurality of computational devices, and the chaining controller is configured to instruct the first chaining subset to operate as a first computational chain.

Aspects of the present invention relate to a multi-sided hand-held controller for a head-worn computing system. The hand-held computer controller includes a first user control interface on a first side of the hand-held controller, a second user control interface on a second side of the hand-held controller, and a control system adapted to detect which of the first side and second side is an active control side of the controller, positioned properly for user interaction. Following the detection, the control system can activate the active control side to accept user interactions for control of a computer.

The present systems include a memory module containing a plurality of RAM chips, typically DRAM, and a memory buffer arranged to buffer data between the DRAM and a host controller. The memory buffer includes an error detection and correction circuit arranged to ensure the integrity of the stored data words. One way in which this may be accomplished is by computing parity bits for each data word and storing them in parallel with each data word. The error detection and correction circuit can be arranged to detect and correct single errors, or multi-errors if the host controller includes its own error detection and correction circuit. Alternatively, the locations of faulty storage cells can be determined and stored in an address match table, which is then used to control multiplexers that direct data around the faulty cells, to redundant DRAM chips in one embodiment or to embedded SRAM in another.

A safe including a safe controller coupled to a data transfer port is provided. The safe controller is configured to selectively enable device data to pass through the data transfer port when a valid code is received by the safe controller. A system for controlling data communications with an internal device in a safe is also provided. The system includes an external computing device configured to execute a series of instructions, and a safe. The safe includes a data transfer port coupled to the external computing device and the internal device. The safe also includes a safe controller coupled to the data transfer port, wherein the safe controller is configured to selectively enable communication between the external computing device and the internal device when a valid code is received by the safe controller.

The invention provides a multi-screen parallel massive information display system. An integral splicing wall is divided by the system with four screens as a unit, each four screens are controlled by an accessory node controller, and the accessory node controllers are connected with a master node controller through a high-speed internet. Under unified allocation and organization of the master node controller, external massive data (including analog video signals, digital signals of a computer and the like) are transmitted to the high-speed internet after quantization and digital processing and finally transmitted to the accessory node controllers, and images are parallelly rendered to a video memory by the accessory node controllers and displayed on a high-definition splicing display screen. The system comprehensively applies the CPU (central processing unit)+CPU parallel processing technology, the cloud computing technology and the high-speed network technology, so that the massive data which cannot be processed and displayed by a traditional system are quickly displayed in real time.

A computer system architecture and memory controller for close-coupling within a hybrid computing system using an adaptive processor interface port (“APIP”) added to, or in conjunction with, the memory and I/O controller chip of the core logic. Memory accesses to and from this port, as well as the main microprocessor bus, are then arbitrated by the memory control circuitry forming a portion of the controller chip. In this fashion, both the microprocessors and the adaptive processors of the hybrid computing system exhibit equal memory bandwidth and latency. In addition, because it is a separate electrical port from the microprocessor bus, the APIP is not required to comply with, and participate in, all FSB protocol. This results in reduced protocol overhead which results higher yielded payload on the interface.

Techniques are provided for use in accordance with relates to computing utilities. For example, in one aspect of the invention, a method for use in a computing utility, wherein the computing utility comprises a plurality of application service provider systems and a utility controller, and each application service provider system comprising an application controller, comprises the following steps. An application request to one of the plurality of application service provider systems is obtained. Then, in response to the application request, at least one of: (i) the application controller of the application service provider system to which the application request is directed computes a value of a business metric associated with a resource action; and (ii) the utility controller computes a value of a business metric associated with a resource action.

The invention provides a computing power resource scheduling method and device, relates to the technical field of communication, and is used for solving the problem of overlarge load of an SDN controller. The method comprises the steps that the SDN controller receives a first calculation task sent by customer premise equipment CPE; the SDN controller determines N target core nodes according to thedemand information of the first computing task, the network state of each core node in the M core nodes and total idle computing power resources which can be scheduled by each core node in the M corenodes; and the SDN controller allocates a second calculation task to the N target core nodes through the CPE. The method and device are applied to the process of scheduling the computing power resources.

Systems and methods for data aggregation and processing are provided in manner that is decentralized and preserves privacy. A data aggregation and computation system may include an interface, a controller, and one or more clusters of computation nodes. The interface may receive an inquiry from a requesting entity for computing information regarding an individual based on pieces of information held by a plurality of entities. The controller may communicate an identifier for the individual to a processor system associated with each of the entities based on the inquiry. The clusters of computation nodes may each receive encrypted data fragments from each of the processor systems, the data fragments comprising unrecognizable fragments that no individual processor system can re-assemble to recover the information, perform secure, multi-party computations based on the data fragments, and generate a result based on the secure, multi-party computations for the individual.

A system may include a database, where a managed network includes a computing cluster that provides networking, storage, and virtualization services distributed across a plurality of computing devices, where each computing device can execute one or more respective software applications and comprises: (i) a respective controller, and (ii) a respective storage device, and where the storage devices of the plurality of computing devices collectively form a storage pool. The system may also include a proxy server application configured to: request and receive computing cluster data that identifies the computing cluster; request and receive storage pool data that identifies the storage pool; request and receive storage container data that identifies storage containers of the storage pool; request and receive controller data that identifies the controllers of the plurality computing devices; and provide, to the database, the computing cluster data, the storage pool data, the storage container data, and the controller data.

A controller to instruct execution in an environment of plural computing resources. The controller comprising: an information collecting unit to collect available resource information of computing resources available to execute an application indicating an amount and/or type of computing resource available in categories of computing resource; scalability information including an indication of application execution rate; and performance target information including an indication of performance targets. The controller further comprises: a configuration selection unit to select a configuration which will come closest to meeting, the performance targets; and an instructing unit to instruct the execution of the application using the selected configuration.