543 results about "Controller (computing)" patented technology

The present application relates to the technical field of large-scale data processing, and particularly relates to a parallel computing method and system suitable for large-scale data processing. The system comprises a task management unit, a distributed load balancing module, an elastic expansion architecture, an intelligent communication optimization module, and a resource monitoring unit, wherein the task management unit divides large-scale data into a plurality of sub-tasks by means of a task decomposer, and distributes the sub-tasks to computing nodes by means of a task scheduler and a priority distributor; the distributed load balancing module achieves global load balancing by means of a load sensing unit, a dynamic adjustment unit and a balance optimization unit; the elastic expansion architecture dynamically adjusts system resources by means of a node manager, a resource pool controller and an expansion decision-making device; the intelligent communication optimization module optimizes inter-node communication by means of a communication path planning unit, a bandwidth distribution unit and a delay compensation unit; and the resource monitoring unit monitors the system performance in real time by means of a performance collector, a state analyzer and an anomaly detector.

The invention discloses a hardware accelerator and equipment oriented to triple sparse matrix multiplication and an application method thereof.The hardware accelerator comprises a high-bandwidth memory HBM, a crossbar switch network and an on-chip processing unit which are connected in sequence, and the on-chip processing unit comprises a hierarchical cache module, a global controller and a plurality of computing chips; each calculation piece comprises an RA calculation array, a TP calculation array and a local controller, wherein the RA calculation array and the TP calculation array are respectively used for executing front-end operation T = R * A and rear-end operation C = T * P in triple sparse matrix multiplication. The method aims at solving the problem that when a traditional universal processor processes triple sparse matrix multiplication, due to irregular memory access, uneven calculation load and sharp increase of middle parts and results, huge off-chip data carrying is confronted with serious performance and energy efficiency bottlenecks, and the calculation performance and energy efficiency of triple sparse matrix multiplication are improved.

The invention relates to the technical field of computers, discloses a heterogeneous computing low-delay communication method and system, and aims to solve the problem of high delay caused by high communication protocol overhead, lack of dynamic scheduling collaboration, memory migration redundancy and non-uniform cross-node communication abstraction in existing heterogeneous computing. The method comprises the following steps: receiving a task scheduling request and analyzing a task dependency graph; tasks are dynamically allocated based on node loads and link states; rDMA, NVLink or PCIe straight-through protocols are adaptively selected according to node types to establish communication channels; zero-copy data exchange is realized through a shared memory mapping buffer area; hardware timestamps are utilized to synchronize feedback delays with PTP to optimize scheduling. The system comprises a heterogeneous computing node cluster, a unified communication scheduling controller, a low-delay communication protocol stack, a shared memory mapping buffer area and a communication delay sensing task distributor. According to the scheme, the communication delay is remarkably reduced, and the throughput and the task execution efficiency are improved.

The invention discloses a circuit, a data processing method, equipment, a medium and a program product in the technical field of computers. In the application, the three-dimensional heterogeneous computing body layer can adapt to diversified computing power requirements, and is beneficial to realizing higher routing and higher data transmission efficiency between nodes. The shared cache layer is beneficial to realizing cache consistency of different heterogeneous computing nodes, and the cache utilization rate is improved. The internal interconnection module and the external interconnection module provided by the interface layer are easy to realize internal and external efficient communication. A first channel controller provided by the control layer can realize direct connection of physical channels between the control layer and the three-dimensional heterogeneous computing body layer and direct connection of physical channels between the control layer and the shared cache layer; a second channel controller provided by the control layer can realize direct connection of physical channels between the control layer and the interface layer; therefore, the communication delay between different levels can be reduced, the data transmission efficiency between different levels can be improved, and a high-bandwidth application scene can be met.

The invention discloses a cache maintenance system of a heterogeneous computing system and electronic equipment, and relates to the technical field of data processing, a first directory controller manages the consistency state of a host end, and a second directory controller manages the consistency state of an equipment end. The consistency maintenance operation is firstly efficiently processed by the corresponding directory controller in the storage domain, cross-device frequent coordination communication is reduced, and when cross-domain data access occurs, the two directory controllers cooperate through an established communication coupling mechanism and execute global consistency maintenance as required. The method not only can adapt to a high-burst and high-parallel access mode of a device end, but also can avoid direct conflicts with a cache management mechanism of a host end, and realizes global consistency through distributed collaboration. The technical problem of performance bottleneck of cache consistency in the heterogeneous system is solved, and the technical effect that the overall data access efficiency of the heterogeneous system is improved while the correctness is maintained is achieved.

The invention belongs to the field of storage, and discloses a high-energy-efficiency mixed-precision charge domain in-storage computing architecture and a working method thereof. Comprising a single-slope analog-to-digital converter, a sparsity perception input alignment module, a multi-bit input accumulation module, a controller and an accumulation module, wherein the single-slope analog-to-digital converter consists of an index calculation array, a mantissa calculation array, a shared ramp voltage generator and a bidirectional counter. According to the invention, serial input binary coding based on capacitor voltage is suitable for floating point and integer multiply-accumulate operation with flexible bit width; according to the invention, a shared single-slope analog-to-digital converter (SS-ADC) is introduced to realize maximum index search and index difference calculation; according to the method, a sparsity perception calculation scheme is provided, low-importance input-weight pairs are filtered out through an adjustable threshold value, and invalid power consumption is reduced; according to the method, a multi-bit input accumulation method is further combined, and an ADC redundancy optimization quantization and normalization process is utilized, so that the overall energy efficiency is improved.

The invention discloses a hand-eye cooperative robot control system and method based on dynamic operator arrangement, an upper computer planning layer operates a master control computer to periodically trigger task scheduling, a joint controller of a lower computer execution layer receives an instruction through a redundant bus to perform servo control, hand-eye camera data triggers a visual assembly line through an interrupt event, and a visual assembly line is controlled through a control interface. According to the method, pressure is calculated through visual processing, motion planning and joint control in a load sharing mode, a double-buffering mechanism is adopted to enable current frame visual processing and previous frame motion control to be executed in an overlapping mode, real-time scheduling and parallel computing of tasks are completed, hot data are cached in a memory database, cold data are archived to an HDFS and migrated through an LRU strategy, and the real-time scheduling and parallel computing of the tasks are completed. Data type conversion is automatically derived and performed based on a feature type registry, and conditional branch execution is triggered according to real-time sensor data. According to the control system, cross-hardware plug and play, algorithm flow configurability and data flow real-time sharing are achieved, and the requirement for improving the efficiency of complex operation tasks is met.

The invention provides an intelligent control method and system for a refrigeration house refrigeration device based on edge calculation, and the method comprises the steps: collecting first data, and transmitting the first data to an edge calculation controller; establishing a comprehensive thermodynamic mechanism model in the edge calculation controller; taking the first data and the historical operation data as training samples, and combining a comprehensive thermodynamic mechanism model as a physical constraint and a machine learning model to train a prediction model; obtaining an optimal control strategy based on the prediction model; the prediction model is used for monitoring the degree that the equipment operation state deviates from the normal working condition, and when the predicted fault probability exceeds a preset threshold value, the optimal control strategy is automatically adjusted; and according to the deviation between the control execution effect and the expected target, adjusting weight parameters of the machine learning model, and updating equipment characteristic parameters of the comprehensive thermodynamic mechanism model. The temperature control precision can be improved, the energy consumption level can be reduced, the service life of equipment can be prolonged, the maintenance cost can be reduced, and the fault prediction and self-adaptive adjustment capabilities can be realized.

A data protection method and system are provided. At least one computing device provides information representing failure of a drive that is assigned to a RAID group. Available storage on each of a plurality of drives in use in the RAID group is identified and at least one virtual drive is built using at least the available storage. Data associated with the failed drive is provided to the virtual drive(s). The virtual drive(s) is / are assigned to the RAID group, and appears to be the failed drive in a non-failed state. Information representing the failed drive having been replaced is received and data from the at least one virtual drive is provided to the replacement drive. The replacement drive is assigned to the RAID group. The replacement drive appears to the RAID controller to be the failed drive. The virtual drive(s) are released.

The invention relates to the technical field of electric digital data processing, and discloses a data processing system for message management, which comprises a look-ahead buffer unit for maintaining a sliding window with variable window size parameters and pre-reading a message sequence; the mapping logic circuit is used for converting the resource identifier into a resource request mask; the state register is used for storing a global occupancy bitmap for representing resource occupancy; the scheduling controller is used for distributing messages according to bit operation results, counting bitmap setting quantity based on the population counting instruction to generate a resource saturation index, and then adjusting window size parameters in a negative feedback mode. The resource contention entropy value is directly sensed by utilizing a hardware instruction, nanosecond-level self-adaptive breathing control of a scheduling window is realized, and the service life of the scheduling window is prolonged. The problem of physical computing power collapse caused by bitmap scanning jitter in a high-concurrency scene is solved.

The invention discloses an industrial intelligent control system and method, relates to the technical field of industrial automatic control, and mainly aims to solve the problems of low data cross-layer interaction efficiency, system global optimization, poor safety, poor expansion capability, difficulty in function upgrading and difficulty in fusion of AI control and traditional control in the existing industrial intelligent control scheme. The system comprises a basic control layer, an intelligent I / O layer and an intelligent control layer. The basic control layer comprises an extended I / O cabinet, a common controller and a main control network A / B; the intelligent I / O layer comprises an intelligent I / O cabinet and an intelligent I / O switch; the intelligent control layer comprises an intelligent controller, a credibility regulator, a hyper-fusion module and an intelligent middle table, an end-edge-cloud intelligent collaborative architecture is constructed, the computing power of a DCS is enhanced, the development collaborative safety capability of an intelligent algorithm of the system is improved, and safety fusion and smooth transition of AI intelligent control and traditional control are promoted.

The invention relates to the technical field of microelectronics, and discloses a three-dimensional stacked near-memory computing architecture, a chip and a data access method. The memory device comprises at least one computing chip layer and at least one memory chip layer which are stacked along a first direction, a plurality of vertical interconnection channels extending along the first direction; the memory chip layer comprises a plurality of memory banks; the computing chip layer comprises a plurality of computing cluster units; the computing cluster unit comprises at least one storage controller; and the storage controller is connected with at least one of the plurality of storage banks through the vertical interconnection channel and is used for managing data in the correspondingly connected storage banks. The problems that in a three-dimensional stacking computing architecture, storage access delay is high, and the bandwidth expansion capacity is limited are solved.

The invention discloses a virtual machine monitor system for a resource-limited persistent memory server, which comprises a configuration file module, a CPU (Central Processing Unit) management module, a memory management module, a cache management module, an interrupt management module, a cross-partition communication module and a virtual machine management module. The CPU management module is used for binding a virtual CPU to a physical CPU core, so that computing resources of the virtual machines are dedicated, and meanwhile, the virtual machines are prevented from competing for the CPU; the memory management module is used for dividing a physical memory region according to a configuration file and realizing address space isolation between virtual machines by utilizing two-stage address translation; the cache management module is used for performing isolation control on cache access of a plurality of virtual machines through a coloring mechanism of the last-level cache; and the interrupt management module is used for simulating the universal interrupt controller, and the virtual machine monitor re-injects the interrupt into the target virtual machine according to the configuration file after capturing the hardware interrupt.

A digital asset custody system dynamically provisions clusters of multi-party computation (MPC) nodes to securely create different private key shares for signing digital asset transactions and generate blockchain addresses for digital asset owners (AOs). Each cluster of MPC nodes is configured for an AO and to operate in a plurality of computing environments. Each of the computing environments is associated with a respective different signing party, and each computing environment includes a respective one of plural MPC node initializers and a respective one of plural MPC node operators. An MPC controller and MPC node initializers perform operations to generate first configuration information for each MPC node in a first MPC cluster of MPC nodes. Each MPC node operator, based on the first configuration information, deploys one of the MPC nodes in the first MPC cluster in the computing environment corresponding to where the MPC node operator operates, such that the one MPC node in the first MPC cluster is deployed into a different one of the plurality of computing environments as compared to the computing environments into which the other MPC nodes in the first MPC cluster are deployed. Analogous operations are performed to generate second configuration information to deploy a second MPC cluster, third configuration information to deploy a third MPC cluster, etc. as desired.

The invention relates to the technical field of semiconductors, provides a semiconductor device, and is used for solving the technical problem that a large lifting space still exists in a high-bandwidth memory technology. The semiconductor device includes: a chip stacking structure including a first semiconductor chip and a second semiconductor chip stacking structure stacked in a first direction; the first semiconductor chip comprises a controller, a calculation module and an interface module; the controller is configured to execute a first access operation on storage data in the second semiconductor chip stacking structure and send the storage data to the interface module to allow external equipment to access the storage data in the second semiconductor chip stacking structure through the interface module; and performing a second access operation on the storage data in the second semiconductor chip stack structure and sending the storage data to the computing module to allow the computing module to perform a computing operation on the storage data. Therefore, the integration level can be improved, the data transmission path can be shortened, and bandwidth consumption and energy consumption loss can be reduced.

The invention relates to the technical field of building self-control, and discloses a building self-control real-time data processing system based on a heterogeneous computing architecture. Aiming at the problems of single data processing architecture, weak parallel processing capability, low core algorithm execution efficiency, insufficient task scheduling flexibility and the like of the existing building automatic control controller, the system innovatively adopts a heterogeneous computing architecture of a master control core, a multi-task slave core and a special hardware accelerator; and in combination with a dynamic task scheduling mechanism, a three-level data caching strategy and a multi-source data synchronous acquisition module, parallel efficient processing of multi-type building equipment data is realized. The internal logic loop period of the system is shortened to be within 15 milliseconds, the PID operation time delay is as low as 0.4 microsecond / path, the data processing throughput is improved by more than 4 times, high-frequency cooperative control of 128-path equipment is supported, meanwhile, fault redundancy and load balancing capacity is achieved, the real-time performance, the control precision and the operation reliability of the building automatic control system are remarkably improved, and the building automatic control system is suitable for large-scale popularization and application. The method is suitable for complex control scenes such as large intelligent buildings, data centers and commercial complexes.

The embodiment of the invention provides a security control method, a baseboard management controller, a computer program product and a storage medium. A security subsystem and a function subsystem which are isolated from each other by hardware are arranged in the baseboard management controller, so that the defense capability of the security subsystem to hardware attacks can be effectively guaranteed. On the basis, security control firmware is arranged in the security subsystem, and the security subsystem can control the computing device to be safely started by executing the security control firmware; moreover, through a bus interface of the baseboard management controller, an access request which is initiated by each system-on-chip in the computing equipment and aims at the target storage component can be received, and the security subsystem can perform access control on the access request by executing the security management and control firmware. Therefore, the baseboard management controller can be used as a platform trust root in the computing equipment to control the computing equipment to be safely started and protect data stored in the target storage component in the computing equipment, so that the safety of the computing equipment is guaranteed.

According to the near memory DMA asynchronous controller, the data transmission method of the AI computing system, the medium and the product, a buffer does not need to be configured, the area of the near memory DMA asynchronous controller is reduced, the data carrying path is shortened, and the power consumption overhead in the data carrying process is reduced. Bus bit width address alignment is carried out in the near memory DMA asynchronous controller and then transmission is carried out, so that the utilization rate of the bus bandwidth is improved, and the current requirements of the AI chip are adapted with low logic overhead, low power consumption and high transmission efficiency; the asynchronous control mode can enable the calculation process and the data transmission process of the AI chip in the operation of the network model to be higher in parallel degree and higher in coupling degree.

The invention discloses a heterogeneous computer and system for dynamically optimizing cache resources and a cache allocation method. The heterogeneous computer comprises a hardware performance monitoring unit, a main controller, a plurality of heterogeneous computing units and a shared cache unit. The hardware performance monitoring unit detects the utility gradient of the heterogeneous computing units based on a perturbation and observation method, the utility index and the cache resource allocation amount of each heterogeneous computing unit are collected before and after the cache resource allocation amount is changed, and the utility gradient is the utility index variation corresponding to the unit cache resource allocation amount variation; if the utility gradient is not smaller than a preset first threshold value, the main controller increases the cache resource allocation quantity of the heterogeneous computing unit; and if the utility gradient is not greater than a preset second threshold value, the main controller maintains or reduces the cache resource allocation quantity of the heterogeneous computing unit. According to the method, dynamic adaptation, intelligent scheduling and efficient utilization of cache resources can be realized, the execution efficiency of high-priority tasks is guaranteed, and the performance loss caused by cache competition and conflict is reduced.

Apparatus and method for a low-power quantum controller. For example, one embodiment of an apparatus comprises: a low-power quantum control chip to process a first portion of quantum program code associated with a quantum computing application, the low-power quantum control chip configurable within a dilution refrigeration unit, the low-power quantum control chip comprising: an interface to couple the quantum control chip to a computer which is to execute a second portion of the quantum program code associated with the quantum computing application; a Static Random Access Memory (SRAM) to store the first portion of quantum program code; a compute unit to execute the first portion of quantum program code during execution of the quantum computing application and responsively generate control signals; routing hardware logic to route the control signals; a plurality of digital signal processor (DSP) units coupled to the routing hardware logic, at least one DSP of the plurality of DSPs to receive one or more of the control signals and responsively generate analog qubit control signals to control qubits of a quantum processor.

The invention provides a computing system and a configuration method, and relates to the technical field of hardware, the computing system comprises a plurality of mainboards, the mainboards are provided with control circuits and functional devices, and the control circuits are connected with the functional devices; the management board is provided with a first controller, and the first controller is connected with one of the main boards; the expansion board is provided with an expansion circuit; wherein the control circuit of the main board is configured as follows: in a first mode, a functional device of the main board is connected to a first controller on the management board through the control circuit on the main board and an expansion circuit on the expansion board; and in the second mode, the functional device of the main board is connected to the first controller on the management board through the control circuit on the main board.

The invention discloses a future computing-oriented super-node cluster liquid cooling efficient computing platform and a resource management method thereof. A CPU, a GPU and a reserved photon / quantum accelerator slot in a super node are virtualized into a computing resource pool through a unified heterogeneous resource abstraction layer, and a CXL large-capacity memory and an NVMe-oF storage are virtualized into a cross-node memory resource pool and a storage resource pool respectively; the physical state of the super node cluster, the temperature-flow distribution of the liquid cooling heat dissipation system and the operation parameters of the heat recovery system are mapped in real time in the digital twin system; the intelligent scheduler takes task completion time, cluster total power consumption and waste heat recovery efficiency as a joint optimization target, and decomposes the task based on a virtual model; and in the task execution process, the energy efficiency cooperative controller adjusts the operation frequency of the allocated resources and the rotating speed of the liquid cooling pump in real time according to the node temperature change predicted by the digital twin model, so that the task performance, the energy consumption and the heat dissipation capability are globally matched.

An apparatus to facilitate supporting 8-bit floating point format operands in a computing architecture is disclosed. The apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that operates on 8-bit floating point operands to cause the processor to perform a parallel dot product operation; a controller to schedule the decoded instruction and provide input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and systolic dot product circuitry to execute the decoded instruction using systolic layers, each systolic layer comprises one or more sets of interconnected multipliers, shifters, and adder, each set of multipliers, shifters, and adders to generate a dot product of the 8-bit floating point operands.

The invention provides a near-storage DMA data transpose controller, a data transpose method, a medium and a product, the near-storage DMA data transpose controller is arranged on a data transmission path between a far-end memory and a near-end memory of an AI computing chip, and comprises a first DMA control module and a second DMA control module; the transpose operation only occurs after the data is read from the near-end memory, so that an independent transpose processing link is reduced, the transpose power consumption overhead and the operation delay are reduced, the bus bandwidth utilization rate reduction caused by transpose is avoided, and the hardware resource overhead is reduced. The dynamic segmentation strategy limits the non-aligned access to the first data block in a centralized mode, and the overall bandwidth utilization rate is improved. Transposition operation is separated from a calculation unit, transposition is synchronously completed in the data carrying process, calculation resources are released, and the operation period and the power consumption overhead are reduced.

Technologies disclosed herein provide for a multi-device host controller to emulate a first embedded device of a plurality of embedded devices of a computing system. Emulating an embedded device includes generating a descriptor based on a Universal Serial Bus (USB) protocol and on peripheral configuration information associated with the first embedded device. The peripheral configuration information is pre-programmed for the multi-device host controller. The multi-device host controller provides the first descriptor to a software stack running on a processor of the computing system. The first embedded device operates according to a Universal Serial Bus (USB) protocol or a non-USB protocol. The multi-device host controller can further take an action to autonomously manage the first embedded device based on one or more inputs received from one or more other embedded devices connected to the multi-device host controller.

The invention belongs to the field of edge computing, and discloses an edge intelligent computing device and method supporting multi-level storage and computing integrated acceleration, and the device comprises a main processor system, a near memory computing module and a near flash memory computing module. The near memory calculation module integrates an NPU (Network Processing Unit) with a distributed SRAM (Static Random Access Memory) and an HBM DRAM (Dynamic Random Access Memory) with an MAC (Media Access Control) array, and realizes high-throughput reasoning acceleration And the near flash memory calculation module is used for tightly coupling the SSD controller and the retrieval acceleration engine to realize the nearest retrieval acceleration of mass data at the SSD level. All the modules are interconnected through a PCIe bus, a three-level storage and calculation integrated framework of SRAM-HBM DRAM-SSD is constructed, cross-level data migration is effectively reduced, and the bottleneck of the PCIe bus is avoided. According to the method, high-throughput video reasoning and TB-level data retrieval tasks on the edge side can be efficiently supported at the same time, and the calculation energy efficiency ratio and the system throughput rate are remarkably increased.

Systems and methods for loop detecting and remediating in a firmware framework are described. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include a controller that instantiates an orchestrator, and multiple devices coupled to the controller, wherein each device instantiates a node. The IHS may also include executable instructions to identify a plurality of communication links between the nodes, determine that at least a subset of the communication links causes a loop to be formed, and communicate with one of the nodes to block one of the communication links with an adjacent node to the one node.

Embodiments of the present disclosure provide an electronic system and an operating method thereof, a computing storage system, and a host. The electronic system includes a host and a computing storage system coupled with the host. The computing storage system includes a controller. The host is configured to send a first command. The controller is configured to receive the first command, and obtain information related to time required by the computing storage system to execute each program in response to the first command. The host is configured to perform program execution related task allocation according to the information related to time required by the computing storage system to execute each program.

Implementations described herein relate to a device identifier composition engine (DICE) 3-layer architecture. In some implementations, a device may include a secure computing environment including a hardware root of trust (HRoT) DICE component. The secure computing environment may include a DICE layer 0 component configured to derive a DICE identity key. The secure computing environment may include a DICE layer 1 component configured to derive a DICE alias key based on the DICE identity key. The secure computing environment may include a controller configured to receive an update to firmware of a component. The controller may be configured to update the firmware of the component based on receiving the update. The controller may be configured to update one or more keys of the component or one or more keys of one or more components above the component in a layer stack.