19 results about "Scalable computing" patented technology

A scalable AI system includes a plurality of slots on a main board, at least one AI module mounted in the slots to perform AI operations, and a main processor that controls the entire system. A user can flexibly scale the overall AI computation performance of the system by adjusting the number of AI modules as needed. Each AI module is equipped with a low-power NPU specialized for AI operations and adopts standard form factors (e.g., M.2, E1.S) to improve economy and scalability. This can solve the problems of high-power consumption and cost, which are limitations of GPU-based systems, and can efficiently support various AI applications.

This application provides a key generation method and a core cryptographic processing system based on a scalable computing data path. The method includes: determining plaintext data, initial key data, counter configuration parameters, and encryption operation parameters based on key generation requirement information; generating counter block data based on the counter configuration parameters, and generating multiple round keys based on the initial key data; performing multi-level folding operations on the counter block data and round keys by the scalable computing data path according to the folding factor and pipeline number under preemptive release logic to generate intermediate key data, and performing synchronization buffer alignment processing on the plaintext data based on the pipeline number to obtain aligned plaintext data; and performing a bitwise XOR operation on the aligned plaintext data based on the intermediate key data to generate target key data. Through the above method, high performance, resource adaptability, accurate synchronization, and continuous reliability are achieved in key generation.

The utility model provides a computing device capable of expanding computing power. The computing device comprises a circuit board, a first computing chip, a second computing chip, a first resistance-capacitance discrete device, a second resistance-capacitance discrete device, a third resistance-capacitance discrete device, a packaging shell, a first wire and a second wire, wherein the first computing chip, the second computing chip, the first resistance-capacitance discrete device, the second resistance-capacitance discrete device and the third resistance-capacitance discrete device are mounted on the circuit board; the first end of the first resistance-capacitance discrete device is connected with the first computing chip, and the second end is connected with the first end of the first wire; the first end of the second resistance-capacitance discrete device is connected with the second computing chip, and the second end is connected with the second end of the second wire; the first end of the third resistance-capacitance discrete device is connected with the first end of the first resistance-capacitance discrete device, and the second end of the third resistance-capacitance discrete device is connected with the first end of the second resistance-capacitance discrete device; the second end of the first wire and the second end of the second wire are used for being connected with an external computing power extension module. According to the computing device capable of expanding the computing power, the computing power expansion module can be connected to expand two signal channels, the signal transmission rate is improved, and signal interference is avoided.

Scalable Computing Device This description relates to a network chip (108) comprising: a programmable infrastructure (201) having a plurality of access points (202); at least one 3D plug communication interface adapted to interface with at least one 110 fragment chip, each 3D plug communication interface being connected to a corresponding access point (202); and a plurality of network-to-network communication interfaces (206, 208, 210, 212), each adapted to interface with another network chip (108). Figure for the abstract: Fig. 2

The invention relates to the technical field of extensible computing, in particular to a subunit system for AI extensible computing power, and the subunit system for the AI extensible computing power comprises a resource prediction and adjustment module, a task optimization scheduling module, a fault detection and recovery module and a micro-service management and recombination module. According to the method, through real-time monitoring and accurate analysis of AI task performance data, future resource demands are allowed to be effectively predicted, instant optimization of resource allocation is realized, and dynamic adaptability not only improves the resource utilization rate, but also prevents performance bottleneck caused by improper resource allocation, and improves the resource utilization rate. By continuously monitoring the running state and quickly identifying and solving potential faults, the stability and reliability of the system are remarkably enhanced, and the micro-service configuration is dynamically adjusted, so that the system can keep the highest efficiency under different service loads, and particularly, the system can keep high performance when a large number of tasks are processed in parallel; therefore, the processing speed and the cost efficiency are remarkably improved.

A system for repeatable and flexible predictive analysis of very large data sets using a distributed computational graph using a domain specific language for pipeline and resource declaration has been developed. Data receipt software receives data from one or more sources. In a declared data pathway, data formalization software formats input data for storage, enrichment, or continued processing. An event analysis server inspects stored data for trends, situations, or knowledge. Aggregated data is passed to event message store and data stream handler software. Transformation pipeline software stores, triggers, executes and monitors declared transformation steps and pipelines to manipulate and act on bulk data and data streams, provides results and enables dynamic model and routine re-training and learning.

A data management system (DMS) may support the backing up of scalable computing objects, such as hierarchical computing objects. For example, the DMS may backup a computing system and facilitate that capture and storage of snapshots of the computing system. The DMS may determine to capture a first snapshot of a computing object within the computing system. The DMS may identify components corresponding to respective portions of the computing object and cause the computing system to generate respective snapshots of the components. That is, the DMS may cause the computing system to generate multiple individual snapshots that together may constitute snapshot of the computing object. The DMS may generate the first snapshot that includes metadata for the snapshots of the components. The metadata may include a first identifier for the first snapshot and respective identifiers for the respective snapshots of the components.

The present application relates to a computing system, a model training method and apparatus, and a product. The computing system relates to a computing unit, and the computing unit comprises: a main board, which is configured with a central processing unit (CPU); and a base board, which is connected to the main board by means of a first communication link, wherein the base board is configured with a plurality of accelerator cards, and the plurality of accelerator cards are connected to each other by means of a second communication link. The main board is used for splitting a training task of a target model into a plurality of concurrent model training tasks and releasing same to the plurality of accelerator cards, and processing training results of the plurality of accelerator cards, so as to obtain a trained target model. The plurality of accelerator cards are used for concurrently executing the respective model training tasks thereof, so as to obtain the training results. The computing system forms an elastically scalable computing system architecture by means of modular base-board design and interconnection, such that the computing power and bandwidth of the computing system can match model training tasks at different parameter scales.

Data processing system for real-time processing and analysis of distributed data in scalable computer networks, comprehensive a plurality of processing units distributed from one another, a data stream acquisition unit for the continuous recording of incoming data streams, a coordinating control unit for assigning data processing tasks to the processing units, as well as an intermediate storage unit for the temporary storage of data and processing results, characterized by the fact that The data processing system has a hardware-implemented synchronization and consistency control unit, which is set up to synchronize time-distributed data streams in real time using deterministic timestamp mechanisms and to physically suppress inconsistent data states before further processing, with the processing units performing parallel analysis processes and the results being merged into a consistent global state space.

The application discloses a kind of based on distributed scheduling's real-time monitoring Spark engine output progress method and platform, belong to information technology field, including: task creation, task execution and progress monitoring and task state and progress monitoring display.The application integrates distributed scheduling and Spark computing engine, adopts MasterServer, WorkerServer and SeaTunnel engine to carry out task execution and progress monitoring, obtains relevant information of output progress from Spark computing engine end in real time and sends back to scheduling system, so that user can see the output progress condition of task in real time from the page of scheduling monitoring conveniently while using reliable and stable performance scheduling ability and high-performance scalable computing ability, improve data reconciliation efficiency, reduce data operation cost.

The technology disclosed in this patent document can be implemented to combine quantum computing and classical digital computing in a scalable computing system based on superconducting qubits using Josephson junctions that exhibit low dissipation long coherence times and can be fabricated with well-developed integrated circuit fabrication techniques. More specifically, the disclosed technology can be implemented by using two radio frequency (RF) superconducting quantum interference device (SQUID) circuits coupled in balance to preserve general symmetry and form a quantum readout circuit for reading and digitizing a superconducting qubit state with improved readout fidelity and sensitivity.

The invention provides a rail transit ATS system based on a cloud native stateless multi-activity architecture, which adopts the technical scheme that a rail transit ATS application is transformed into the stateless multi-activity architecture from stateful active-standby switching, and is characterized in that a client layer is used for separating state data management and service logic of the rail transit ATS system; the stateless service cluster is composed of a plurality of elastic scalable computing nodes and is used for processing service logic and managing temporary data of high-frequency access; the configuration center is used for uniformly managing configuration parameters of all modules of the system and supporting hot update and gray release; the stateless service layer is used for managing the full life cycle of service state data and automatically adjusting the number of computing nodes based on system performance indexes monitored in real time; the message middleware is used for guaranteeing high concurrent processing and real-time message transmission among layers of the system through asynchronous communication; and the persistent storage layer is used for persistently storing business key data of the rail transit ATS system by adopting a multi-type storage engine and providing data backup and disaster recovery support.

A method and system for leveraging an existing issuer user application, associated with a payment network, to create centralized merchant loyalty platform. The centralized merchant loyalty platform consolidates computing resources from different merchant systems to a centralized processing system. The centralized processing system creates a scalable computing platform that allows for loyalty programs associated with a plurality of different merchants to be seamlessly accessed through the existing issuer user application.

The invention provides a key generation method based on a scalable operation data path and a password processing core system, and the method comprises the steps: determining plaintext data, initial key data, counter configuration parameters and encryption operation parameters based on key generation demand information; generating counter block data based on the counter configuration parameters, and generating a plurality of round keys based on the initial key data; based on the counter block data and the round key, a scalable operation data path carries out multi-level folding operation according to a folding factor and a pipeline series under preemptive release logic to generate intermediate key data, and carries out synchronous buffer alignment processing on the plaintext data based on the pipeline series to obtain aligned plaintext data; and based on the intermediate key data, performing bitwise XOR operation on the aligned plaintext data to generate target key data. By means of the method, the effects of high performance, resource adaptation, accurate synchronization, continuity and reliability during key generation are achieved.

The content of the invention can provide an extensible artificial intelligence system. The system includes a plurality of slots on a mainboard, at least one artificial intelligence module mounted in the slots to perform artificial intelligence operations, and a main processor controlling the entire system. A user can adjust the number of the artificial intelligence modules according to needs, and the overall artificial intelligence calculation performance of the system is flexibly expanded. Each artificial intelligence module can be provided with a low-power-consumption neural processing unit specially used for artificial intelligence operation, and standard appearance specifications (such as M.2 and E1. S) are adopted, so that economical efficiency and expandability are improved. This can solve the limitation problems of high power consumption and high cost of a GPU-based system, and efficiently support various artificial intelligence applications.

Systems and methods for processing orders for products customized in a store are disclosed herein. An example system may include a management system, a plurality of micro-services, and an in-store custom order platform. The management system may be associated with a customized store within a store providing a product. The plurality of microservices may include at least a virtual queue system, a commerce platform, an event proxy system, and a user messaging system. The in-store customized order platform may be configured to integrate functions of the management system and the plurality of micro-services to perform operations to process orders of products customized in the store using a self-service terminal application executing on a self-service terminal device.

Methods, systems, and techniques for right-sizing resource requests for applications in a dynamically scalable computing environment. In one aspect, a method comprises monitoring resource usage of at least one computer resource by an application executing on a computer system, and monitoring resource requests for the computer resource(s) associated with the application. The method further comprises determining, for the computer resource(s), a resource usage upper bound associated with the application, testing the resource usage upper bound against at least one threshold, determining, from the testing, a resource request adjustment, and dynamically applying the resource request adjustment to the resource requests for the computer resource(s) associated with the application.

Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in a coplanar array, each microelectronic sub-assembly having a first side and an opposing second side; a first conductive plate coupled to the first sides of the microelectronic sub-assemblies; and a second conductive plate coupled to the second sides of the microelectronic sub-assemblies. The first conductive plate and the second conductive plate comprise sockets corresponding to each of the microelectronic sub-assemblies, and each microelectronic sub-assembly comprises a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die; and a second plurality of IC dies coupled to the first IC die and to the second IC die.

This invention discloses a scalable computing unit, hardware accelerator, and electronic chip. The scalable computing unit includes: local memory, a core controller, and a configurable PE-LUT array for computation and storage. The PE-LUT array includes multiple lookup table columns and a processing unit column for performing computations. Under the control of the core controller, the PE-LUT array can be configured into a computation-intensive mode or a storage-intensive mode. In computation-intensive mode, each lookup table column is used to pre-store the product results of low-precision multiplication operations and accumulation operations. In storage-intensive mode, each lookup table column is used to cache data participating in the computation of the processing unit column. This invention can be used in visual autoregressive models to flexibly expand computing power according to task size and computational load.