33277 results about "Data lines" patented technology

A precharge circuit includes a precharge unit configured to apply a voltage of a precharge voltage terminal to a data line during a precharge operation, and a sensing unit configured to disable the precharge unit by sensing the voltage of the precharge voltage terminal, The precharge circuit may control a precharge operation by sensing a change in the voltage level of the precharge voltage terminal.

The invention provides a display device in which parasitic capacitance associated with data lines and driving circuits is prevented using a bank layer whose primary purpose is to define areas on a substrate in which an organic semiconductor film is formed. When the organic semiconductor film for forming a luminescent element such as an electroluminescent element or an LED is formed is formed in pixel regions (7), the organic semiconductor film is formed in the areas surrounded by the bank layer (bank) formed of a black resist. The bank layer (bank) is also formed between an opposite electrode (op) and data lines (sig) for supplying an image signal to first TFTs (20) and holding capacitors (cap) in the pixel regions (7) thereby preventing parasitic capacitance associated with the data lines (sig).

An ExpressCard contains flash memory. The ExpressCard has an ExpressCard connector that plugs into a host, such as a personal computer, digital camera, or personal digital assistant (PDA). A controller chip on the ExpressCard uses a pair of differential Universal-Serial-Bus (USB) data lines in the connector to communicate with the USB host, or can use PCI Express, Firewire, or other protocols. One or more flash-memory chips on the ExpressCard are controlled by a flash-memory controller in the controller chip. Two or more channels of a flash bus have a shared control bus but separate ready lines. The separate ready lines allow flash-memory chips in the two channels to finish operations at different times.

A drive circuit for a display apparatus includes a gradation voltage generation circuit and a D/A conversion circuit. The gradation voltage generation circuit generates a plurality of different first gradation voltages and a plurality of different second gradation voltages. The D/A conversion circuit drives a light emitting element of a pixel through a data line with a gradation voltage based on one of the first gradation voltages as a first specific gradation voltage in a precharge period and drives the light emitting element of the pixel through the data line with a gradation current based on one of the second gradation voltages as a second specific gradation voltage. The D/A conversion circuit includes a voltage driver to drive the light emitting element, and a current driver to drive the light emitting element.

A light emitting display for compensating for the threshold voltage of transistor or mobility and fully charging a data line. A transistor and first through third switches are formed on a pixel circuit of an organic EL display. The transistor supplies a driving current for emitting an organic EL element (OLED). The first switch diode-connects the transistor. A first storage unit stores a first voltage corresponding to a threshold voltage of the transistor. A second switch transmits a data current in response to a select signal. A second storage unit stores a second voltage corresponding to the data current. A third switch transmits the driving current to the OLED. A third voltage determined by coupling of the first and second storage units is applied to a transistor to supply the driving current to the OLED.

A light-emitting element capable of emitting light having a preferred gradation level depending on display data. During a precharge period, a data driver applies a precharge voltage to a capacitor via a data line. After the application of the precharge voltage, a voltage converter reads a first reference voltage Vref(t1) and a second reference voltage Vref(t2) to generate a compensation voltage based on a difference between the respective reference voltages. Based on the compensation voltage, a voltage calculator compensates an original gradation level voltage Vorg having a value in accordance with display data generated by a gradation level voltage generator. The voltage calculator generates a compensated gradation level voltage Vpix corresponding to a variation amount of an element characteristic for a transistor Tr13 for driving light emission to apply the compensated gradation level voltage Vpix to a data line Ld.

The data line voltage on the data line of the AMOLED sub-pixels is measured while the OLED is being driven by a reference current, in order to determine the age of the OLED in the sub-pixel. The pixel transistor serves as a current source for driving the OLED in the sub-pixel with the reference current. The data line voltage is substantially equal to the forward voltage VF(aged) of the aged OLED being driven at the reference current. The forward voltage VF (un-aged) of a reference (un-aged) OLED sub-pixel also measured at the reference current, and is subtracted from the measured OLED diode forward voltage VF (aged) to obtain their difference ΔVF=VF(aged)−VF(un-aged). ΔVF is an indicator of the age of the OLED in the sub-pixel, and is used as an index to a look-up-table that stores the corresponding aging offset data for generating the incremental pixel current needed to maintain constant luminance in the aged OLED pixel.

A semiconductor device to which active drive current programming is applied, comprising current load cells each having a current load and a current load driving circuit, which are arranged in a matrix, capable of reducing the circuit scale of a current driver with little change made in the structure of the current load driving circuit, and a driving method of the same.

A current load cell (113, 114) includes a current load driving circuit which is provided with a transistor (115) connected in series with a current load (122) between first and second power supplies (109, 110); a capacitance (116) connected between the control terminal of the transistor (115) and the first power supply (109); and switches (117, 118) connected between the control terminal of the transistor (115) and a corresponding data line. The output (101) of a current driver is connected to a plurality of data lines via a selector (123, 124), and the plural data lines connected to one output of the current driver via the selector and at least one of the switches of each of the current load cells corresponding to the respective data lines are drive-controlled in a time division manner during one horizontal period.

A system for providing power over data lines, particularly Ethernet data lines, comprises a network switch including a multiplicity of ports each of which is capable of supplying power in addition to data packets, a controllable power source which is coupled to said ports for supplying power thereto and a processor which is coupled to control the supply of power by the power source. The processor is programmed to guarantee the supply of power to selected ports and to allow or inhibit the supply of power to ports other than the selected ports, having regard to a specified limit on the supply of power by the controllable power source and the total guaranteed power to the selected ports.

A computer memory system provides a double data rate (DDR) memory output while requiring memory chips with only half the frequency limit of the prior art DDR memory chips. The system contains a first memory bank having data lines and a second memory bank having data lines. The first and second memory banks are associated with first and second clock signals, respectively, where the second clock signal is delayed from the first clock signal such that the data lines of the first memory bank are connected to a data bus in synchronism with the first clock signal while the data lines of the second memory bank are connected with the data bus in synchronism with the second clock signal. In one embodiment, a first FET switch connects the data lines of the first memory bank with the data bus and a second FET switch connects the data lines of the second memory bank with the data bus. The second FET switch is connected to the data bus at a time delayed from the beginning after the start of each clock cycle of the second clock signal. As a result, the data bus is never connected to the data lines of both memory banks at the same time, but rather, the data bus is alternately connected with the first memory bank and then the second memory bank.

The invention provides an electro-optical device that stabilizes display quality by performing correction processing corresponding to a plurality of disturbance factors. Specifically, a grayscale characteristic generating unit can generate conversion data having grayscale characteristics obtained by changing the grayscale characteristics of display data that defines the grayscales of pixels with reference to a conversion table whose description contents include correction factors. A data line driving circuit can drive the pixels after correcting the grayscale characteristics of the conversion data by the correction factors using other processing different from the that performed by the grayscale characteristic generating unit.

A high density horizontal merged MOS-bipolar gain memory cell is realized for DRAM operation. The gain cell includes a horizontal MOS transistor having a source region, a drain region, and a floating body region therebetween. The gain cell includes a horizontal bi-polar transistor having an emitter region, a base region and a collector region. The collector region for the horizontal bi-polar transistor serves as the floating body region for the horizontal MOS transistor. A gate opposes the floating body region and is separated therefrom by a gate oxide. The emitter region for the horizontal bi-polar transistor is coupled to a write data line.

An integrated circuit is provided with a scan chain including a scan flip-flop and a dummy block. The dummy block has a clock terminal receiving a clock signal, a scan input terminal connected to a scan data line within the scan chain, and a scan output terminal connected to another scan data line within the scan chain. The dummy block is configured to output data on the scan output terminal in response to input data fed to the scan input terminal, not responsively to the clock signal.