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41405results about How to "High density" patented technology

Targeted and high density drug loaded polymeric materials

Polymeric delivery devices have been developed which combine high loading/high density of molecules to be delivered with the option of targeting. As used herein, “high density” refers to microparticles having a high density of ligands or coupling agents, which is in the range of 1000-10,000,000, more preferably between 10,000 and 1,000,000 ligands per square micron of microparticle surface area. A general method for incorporating molecules into the surface of biocompatible polymers using materials with an HLB of less than 10, more preferably less than 5, such as fatty acids, has been developed. Because of its ease, generality and flexibility, this method has widespread utility in modifying the surface of polymeric materials for applications in drug delivery and tissue engineering, as well other other fields. Targeted polymeric microparticles have also been developed which encapsulate therapeutic compounds such as drugs, cellular materials or components, and antigens, and have targeting ligands directly bound to the microparticle surface. Preferred applications include use in tissue engineering matrices, wound dressings, bone repair or regeneration materials, and other applications where the microparticles are retained at the site of application or implantation. Another preferred application is in the use of microparticles to deliver anti-proliferative agents to the lining of blood vessels following angioplasty, transplantation or bypass surgery to prevent or decrease restenosis, and in cancer therapy. In still another application, the microparticles are used to treat or prevent macular degeneration when administered to the eye, where agents such as complement inhibitors are administered.
Owner:YALE UNIV

Method for fabricating programmable memory array structures incorporating series-connected transistor strings

A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer. By interleaving the NAND strings on each memory level and using two shared bias nodes per block, very little additional overhead is required for the switch devices at each end of the NAND strings. The NAND strings on different memory levels are preferably connected together by way of vertical stacked vias, each preferably connecting to more than one memory level. Each memory level may be produced with less than three masks per level.
Owner:SANDISK TECH LLC
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