306 results about "Phase-change memory" patented technology

The invention discloses a data center power distribution cabinet energy-saving heat dissipation method based on heat flow optimization, and the method comprises the steps: arranging a multi-source sensing unit for collecting monitoring data, and constructing a heat flow map containing the relation between nodes and edges; establishing a self-evolution heat flow neural map model based on the heat flow map, and dynamically updating an edge weight to output a prediction result; determining a temperature difference and an air flow direction according to a prediction result, and setting a phase change memory air guide composite layer structure; the central controller receives the prediction and air flow state and generates a heat flow control instruction linkage control parameter; an energy bond scheduling mechanism is established, a credit account is set, and cross-cabinet cooling capacity borrowing and repayment operation is executed; and updating the model by using feedback and deviation data, and periodically executing retraining and parameter optimization. According to the invention, intelligent heat dissipation and energy-saving optimization of the data center power distribution cabinet are realized through self-evolution heat flow neural map modeling and a synergistic effect of the phase change memory air guide composite layer and an energy bond scheduling mechanism.

The embodiment of the utility model relates to a phase change memory unit and a memory device. A phase change memory cell includes a heater having first and second lateral sides opposed to each other along a first axis, and top and bottom sides opposed to each other along a second axis orthogonal to the first axis; and a memory region made of a phase change material layer, the memory region being electrically and thermally coupled to the top side of the heater; and a conductive element having a resistive property, the conductive element extending parallel to the first axis away from the first lateral side; wherein the conductive element is positioned adjacent the first lateral side and in contact with the memory region. According to the embodiment of the invention, a window or a gap between the set / reset resistance values of the two states is advantageously increased.

Systems and methods for intelligent data sanitization employing PCM and AI / ML are provided. The idea uses AI / ML to detect specific facts that needs sanitization rather than full properties in incoming records. Data sanitization is optimized using this focused method, saving computational resources. To properly manage changing data volumes, PCM shifts between Logical 0 and Logical 1 states. Logical 0 processes smaller volumes with high resistance and low conductivity, while Logical 1 processes large volumes with low resistance and high conductivity. The AI / ML module organizes and directs data to maximize resource and processing efficiency. The PCM processes data in-memory and directly overwrites, eliminating erasure. AI / ML and PCM integrate to sanitize data quickly, efficiently, and securely, improving system performance and data integrity without a central repository. The system dynamically adjusts to changing data patterns, protecting and optimizing data.

The technology described herein is directed towards a design and implementation of a unit cell for a reconfigurable intelligent surface / reflectarray by incorporating reconfigurability within a phase-delay element of the unit cell. Reconfigurability is directly incorporated into the unit cell via a variable length phase delay line element and PCM-based (e.g., mmWave) phase shifter that determines the unit cell's phase shift by changing the length of the phase delay line element. One implementation is directed to a monolithic integration of the element using chalcogenide materials as switch elements with pulsed actuation to switch among different available lengths that determine the length of the phase delay line element, resulting in a significant reduction in power consumption, area saving, and digital reconfigurability.

A bottom electrode is deposited on a substrate. A dielectric layer is deposited on the bottom electrode. One or more structures are patterned within the dielectric layer. A liner layer is deposited on top of the dielectric layer and the bottom electrode. A selectivity promotion layer is deposited on top of the liner layer. The selectivity promotion layer is etched to expose a top surface of the dielectric layer and a portion of the bottom electrode. A phase change memory material layer is deposited within a void of the one or more structures between the selectivity promotion layer.

A device structure includes a first series connection of a first phase change memory (PCM) switch and a second PCM switch. The first PCM switch includes a first heater line, a first PCM line, and a first contact electrode and a second contact electrode located on the first heater line. The second PCM switch includes a second heater line, a second PCM line, and a third contact electrode and a fourth contact electrode located on the second heater line. The second contact electrode is electrically connected to the third contact electrode. The fourth contact electrode is electrically grounded. One of the first contact electrode and the second contact electrode includes an radio-frequency (RF) signal input port. Another of the first contact electrode and the second contact electrode comprises an RF signal output port. The device structure may function as a combination PCM switch that decreases noise level during signal transmission.

A semiconductor device includes a PCM stack that includes bottom electrode liner over a lower heater. The bottom electrode liner has a top-down view plus (+) geometry with a ‘horizontal’ portion being orthogonal to a ‘vertical’ portion. An airgap is formed within the PCM stack in an area located adjacent and between the ‘horizontal’ portion and the ‘vertical’ portion. The airgap has a substantially smaller dielectric constant than the surrounding PCM stack material(s). Therefore, the airgap may effectively reduce the amount of current that leaks from the PCM stack when flowing from the bottom electrode liner to a top contact or top electrode. Further, the airgap may allow for expansion of the surrounding PCM stack material(s) that may result from the heating of the PCM stack.

A phase-change memory structure with improved sidewall heating and the fabrication thereof may be presented. Phase-change materials can be switched between a first structural state, in which the material is in a generally amorphous solid phase, and a second structural state, in which the material is in a generally crystalline solid phase, in the active region of the cell. A sidewall heater may be presented herein in which the upper portion passes through a double-layer dielectric to form contact with a phase-change material layer, and the lower portion of the sidewall heater has conductive layers in contact with the lower electrode. The width of the sidewall heater may be an inverted T-shape to reduce the current required to reset the phase-change material.

A phase change memory includes a phase change structure. There is a heater coupled to a first surface of the phase change structure. A first electrode is coupled to a second surface of the phase change structure. A second electrode coupled to a second surface of the heater. A third electrode is connected to a first lateral end of the phase change structure and a fourth electrode connected to a second lateral end of the phase change structure.

A semiconductor device is provided. The semiconductor device includes a heater formed on a substrate; a hardmask formed on the heater; a phase change material layer formed on a first side of the heater and the hardmask; a first electrode formed on the phase change material layer on the first side; and a second electrode formed on the substrate on a second side of the heater and the hardmask.

The application discloses an operating method of a phase change memory, a control circuit and the phase change memory, and relates to the technical field of memories. The method comprises the following steps: decoding an operation command to obtain a target operation address; determining a storage area where a phase change memory unit to be operated is located according to the target operation address; acquiring a timing adjustment parameter corresponding to the storage area where the phase change memory to be operated is located; adjusting a key stage timing of the phase change memory unit to be operated according to the timing adjustment parameter to obtain a target time length; and providing required energy for executing a target operation of the phase change memory unit to be operated by making the key stage timing last for the target time length. In this way, the required energy can be provided for the phase change memory unit to be operated located in different storage areas according to the timing adjustment parameter, so that the power consumption of the phase change memory for executing the target operation is reduced, and the cycle performance of the phase change memory is significantly improved.

The present invention discloses a phase change junction film, a phase change memory and a preparation method thereof. The phase change junction film comprises a structural phase change layer and a structural stabilization layer alternately stacked; wherein the structural phase change layer is a cubic phase M x Sb2Te3 layer, the structural stabilizing layer is a hexagonal Ti y Te 1‑y layer, M is one of scandium and yttrium. The present invention is based on the cubic phase of M x Sb2Te3 structure phase change layer and hexagonal Ti y Te 1‑y The phase-shifting heterojunction film, formed by alternating stacking of structurally stable layers, offers faster operating speeds, lower operating power consumption, and improved fatigue cycle life. It also possesses the performance advantages common to heterojunction materials, namely, extremely low resistance drift and resistance fluctuation under weaker atomic diffusion conditions.

The invention provides a three-dimensional vertical structure phase change memory and a preparation method thereof. The preparation method comprises the following steps: forming a word line structure in a stacking structure on a substrate; symmetrical sunken structures are formed in the electrode layer of the word line structure; forming a gate layer in the recessed structure; filling an insulating medium, and forming a through hole structure in the insulating medium at two sides of the word line structure; sequentially forming an insertion layer and a phase change layer on the outer side of the gating layer; and forming a top electrode layer in the through hole structure. Aiming at the bottleneck of a laminated hole etching process, through hole processing is carried out on an insulating medium, so that the etching difficulty is reduced; the insulating medium forms a thermal isolation groove at the periphery of the storage unit to block a thermal diffusion path, so that the thermal crosstalk of adjacent units is reduced, and the data storage reliability is improved; the storage density is doubled by optimizing the position of the bit line circuit and the efficient arrangement of the multiple layers of storage units. According to the method, an efficient solution is provided for high-density nonvolatile storage requirements in the fields of artificial intelligence, cloud computing and the like.

The present invention is to provide a phase change memory unit and preparation method thereof. The phase change memory comprises a bottom electrode, a phase change cell, a heating electrode and a top electrode on a substrate from bottom to top. The phase change cell is a column vertically connected to the bottom electrode, which sequentially comprise a columnar phase change material layer, a hollow columnar heat dissipation layer and a hollow columnar switch layer from inside to outside. The top electrode, the heating electrode and the phase change material layer are connected sequentially from top to bottom, the switch layer is connected to the bottom electrode. The present invention adopts a heat dissipation layer wrapping around the phase change material layer to make the current density and the heat distribution more concentrated, thus to keep the effective phase transition region unchanged, reduce the volume of the effective phase transition region and the power consumption, and increase the device reliability.

In an embodiment, a non-volatile memory device is proposed. The device includes a plurality of local pull-up stages distributed along a group of memory portions in a memory array. Each local pull-up stage includes, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type. The local pull-up transistors of each local pull-up are configured to locally decouple the corresponding wordline from a node at a first reference potential in response to a wordline that extends through the group of memory portions being selected, and locally couple the corresponding wordline to the node at the first reference potential in response to all the wordlines that extend through the group of memory portions being deselected to restore locally a deselection voltage on a wordline previously selected.

The invention relates to programming for non-volatile memory. According to an embodiment, a circuit for generating an adaptive set pulse current for a phase change memory (PCM) cell is disclosed. The circuit includes: a first current digital-to-analog converter (IDAC) and a second IDAC, each IDAC configured to generate a bias current having a programmable curve, the programmable curve including: a constant current phase at a predefined set current; a first ramp down phase from a predefined set current to a minimum off current; a second ramp down phase from a minimum off current to zero; and a zero current phase, wherein the constant current phase of each IDAC begins in response to another IDAC starting a second ramp-down phase; and a programming circuit configured to select one of the bias currents from the first IDAC and the second IDAC and generate an adaptive set pulse current.

The invention relates to a phase change material, a phase change memory and a preparation method thereof, the phase change material comprises an In2Te3 component, a Sb2Te3 component and a doping element M, the chemical general formula of the phase change material is (In2Te3) x (Sb2Te3) yMz, x, y and z satisfy 0 < = x < = 5 and 15 < = ytt, and the doping element M is a doping element M. 20, 0 < = zlt; 10, and 5x + 5y + z = 100; the doping element M comprises one or more of B, C, N and O. By adjusting the proportion of Sb2Te3 to In2Te3 and the doping content of the light element, the phase change material with better thermal stability and higher data retention can be obtained, and the phase change memory based on the phase change material has nanosecond-level high speed, high thermal stability and high reliability.

A memory device having: a first local digit line configured to extend in a first direction; a second local digit line configured in parallel with the first local digit line; a plurality of unit cells stacked in the first direction and sandwiched between the first local digit line and the second local digit line, each respective unit cell among the plurality of unit cells configured to connect the first local digit line to the second local digit line in a second direction that is perpendicular to the first direction, the respective unit cell having a transistor and a memory cell; and a plurality of wordlines configured to extend in a third direction that is perpendicular to the first direction and the second direction, where transistors in the plurality of unit cells are connected to the wordlines.

The application discloses a self-adaptive control method of a phase change memory, the phase change memory, a storage medium and electronic equipment, and belongs to the technical field of semiconductors. The method comprises the following steps: writing a full 0 data mode into a storage unit within a minimum write-to-read time interval; performing a read operation on the storage unit to which the full 0 data mode is written, and obtaining detection data; obtaining at least one storage array bit error rate index according to the detection data; and based on a comparison result of the bit error rate index and a preset threshold, selecting a target voltage gear from a preconfigured voltage gear set to adjust the read voltage of the storage unit to a corresponding read voltage gear. The application realizes self-adaptive and accurate calibration of the read voltage through fast detection of the full 0 mode under the minimum write-to-read interval and global evaluation of the bit error rate, thereby guaranteeing the test efficiency and significantly improving the reliability and durability of the memory.

A programmable integrated circuit device able to be selectively programmed to perform one or more logic functions includes multiple configurable logic blocks (“LBs”), routing fabric, and a nonvolatile memory (“NVM”). While the configurable LBs are able to be selectively programmed to perform one or more logic functions, the routing fabric selectively routes information between the configurable LBs and input / output ports based on a routing configuration signals. The NVM, such as magnetoresistive random access memory (“MRAM”), phase-change memory, or ferroelectric RAM (“FeRAM”), is flexibly organized to contain a configuration NVM storage and a user NVM storage, wherein the user NVM storage is a word addressable memory capable of facilitating random memory access.

A method for modifying a conductance or resistance value within a resistance distribution range defined around a median resistance distribution value of at least one phase change memory cell, the method including: a determination step in which a melting current and an amorphous phase current are determined; a quenching step in which a first pulse with a steep falling ramp having a quenching effect is applied to the at least one phase change memory cell; a crystallization step in which a second pulse with a progressively falling ramp is applied to at least one phase change memory cell.

A process is provided to trim PCRAM cells to have consistent programming curves. Initial programming curves of PCRAM cells are measured. A target programming curve is set up for the PCRAM cells. Each PCRAM cell is then modulated individually to meet the target programming curve.

The present disclosure provides a phase-change memory and a method for manufacturing the same. The method includes: providing a semiconductor structure comprising: a first memory cell; an isolation layer disposed between adjacent first memory cells; a first conductive line disposed on one side of the first memory cell, wherein a surface of the first conductive line protrudes from a surface of the isolation layer, and adjacent first conductive lines and the isolation layer jointly form a first groove; forming a first dielectric layer covering the sidewalls and bottom of the first groove and covering the first conductive line, thereby forming a second groove in the first groove; forming a second dielectric layer covering the sidewalls and bottom of the second groove and covering the first dielectric layer; and performing a planarization process to expose the first conductive line; wherein, during the planarization process, the removal rate of the second dielectric layer is lower than the removal rate of the first dielectric layer.

The application discloses a three-dimensional phase change memory write circuit with temperature compensation and a write operation method. In view of the influence of temperature on threshold voltage of a storage unit and on off-state current, temperature compensation is performed through word line power supply and bit line power supply respectively. When the influence of temperature on leakage current is compensated, the influence of off-state current on different positions of the storage unit is considered. Therefore, when the influence of temperature on off-state current is compensated, the storage unit is divided into a plurality of storage blocks according to positions, and output voltages are divided into a plurality of groups. Different output voltages correspond to different storage blocks, so that different degrees of temperature compensation are performed on the storage unit at different positions. According to the application, the temperature compensation of off-state current reduces the failure rate of write operation which increases with the increase of temperature; and the temperature compensation of threshold voltage reduces unnecessary power waste and the probability of error half-voltage opening during write operation caused by the increase of temperature.

The invention discloses a phase change memory which can be used in the field of semiconductors, the phase change memory comprises phase change memory units arranged in an array, and each phase change memory unit comprises a phase change memory material and a spacing layer; the spacer layer covers the side wall of the phase change storage material; the spacing layer comprises a first spacing layer and a second spacing layer; the phase change storage material, the first spacing layer and the second spacing layer are sequentially arranged from inside to outside, the first spacing layer comprises an oxide interlayer and a nitride layer, and the second spacing layer is an oxide layer; the thickness of the oxide interlayer in the first spacer layer is smaller than that of the second spacer layer. Therefore, the oxide interlayer is added in the first spacing layer, the oxide interlayer and the nitride layer jointly form a sandwich-like N-O-N structure, and the oxide interlayer is added to serve as a heat barrier layer, so that the thermal boundary resistance can be effectively increased, and the efficiency of transferring heat generated by a phase change storage material along a signal line of the phase change memory is reduced; therefore, the thermal crosstalk among the phase change memory units in the phase change memory is improved.

The invention relates to a self-induced crystallization phase change storage unit and a preparation method thereof, the self-induced crystallization phase change storage unit comprises a phase change storage medium layer, the phase change storage medium layer is a multi-layer structure formed by phase change material layers and self-induced crystallization InyTe100-y material layers which are vertically stacked, periodically and alternately grown, and y is more than or equal to 20 and less than or equal to 80. The self-induced crystallization phase change memory cell has the characteristics of rapid data writing capability and long service life, can realize high-low resistance difference of more than three orders of magnitude, effectively improves the multi-resistance state memory stability, and can solve the problems of high power consumption, short service life, slow phase change speed and the like of a phase change memory in the prior art.

The invention discloses a phase change memory and a preparation method thereof, a micro-control unit, a controller and a vehicle, relates to the technical field of semiconductors, and aims to solve the problem that the yield of the phase change memory is low due to high manufacturing difficulty caused by more thin film layers of the phase change memory. The phase change memory comprises at least one phase change memory unit; the phase change storage unit comprises a first electrode, a second electrode and a gating storage layer, the gate storage layer is arranged between the first electrode and the second electrode; the materials of the gate storage layer comprise a chalcogenide phase change material and a doping element doped in the chalcogenide phase change material; the doping element is at least configured to enable the crystallization temperature of the material of the gate storage layer to be higher than the crystallization temperature of the chalcogenide phase change material; wherein the mass ratio range of the doped element in the material of the gate storage layer is 30%-48%.

A phase-change memory device is disclosed. The phase-change memory device includes a heater electrode having an uppermost surface. The phase-change memory device further includes a phase-change layer having a lowermost surface in direct contact with the uppermost surface of the heater electrode at a first location. The phase-change memory device further includes an outer electrode contact arm in direct contact with the phase-change layer at a second location that is spaced apart from the first location such that current flows through the phase-change layer from the first location to the second location. The outer electrode contact arm has a lowermost surface that is coplanar with the lowermost surface of the phase-change layer.

The invention relates to a phase change memory write circuit and method based on an SPI (Serial Peripheral Interface), and the circuit comprises an N-bit address register, a 2M-bit input data register, an N-K-bit phase change memory write address register, a K-bit write address decoder, a 2K-bit write mask register and a 2M + K-bit write data register. According to the invention, at most 2K data received by the SPI interface is merged and then written into the phase change memory at one time, so that the write-in delay of the phase change memory is utilized to the maximum extent, and the data transmission rate of the phase change memory based on the SPI interface is improved.