200 results about "Phase-change memory" patented technology

The invention discloses a data center power distribution cabinet energy-saving heat dissipation method based on heat flow optimization, and the method comprises the steps: arranging a multi-source sensing unit for collecting monitoring data, and constructing a heat flow map containing the relation between nodes and edges; establishing a self-evolution heat flow neural map model based on the heat flow map, and dynamically updating an edge weight to output a prediction result; determining a temperature difference and an air flow direction according to a prediction result, and setting a phase change memory air guide composite layer structure; the central controller receives the prediction and air flow state and generates a heat flow control instruction linkage control parameter; an energy bond scheduling mechanism is established, a credit account is set, and cross-cabinet cooling capacity borrowing and repayment operation is executed; and updating the model by using feedback and deviation data, and periodically executing retraining and parameter optimization. According to the invention, intelligent heat dissipation and energy-saving optimization of the data center power distribution cabinet are realized through self-evolution heat flow neural map modeling and a synergistic effect of the phase change memory air guide composite layer and an energy bond scheduling mechanism.

Systems and methods for intelligent data sanitization employing PCM and AI / ML are provided. The idea uses AI / ML to detect specific facts that needs sanitization rather than full properties in incoming records. Data sanitization is optimized using this focused method, saving computational resources. To properly manage changing data volumes, PCM shifts between Logical 0 and Logical 1 states. Logical 0 processes smaller volumes with high resistance and low conductivity, while Logical 1 processes large volumes with low resistance and high conductivity. The AI / ML module organizes and directs data to maximize resource and processing efficiency. The PCM processes data in-memory and directly overwrites, eliminating erasure. AI / ML and PCM integrate to sanitize data quickly, efficiently, and securely, improving system performance and data integrity without a central repository. The system dynamically adjusts to changing data patterns, protecting and optimizing data.

A bottom electrode is deposited on a substrate. A dielectric layer is deposited on the bottom electrode. One or more structures are patterned within the dielectric layer. A liner layer is deposited on top of the dielectric layer and the bottom electrode. A selectivity promotion layer is deposited on top of the liner layer. The selectivity promotion layer is etched to expose a top surface of the dielectric layer and a portion of the bottom electrode. A phase change memory material layer is deposited within a void of the one or more structures between the selectivity promotion layer.

A device structure includes a first series connection of a first phase change memory (PCM) switch and a second PCM switch. The first PCM switch includes a first heater line, a first PCM line, and a first contact electrode and a second contact electrode located on the first heater line. The second PCM switch includes a second heater line, a second PCM line, and a third contact electrode and a fourth contact electrode located on the second heater line. The second contact electrode is electrically connected to the third contact electrode. The fourth contact electrode is electrically grounded. One of the first contact electrode and the second contact electrode includes an radio-frequency (RF) signal input port. Another of the first contact electrode and the second contact electrode comprises an RF signal output port. The device structure may function as a combination PCM switch that decreases noise level during signal transmission.

A phase change memory includes a phase change structure. There is a heater coupled to a first surface of the phase change structure. A first electrode is coupled to a second surface of the phase change structure. A second electrode coupled to a second surface of the heater. A third electrode is connected to a first lateral end of the phase change structure and a fourth electrode connected to a second lateral end of the phase change structure.

A semiconductor device is provided. The semiconductor device includes a heater formed on a substrate; a hardmask formed on the heater; a phase change material layer formed on a first side of the heater and the hardmask; a first electrode formed on the phase change material layer on the first side; and a second electrode formed on the substrate on a second side of the heater and the hardmask.

The application discloses an operating method of a phase change memory, a control circuit and the phase change memory, and relates to the technical field of memories. The method comprises the following steps: decoding an operation command to obtain a target operation address; determining a storage area where a phase change memory unit to be operated is located according to the target operation address; acquiring a timing adjustment parameter corresponding to the storage area where the phase change memory to be operated is located; adjusting a key stage timing of the phase change memory unit to be operated according to the timing adjustment parameter to obtain a target time length; and providing required energy for executing a target operation of the phase change memory unit to be operated by making the key stage timing last for the target time length. In this way, the required energy can be provided for the phase change memory unit to be operated located in different storage areas according to the timing adjustment parameter, so that the power consumption of the phase change memory for executing the target operation is reduced, and the cycle performance of the phase change memory is significantly improved.

The present invention discloses a phase change junction film, a phase change memory and a preparation method thereof. The phase change junction film comprises a structural phase change layer and a structural stabilization layer alternately stacked; wherein the structural phase change layer is a cubic phase M x Sb2Te3 layer, the structural stabilizing layer is a hexagonal Ti y Te 1‑y layer, M is one of scandium and yttrium. The present invention is based on the cubic phase of M x Sb2Te3 structure phase change layer and hexagonal Ti y Te 1‑y The phase-shifting heterojunction film, formed by alternating stacking of structurally stable layers, offers faster operating speeds, lower operating power consumption, and improved fatigue cycle life. It also possesses the performance advantages common to heterojunction materials, namely, extremely low resistance drift and resistance fluctuation under weaker atomic diffusion conditions.

The invention provides a three-dimensional vertical structure phase change memory and a preparation method thereof. The preparation method comprises the following steps: forming a word line structure in a stacking structure on a substrate; symmetrical sunken structures are formed in the electrode layer of the word line structure; forming a gate layer in the recessed structure; filling an insulating medium, and forming a through hole structure in the insulating medium at two sides of the word line structure; sequentially forming an insertion layer and a phase change layer on the outer side of the gating layer; and forming a top electrode layer in the through hole structure. Aiming at the bottleneck of a laminated hole etching process, through hole processing is carried out on an insulating medium, so that the etching difficulty is reduced; the insulating medium forms a thermal isolation groove at the periphery of the storage unit to block a thermal diffusion path, so that the thermal crosstalk of adjacent units is reduced, and the data storage reliability is improved; the storage density is doubled by optimizing the position of the bit line circuit and the efficient arrangement of the multiple layers of storage units. According to the method, an efficient solution is provided for high-density nonvolatile storage requirements in the fields of artificial intelligence, cloud computing and the like.

The present invention is to provide a phase change memory unit and preparation method thereof. The phase change memory comprises a bottom electrode, a phase change cell, a heating electrode and a top electrode on a substrate from bottom to top. The phase change cell is a column vertically connected to the bottom electrode, which sequentially comprise a columnar phase change material layer, a hollow columnar heat dissipation layer and a hollow columnar switch layer from inside to outside. The top electrode, the heating electrode and the phase change material layer are connected sequentially from top to bottom, the switch layer is connected to the bottom electrode. The present invention adopts a heat dissipation layer wrapping around the phase change material layer to make the current density and the heat distribution more concentrated, thus to keep the effective phase transition region unchanged, reduce the volume of the effective phase transition region and the power consumption, and increase the device reliability.

In an embodiment, a non-volatile memory device is proposed. The device includes a plurality of local pull-up stages distributed along a group of memory portions in a memory array. Each local pull-up stage includes, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type. The local pull-up transistors of each local pull-up are configured to locally decouple the corresponding wordline from a node at a first reference potential in response to a wordline that extends through the group of memory portions being selected, and locally couple the corresponding wordline to the node at the first reference potential in response to all the wordlines that extend through the group of memory portions being deselected to restore locally a deselection voltage on a wordline previously selected.

The invention relates to programming for non-volatile memory. According to an embodiment, a circuit for generating an adaptive set pulse current for a phase change memory (PCM) cell is disclosed. The circuit includes: a first current digital-to-analog converter (IDAC) and a second IDAC, each IDAC configured to generate a bias current having a programmable curve, the programmable curve including: a constant current phase at a predefined set current; a first ramp down phase from a predefined set current to a minimum off current; a second ramp down phase from a minimum off current to zero; and a zero current phase, wherein the constant current phase of each IDAC begins in response to another IDAC starting a second ramp-down phase; and a programming circuit configured to select one of the bias currents from the first IDAC and the second IDAC and generate an adaptive set pulse current.

The invention relates to a phase change material, a phase change memory and a preparation method thereof, the phase change material comprises an In2Te3 component, a Sb2Te3 component and a doping element M, the chemical general formula of the phase change material is (In2Te3) x (Sb2Te3) yMz, x, y and z satisfy 0 < = x < = 5 and 15 < = ytt, and the doping element M is a doping element M. 20, 0 < = zlt; 10, and 5x + 5y + z = 100; the doping element M comprises one or more of B, C, N and O. By adjusting the proportion of Sb2Te3 to In2Te3 and the doping content of the light element, the phase change material with better thermal stability and higher data retention can be obtained, and the phase change memory based on the phase change material has nanosecond-level high speed, high thermal stability and high reliability.

The application discloses a self-adaptive control method of a phase change memory, the phase change memory, a storage medium and electronic equipment, and belongs to the technical field of semiconductors. The method comprises the following steps: writing a full 0 data mode into a storage unit within a minimum write-to-read time interval; performing a read operation on the storage unit to which the full 0 data mode is written, and obtaining detection data; obtaining at least one storage array bit error rate index according to the detection data; and based on a comparison result of the bit error rate index and a preset threshold, selecting a target voltage gear from a preconfigured voltage gear set to adjust the read voltage of the storage unit to a corresponding read voltage gear. The application realizes self-adaptive and accurate calibration of the read voltage through fast detection of the full 0 mode under the minimum write-to-read interval and global evaluation of the bit error rate, thereby guaranteeing the test efficiency and significantly improving the reliability and durability of the memory.

A method for modifying a conductance or resistance value within a resistance distribution range defined around a median resistance distribution value of at least one phase change memory cell, the method including: a determination step in which a melting current and an amorphous phase current are determined; a quenching step in which a first pulse with a steep falling ramp having a quenching effect is applied to the at least one phase change memory cell; a crystallization step in which a second pulse with a progressively falling ramp is applied to at least one phase change memory cell.

The present disclosure provides a phase-change memory and a method for manufacturing the same. The method includes: providing a semiconductor structure comprising: a first memory cell; an isolation layer disposed between adjacent first memory cells; a first conductive line disposed on one side of the first memory cell, wherein a surface of the first conductive line protrudes from a surface of the isolation layer, and adjacent first conductive lines and the isolation layer jointly form a first groove; forming a first dielectric layer covering the sidewalls and bottom of the first groove and covering the first conductive line, thereby forming a second groove in the first groove; forming a second dielectric layer covering the sidewalls and bottom of the second groove and covering the first dielectric layer; and performing a planarization process to expose the first conductive line; wherein, during the planarization process, the removal rate of the second dielectric layer is lower than the removal rate of the first dielectric layer.

The application discloses a three-dimensional phase change memory write circuit with temperature compensation and a write operation method. In view of the influence of temperature on threshold voltage of a storage unit and on off-state current, temperature compensation is performed through word line power supply and bit line power supply respectively. When the influence of temperature on leakage current is compensated, the influence of off-state current on different positions of the storage unit is considered. Therefore, when the influence of temperature on off-state current is compensated, the storage unit is divided into a plurality of storage blocks according to positions, and output voltages are divided into a plurality of groups. Different output voltages correspond to different storage blocks, so that different degrees of temperature compensation are performed on the storage unit at different positions. According to the application, the temperature compensation of off-state current reduces the failure rate of write operation which increases with the increase of temperature; and the temperature compensation of threshold voltage reduces unnecessary power waste and the probability of error half-voltage opening during write operation caused by the increase of temperature.

The invention relates to a self-induced crystallization phase change storage unit and a preparation method thereof, the self-induced crystallization phase change storage unit comprises a phase change storage medium layer, the phase change storage medium layer is a multi-layer structure formed by phase change material layers and self-induced crystallization InyTe100-y material layers which are vertically stacked, periodically and alternately grown, and y is more than or equal to 20 and less than or equal to 80. The self-induced crystallization phase change memory cell has the characteristics of rapid data writing capability and long service life, can realize high-low resistance difference of more than three orders of magnitude, effectively improves the multi-resistance state memory stability, and can solve the problems of high power consumption, short service life, slow phase change speed and the like of a phase change memory in the prior art.

The technology described herein is directed towards a design and implementation of a unit cell for a reconfigurable intelligent surface / reflectarray by incorporating reconfigurability within a phase-delay element of the unit cell. Reconfigurability is directly incorporated into the unit cell via a variable length phase delay line element and PCM-based (e.g., mmWave) phase shifter that determines the unit cell's phase shift by changing the length of the phase delay line element. One implementation is directed to a monolithic integration of the element using chalcogenide materials as switch elements with pulsed actuation to switch among different available lengths that determine the length of the phase delay line element, resulting in a significant reduction in power consumption, area saving, and digital reconfigurability.

This disclosure provides a controller, address management method, and system for a phase-change memory (PCM). The method includes: determining the address mapping mode of the PCM; if it is a static mapping mode, mapping a first source address to a first destination address based on a preset mapping table; if it is a dynamic mapping mode, matching a corresponding address mapping rule according to a dynamic scenario, and mapping a second source address to a second destination address based on the address mapping rule; if it is a hybrid mapping mode, mapping a third source address to a third destination address based on a preset mapping table, controlling the PCM to perform read operations based on the third destination address; and matching a corresponding address mapping rule according to a dynamic scenario, mapping a fourth source address to a fourth destination address based on the address mapping rule, and controlling the PCM to perform write operations based on the fourth destination address. This application can reduce the read latency of the PCM, improve the write performance and media lifetime of the PCM, and achieve a balance between read and write performance.

Confined Phase-Change Memory The present invention proposes a confined memory cell (1) in which the active layer (13), formed within the cavity (12) of the dielectric material (14) where it is confined, is such that the active layer lines the lateral wall and the bottom of the cavity while delimiting an internal space without active material. Such a structure allows the advantages of a confined structure, namely a lower programming current intensity than for non-confined structures, while also enabling the memory cell to achieve multiple programming levels. Figure to be published with the abbreviation: Figure 1

Systems and methods for intelligent data sanitization employing PCM and AI / ML are provided. The idea uses AI / ML to detect specific facts that needs sanitization rather than full properties in incoming records. Data sanitization is optimized using this focused method, saving computational resources. To properly manage changing data volumes, PCM shifts between Logical 0 and Logical 1 states. Logical 0 processes smaller volumes with high resistance and low conductivity, while Logical 1 processes large volumes with low resistance and high conductivity. The AI / ML module organizes and directs data to maximize resource and processing efficiency. The PCM processes data in-memory and directly overwrites, eliminating erasure. AI / ML and PCM integrate to sanitize data quickly, efficiently, and securely, improving system performance and data integrity without a central repository. The system dynamically adjusts to changing data patterns, protecting and optimizing data.

The invention provides an optical waveguide and heterojunction two-dimensional material integrated nonvolatile storage structure and an application method, and relates to the technical field of photoelectron integration. A heterojunction two-dimensional material layer is arranged in an evanescent field area of an optical waveguide layer, so that when an electric field pulse is applied to the heterojunction two-dimensional material layer through a positive electrode layer and a negative electrode layer, the heterojunction two-dimensional material layer is not subjected to evanescent field pulse; the heterojunction two-dimensional material layer can generate various non-volatile heterojunction polarization states, so that the optical constant and the optical state of the non-volatile storage structure are changed, the optical state can be stored by utilizing the non-volatility, and the optical memory function is realized. Even under the condition of power failure, the stored optical state cannot be lost, and ultra-low static power consumption can be realized. The overturning of the polarization state of the heterojunction is realized by the overturning of the heterojunction domain, so that the power consumption of the nonvolatile storage structure is far lower than the heat power consumption required by a phase change memory or a thermo-optic device.

EEPROM emulation is provided in a phase-change memory of a circuit integrating a microprocessor. A granularity for writing into lines of the phase-change memory is defined according to a size of data packets to be written. A first error correction code calculated by a program executed by said microprocessor is associated with each data packet. Several data packets and their associated first error correction codes are then stored in a same line of the phase-change memory data packet.

The embodiment of the present application provides a kind of phase change material and its manufacturing method, phase change memory and its manufacturing method, wherein the phase change material includes: first doped element, second doped element and phase change bulk material;Wherein, the first doped element and the second doped element can form chemical bond with the element in the phase change bulk material;The bond energy of the chemical bond formed is greater than the bond energy of the chemical bond between elements in the phase change bulk material;The first doped element and the second doped element belong to the elements of different groups in periodic table.The embodiment of the present application can improve the amorphous thermal stability and data retention of phase change material, so as to improve the electrical performance of phase change memory.

An electrical device includes a first electrode in series with a second electrode. A phase change memory (PCM) is in series with the second electrode. A variable electrical element is in series with the phase change memory.

The present disclosure discloses a phase-change material layer structure, a method for preparing the same, and a phase-change memory. The phase-change material layer structure is applied to a phase-change memory and includes: a first material layer made of GeTe; a second material layer made of at least Ga and Sb; and alternating stacks of the first and second material layers.

The application provides a phase change film, a film preparation method and a phase change memory. x (Sb2Te3) 1‑x wherein x is the percentage of TiTe2, and 0

A reconfigurable inference platform implemented in a system-in-package configuration is provided. The system in the reconfigurable inference platform includes a processor chip, a first memory chip storing a set of executable models for inference engines, and a second memory chip storing weights for a selected executable model. The processor chip has a running processor core, an accelerator core, and a processor-memory interface exposed on a chip-to-chip bonding surface. The first memory chip is, for example, a three-dimensional NAND flash memory. The second memory chip can include a non-volatile random access memory, such as a phase change memory. A direct vertical connection structure, such as a via-to-via connection structure, is provided between the processor chip and the second memory chip.