116 results about "Phase-change memory" patented technology

Systems and methods for intelligent data sanitization employing PCM and AI / ML are provided. The idea uses AI / ML to detect specific facts that needs sanitization rather than full properties in incoming records. Data sanitization is optimized using this focused method, saving computational resources. To properly manage changing data volumes, PCM shifts between Logical 0 and Logical 1 states. Logical 0 processes smaller volumes with high resistance and low conductivity, while Logical 1 processes large volumes with low resistance and high conductivity. The AI / ML module organizes and directs data to maximize resource and processing efficiency. The PCM processes data in-memory and directly overwrites, eliminating erasure. AI / ML and PCM integrate to sanitize data quickly, efficiently, and securely, improving system performance and data integrity without a central repository. The system dynamically adjusts to changing data patterns, protecting and optimizing data.

A semiconductor device is provided. The semiconductor device includes a heater formed on a substrate; a hardmask formed on the heater; a phase change material layer formed on a first side of the heater and the hardmask; a first electrode formed on the phase change material layer on the first side; and a second electrode formed on the substrate on a second side of the heater and the hardmask.

The application discloses an operating method of a phase change memory, a control circuit and the phase change memory, and relates to the technical field of memories. The method comprises the following steps: decoding an operation command to obtain a target operation address; determining a storage area where a phase change memory unit to be operated is located according to the target operation address; acquiring a timing adjustment parameter corresponding to the storage area where the phase change memory to be operated is located; adjusting a key stage timing of the phase change memory unit to be operated according to the timing adjustment parameter to obtain a target time length; and providing required energy for executing a target operation of the phase change memory unit to be operated by making the key stage timing last for the target time length. In this way, the required energy can be provided for the phase change memory unit to be operated located in different storage areas according to the timing adjustment parameter, so that the power consumption of the phase change memory for executing the target operation is reduced, and the cycle performance of the phase change memory is significantly improved.

The invention relates to programming for non-volatile memory. According to an embodiment, a circuit for generating an adaptive set pulse current for a phase change memory (PCM) cell is disclosed. The circuit includes: a first current digital-to-analog converter (IDAC) and a second IDAC, each IDAC configured to generate a bias current having a programmable curve, the programmable curve including: a constant current phase at a predefined set current; a first ramp down phase from a predefined set current to a minimum off current; a second ramp down phase from a minimum off current to zero; and a zero current phase, wherein the constant current phase of each IDAC begins in response to another IDAC starting a second ramp-down phase; and a programming circuit configured to select one of the bias currents from the first IDAC and the second IDAC and generate an adaptive set pulse current.

The application discloses a self-adaptive control method of a phase change memory, the phase change memory, a storage medium and electronic equipment, and belongs to the technical field of semiconductors. The method comprises the following steps: writing a full 0 data mode into a storage unit within a minimum write-to-read time interval; performing a read operation on the storage unit to which the full 0 data mode is written, and obtaining detection data; obtaining at least one storage array bit error rate index according to the detection data; and based on a comparison result of the bit error rate index and a preset threshold, selecting a target voltage gear from a preconfigured voltage gear set to adjust the read voltage of the storage unit to a corresponding read voltage gear. The application realizes self-adaptive and accurate calibration of the read voltage through fast detection of the full 0 mode under the minimum write-to-read interval and global evaluation of the bit error rate, thereby guaranteeing the test efficiency and significantly improving the reliability and durability of the memory.

A method for modifying a conductance or resistance value within a resistance distribution range defined around a median resistance distribution value of at least one phase change memory cell, the method including: a determination step in which a melting current and an amorphous phase current are determined; a quenching step in which a first pulse with a steep falling ramp having a quenching effect is applied to the at least one phase change memory cell; a crystallization step in which a second pulse with a progressively falling ramp is applied to at least one phase change memory cell.

The application discloses a three-dimensional phase change memory write circuit with temperature compensation and a write operation method. In view of the influence of temperature on threshold voltage of a storage unit and on off-state current, temperature compensation is performed through word line power supply and bit line power supply respectively. When the influence of temperature on leakage current is compensated, the influence of off-state current on different positions of the storage unit is considered. Therefore, when the influence of temperature on off-state current is compensated, the storage unit is divided into a plurality of storage blocks according to positions, and output voltages are divided into a plurality of groups. Different output voltages correspond to different storage blocks, so that different degrees of temperature compensation are performed on the storage unit at different positions. According to the application, the temperature compensation of off-state current reduces the failure rate of write operation which increases with the increase of temperature; and the temperature compensation of threshold voltage reduces unnecessary power waste and the probability of error half-voltage opening during write operation caused by the increase of temperature.

The invention relates to a self-induced crystallization phase change storage unit and a preparation method thereof, the self-induced crystallization phase change storage unit comprises a phase change storage medium layer, the phase change storage medium layer is a multi-layer structure formed by phase change material layers and self-induced crystallization InyTe100-y material layers which are vertically stacked, periodically and alternately grown, and y is more than or equal to 20 and less than or equal to 80. The self-induced crystallization phase change memory cell has the characteristics of rapid data writing capability and long service life, can realize high-low resistance difference of more than three orders of magnitude, effectively improves the multi-resistance state memory stability, and can solve the problems of high power consumption, short service life, slow phase change speed and the like of a phase change memory in the prior art.

The technology described herein is directed towards a design and implementation of a unit cell for a reconfigurable intelligent surface / reflectarray by incorporating reconfigurability within a phase-delay element of the unit cell. Reconfigurability is directly incorporated into the unit cell via a variable length phase delay line element and PCM-based (e.g., mmWave) phase shifter that determines the unit cell's phase shift by changing the length of the phase delay line element. One implementation is directed to a monolithic integration of the element using chalcogenide materials as switch elements with pulsed actuation to switch among different available lengths that determine the length of the phase delay line element, resulting in a significant reduction in power consumption, area saving, and digital reconfigurability.

This disclosure provides a controller, address management method, and system for a phase-change memory (PCM). The method includes: determining the address mapping mode of the PCM; if it is a static mapping mode, mapping a first source address to a first destination address based on a preset mapping table; if it is a dynamic mapping mode, matching a corresponding address mapping rule according to a dynamic scenario, and mapping a second source address to a second destination address based on the address mapping rule; if it is a hybrid mapping mode, mapping a third source address to a third destination address based on a preset mapping table, controlling the PCM to perform read operations based on the third destination address; and matching a corresponding address mapping rule according to a dynamic scenario, mapping a fourth source address to a fourth destination address based on the address mapping rule, and controlling the PCM to perform write operations based on the fourth destination address. This application can reduce the read latency of the PCM, improve the write performance and media lifetime of the PCM, and achieve a balance between read and write performance.

Confined Phase-Change Memory The present invention proposes a confined memory cell (1) in which the active layer (13), formed within the cavity (12) of the dielectric material (14) where it is confined, is such that the active layer lines the lateral wall and the bottom of the cavity while delimiting an internal space without active material. Such a structure allows the advantages of a confined structure, namely a lower programming current intensity than for non-confined structures, while also enabling the memory cell to achieve multiple programming levels. Figure to be published with the abbreviation: Figure 1

The invention provides an optical waveguide and heterojunction two-dimensional material integrated nonvolatile storage structure and an application method, and relates to the technical field of photoelectron integration. A heterojunction two-dimensional material layer is arranged in an evanescent field area of an optical waveguide layer, so that when an electric field pulse is applied to the heterojunction two-dimensional material layer through a positive electrode layer and a negative electrode layer, the heterojunction two-dimensional material layer is not subjected to evanescent field pulse; the heterojunction two-dimensional material layer can generate various non-volatile heterojunction polarization states, so that the optical constant and the optical state of the non-volatile storage structure are changed, the optical state can be stored by utilizing the non-volatility, and the optical memory function is realized. Even under the condition of power failure, the stored optical state cannot be lost, and ultra-low static power consumption can be realized. The overturning of the polarization state of the heterojunction is realized by the overturning of the heterojunction domain, so that the power consumption of the nonvolatile storage structure is far lower than the heat power consumption required by a phase change memory or a thermo-optic device.

The embodiment of the present application provides a kind of phase change material and its manufacturing method, phase change memory and its manufacturing method, wherein the phase change material includes: first doped element, second doped element and phase change bulk material;Wherein, the first doped element and the second doped element can form chemical bond with the element in the phase change bulk material;The bond energy of the chemical bond formed is greater than the bond energy of the chemical bond between elements in the phase change bulk material;The first doped element and the second doped element belong to the elements of different groups in periodic table.The embodiment of the present application can improve the amorphous thermal stability and data retention of phase change material, so as to improve the electrical performance of phase change memory.

An electrical device includes a first electrode in series with a second electrode. A phase change memory (PCM) is in series with the second electrode. A variable electrical element is in series with the phase change memory.

A reconfigurable inference platform implemented in a system-in-package configuration is provided. The system in the reconfigurable inference platform includes a processor chip, a first memory chip storing a set of executable models for inference engines, and a second memory chip storing weights for a selected executable model. The processor chip has a running processor core, an accelerator core, and a processor-memory interface exposed on a chip-to-chip bonding surface. The first memory chip is, for example, a three-dimensional NAND flash memory. The second memory chip can include a non-volatile random access memory, such as a phase change memory. A direct vertical connection structure, such as a via-to-via connection structure, is provided between the processor chip and the second memory chip.

A memory device that includes both a heat diffusion facilitating layer and a heat diffusion inhibiting layer is disclosed. A phase change memory device according to an embodiment disclosed herein includes: a first phase change layer; a first heat diffusion facilitating layer disposed to be adjacent to one surface of the first phase change layer; and a first heat diffusion inhibiting layer disposed to be adjacent to the other surface of the first phase change layer.

An example phase change memory, as well as an electronic device comprising an example phase change memory, include a plurality of phase change memory cells. Each of the plurality of phase change memory cells includes a first electrode, a phase change body, and a second electrode, which are sequentially arranged in a first direction. The phase change body has a first end face facing the first electrode and a second end face facing the second electrode. The phase change body further includes a convergence portion, and the convergence portion is located between the first end face and the second end face, where a sectional area of the convergence portion in a direction perpendicular to the first direction is relatively smaller than an area of the first end face and an area of the second end face. A preparation method for a phase change memory is also provided.

The application provides an electrothermal analysis method and system for a phase change memory, comprising: proportionally dividing a phase change layer of the phase change memory into a plurality of sub-regions with the same volume; determining a doping proportion of the doping material, and calculating the number of sub-regions occupied by the doping material according to the doping proportion; randomly selecting a corresponding number of sub-regions to fill the doping material according to the calculated number of sub-regions, and filling the remaining sub-regions with a phase change material; determining electrothermal parameters of the doping material, the phase change material, an upper electrode, a lower electrode and an insulating and heat-insulating layer; determining boundary conditions and current parameters of the phase change memory; the boundary conditions are thermal boundary conditions, and the current parameters are RESET / SET current pulses; and combining the above-mentioned electrothermal parameters, current parameters and boundary conditions to perform thermal simulation analysis on the phase change memory, so as to determine the temperature field distribution inside the phase change memory after the phase change memory receives the RESET / SET current pulses, and further analyze the phase change region inside the phase change memory and the RESET / SET power consumption.

The invention relates to an optimized single-ended EPCM read method adapted to temperature variations. Readout circuitry for an embedded phase change memory (ePCM) cell is disclosed. The circuitry includes a temperature sensor that outputs a signal indicating whether the sensed temperature is above or below a threshold. The microcontroller generates a read signal and a correction signal, wherein the correction signal is based on the temperature signal. A phase generation circuit receives these signals and generates a pre-charge signal and an evaluation signal based on the correction signal. A sense amplifier controlled by the pre-charge signal and the evaluation signal compares the ePCM cell current to a reference current to generate an output. The circuitry dynamically adjusts its timing parameters in response to temperature changes to provide reliable read operations across varying conditions.

To implement SET writing operation on a selected memory cell included in a memory array.SOLUTION: In a device 700, a selection logic 722-1 of a circuit configuration 720 selects one memory cell from among memory cells of a memory array to implement SET writing operation via an interface 703, and a SET logic 722-2 applies a current to a terminal of the memory cell to control a change of a phase change material included in the memory cell from a non-crystalline state to a crystalline state. In a logic and / or function executed by the circuit configuration 720, the change from the non-crystalline state to the crystalline state includes: a nucleation stage for generating crystal seeds; and a crystal growth stage for promoting crystal growth after the nucleation stage to set a crystalline state and turn the memory cell into a SET logic state.SELECTED DRAWING: Figure 7

The invention relates to the technical field of phase change memory testing, in particular to a phase change memory array fault testing circuit which comprises a storage unit read-write circuit, a double-path current real-time monitoring circuit and a parallel reference read detection circuit. Wherein the storage unit read-write circuit is connected with the 1T1R phase change storage unit, the double-path current real-time monitoring circuit is connected with a bit line path and a source line path, synchronous sampling and dynamic comparison are carried out on bit internal line current and source internal line current in the write-in operation period, and corresponding judgment signals are output; and the parallel reference reading detection circuit is connected with the output end of the double-path current real-time monitoring circuit, copies the detected current to a plurality of branches and compares the detected current with the multi-stage reference current in parallel. According to the phase change memory array fault test circuit provided by the invention, online current monitoring and rapid logic judgment can be realized in an array level test process, and the capability of detecting resistance type defects such as short circuit, bridging and open circuit and composite anomalies caused by the resistance type defects is improved.

Readout circuitry for embedded phase change memory (ePCM) cells is disclosed. The circuitry includes a temperature sensor that outputs a signal indicating whether the sensed temperature is above or below a threshold. A microcontroller generates read and trim signals, with the trim signal based on the temperature signal. A phase generation circuit receives these signals and generates precharge and evaluation signals based on the trim signal. A sense amplifier, controlled by the precharge and evaluation signals, compares the ePCM cell current to a reference current to generate an output. The circuitry dynamically adjusts its timing parameters in response to temperature changes, providing for reliable read operations across varying conditions.

The present disclosure provides a semiconductor device. The semiconductor device includes a bottom electrode, a top electrode, and a phase-change memory structure. The bottom electrode includes graphene. The top electrode is disposed on the bottom electrode. The phase-change memory structure is disposed between the top electrode and the bottom electrode.

A memory device including a first electrode and a second electrode are over a first dielectric layer. A heater layer is laterally between the first electrode and the second electrode. A thermal transfer layer is over the heater layer. The thermal transfer layer includes a first tapered region between the first electrode and the heater layer. A phase-change layer is over the thermal transfer layer and extends laterally from a top surface of the first electrode to a top surface of the second electrode. The phase-change layer includes a first lateral region over the first electrode and a first step region directly over the first tapered region of the thermal transfer layer. The phase-change layer has a first thickness along the first step region and a second thickness along the first lateral region. A difference between the first thickness and the second thickness is less than 20%.

The application discloses a forming method of a phase change memory and the phase change memory. An insulating layer is formed on a first contact, the insulating layer is etched to form a groove, and a first conductive line connected with the first contact is formed in the groove. Therefore, the forming method of the first conductive line does not need to etch tungsten, so that the morphology of the first conductive line can be improved, the width consistency and the hole phenomenon of the first conductive line can be improved, the over-etching of the first contact can be improved to reduce the damage of the first contact, and the resistance can be improved.

Embodiments of the present disclosure relate to a method of performing write operations in a phase change memory, a corresponding device and a computer program product. A writable memory portion of the PCM is coupled to a non-volatile memory storing information indicating whether a latest write operation to the writable memory portion uses a first set of current pulses or a second set of current pulses (the second set of current pulses uses a lower current value than the first set of current pulses). Transitioning from the first group to the second group in response to a command to perform a write operation on the writable memory portion using a pulse of the second group of current pulses, and if the stored information indicates that the latest write operation uses a pulse of the first group of current pulses, applying a blanking current pulse to the cells of the writable memory portion in the reset state; a write operation is performed on the writable memory portion using the second set of current pulses, and the non-volatile memory portion is updated to indicate that the latest write operation is performed using the second set of current pulses.

This application provides a phase-change memory and its operation method. The phase-change memory includes a memory array and peripheral circuitry coupled to the memory array. The memory array includes multiple first address lines, multiple second address lines, and multiple phase-change memory cells. Each phase-change memory cell includes a gating element and a phase-change memory element. The peripheral circuitry is configured to: during a read operation, apply a first voltage to a selected first address line, turn on a switching circuit, and apply a second voltage to a selected second address line and a data line; the first voltage is greater than the second voltage; wherein, at a first moment, the gating element is turned on; at a second moment, the gating element is turned off; the second moment is later than the first moment; and at a third moment, the first voltage is reduced; the third moment is between the second moment and the fourth moment.

Provided are a method for etching a phase change material of a phase change memory device and a semiconductor device formed according to the method. A temperature of the phase change memory device is lowered to a target temperature. A plasma etching process is applied to pattern the phase change material in response to cooling the temperature of the phase change memory device to the target temperature.

A phase change memory element including at least one phase change material layer, and a heater conductor, wherein at least a portion of the heater conductor is circumferentially surrounded by the at least one phase change material layer. The phase change memory element is symmetrical. The phase change memory element can include a top electrode circumferentially surrounding and connected to the at least one phase change material layer, and a bottom electrode in contact with the heater conductor. The phase change memory element can include at least one resistive liner in contact with the at least one phase change material layer.