376 results about "Phase-change memory" patented technology

The invention discloses a phase change memory and electronic equipment, the phase change memory comprises a comparator, a second switch, a third switch, a memory circuit, a selected digital line, a first switch and an unselected digital line, the memory circuit, the selected digital line, the first switch and the unselected digital line are connected in sequence, and the reference voltage of the unselected digital line is set in a reading operation through the first switch and the third switch; the reference voltage is in positive correlation with the second negative voltage, the second negative voltage is smaller than the first negative voltage, and compared with the reference voltage which is in positive correlation with the first negative voltage, the lower reference voltage can be generated, so that the overshoot current flowing through the memory cell at the opening moment is reduced, and the reading interference suffered by the memory cell is reduced.

An in-memory computation (IMC) system includes an in-memory computation circuit formed by a first phase change memory (PCM) array configured to store the computational weights for an in-memory computation operation. A data storage circuit is formed by a second PCM array configured to store backup data for the computational weights for the in-memory computation operation. The first PCM array includes PCM cells made of a phase change material provided by a first GST alloy, and the second PCM array includes PCM cells made of a phase change material provided by a second GST alloy different from the first GST alloy. A control circuit operates to read the backup data from the second PCM array and write to the first PCM array to refresh the computational weights for the in-memory computation operation from the backup data.

The invention discloses a data center power distribution cabinet energy-saving heat dissipation method based on heat flow optimization, and the method comprises the steps: arranging a multi-source sensing unit for collecting monitoring data, and constructing a heat flow map containing the relation between nodes and edges; establishing a self-evolution heat flow neural map model based on the heat flow map, and dynamically updating an edge weight to output a prediction result; determining a temperature difference and an air flow direction according to a prediction result, and setting a phase change memory air guide composite layer structure; the central controller receives the prediction and air flow state and generates a heat flow control instruction linkage control parameter; an energy bond scheduling mechanism is established, a credit account is set, and cross-cabinet cooling capacity borrowing and repayment operation is executed; and updating the model by using feedback and deviation data, and periodically executing retraining and parameter optimization. According to the invention, intelligent heat dissipation and energy-saving optimization of the data center power distribution cabinet are realized through self-evolution heat flow neural map modeling and a synergistic effect of the phase change memory air guide composite layer and an energy bond scheduling mechanism.

A system in package platform includes a processor chip having a runtime processor core, an accelerator core and a processor-memory interface exposed on a chip-to-chip bonding surface, a first memory chip such as 3D NAND flash memory storing a collection of executable models of inference engines, and a second memory chip storing weights of a selected executable model. The second memory chip can comprise a nonvolatile, random access memory, such as phase change memory. Direct vertical connections such as via-to-via connections, are provided between the processor chip and the second memory chip.

The embodiment of the utility model relates to a phase change memory unit and a memory device. A phase change memory cell includes a heater having first and second lateral sides opposed to each other along a first axis, and top and bottom sides opposed to each other along a second axis orthogonal to the first axis; and a memory region made of a phase change material layer, the memory region being electrically and thermally coupled to the top side of the heater; and a conductive element having a resistive property, the conductive element extending parallel to the first axis away from the first lateral side; wherein the conductive element is positioned adjacent the first lateral side and in contact with the memory region. According to the embodiment of the invention, a window or a gap between the set / reset resistance values of the two states is advantageously increased.

Systems and methods for intelligent data sanitization employing PCM and AI / ML are provided. The idea uses AI / ML to detect specific facts that needs sanitization rather than full properties in incoming records. Data sanitization is optimized using this focused method, saving computational resources. To properly manage changing data volumes, PCM shifts between Logical 0 and Logical 1 states. Logical 0 processes smaller volumes with high resistance and low conductivity, while Logical 1 processes large volumes with low resistance and high conductivity. The AI / ML module organizes and directs data to maximize resource and processing efficiency. The PCM processes data in-memory and directly overwrites, eliminating erasure. AI / ML and PCM integrate to sanitize data quickly, efficiently, and securely, improving system performance and data integrity without a central repository. The system dynamically adjusts to changing data patterns, protecting and optimizing data.

The technology described herein is directed towards a design and implementation of a unit cell for a reconfigurable intelligent surface / reflectarray by incorporating reconfigurability within a phase-delay element of the unit cell. Reconfigurability is directly incorporated into the unit cell via a variable length phase delay line element and PCM-based (e.g., mmWave) phase shifter that determines the unit cell's phase shift by changing the length of the phase delay line element. One implementation is directed to a monolithic integration of the element using chalcogenide materials as switch elements with pulsed actuation to switch among different available lengths that determine the length of the phase delay line element, resulting in a significant reduction in power consumption, area saving, and digital reconfigurability.

A bottom electrode is deposited on a substrate. A dielectric layer is deposited on the bottom electrode. One or more structures are patterned within the dielectric layer. A liner layer is deposited on top of the dielectric layer and the bottom electrode. A selectivity promotion layer is deposited on top of the liner layer. The selectivity promotion layer is etched to expose a top surface of the dielectric layer and a portion of the bottom electrode. A phase change memory material layer is deposited within a void of the one or more structures between the selectivity promotion layer.

A device structure includes a first series connection of a first phase change memory (PCM) switch and a second PCM switch. The first PCM switch includes a first heater line, a first PCM line, and a first contact electrode and a second contact electrode located on the first heater line. The second PCM switch includes a second heater line, a second PCM line, and a third contact electrode and a fourth contact electrode located on the second heater line. The second contact electrode is electrically connected to the third contact electrode. The fourth contact electrode is electrically grounded. One of the first contact electrode and the second contact electrode includes an radio-frequency (RF) signal input port. Another of the first contact electrode and the second contact electrode comprises an RF signal output port. The device structure may function as a combination PCM switch that decreases noise level during signal transmission.

A semiconductor device includes a PCM stack that includes bottom electrode liner over a lower heater. The bottom electrode liner has a top-down view plus (+) geometry with a ‘horizontal’ portion being orthogonal to a ‘vertical’ portion. An airgap is formed within the PCM stack in an area located adjacent and between the ‘horizontal’ portion and the ‘vertical’ portion. The airgap has a substantially smaller dielectric constant than the surrounding PCM stack material(s). Therefore, the airgap may effectively reduce the amount of current that leaks from the PCM stack when flowing from the bottom electrode liner to a top contact or top electrode. Further, the airgap may allow for expansion of the surrounding PCM stack material(s) that may result from the heating of the PCM stack.

Embodiments of present invention provide a phase change memory (PCM) device. The PCM device includes a first PCM cell with the first PCM cell including an L-shaped phase change element, the L-shaped phase change element having a horizontal portion and a vertical portion on top of the horizontal portion; a selector underneath the horizontal portion of the L-shaped phase change element; a top electrode in contact with a top surface of the vertical portion of the L-shaped phase change element; and a bottom electrode in contact with the selector; and a second PCM cell. A method of manufacturing the PCM device is also provided.

The invention discloses a fault test method and system for a phase change memory array, and relates to the technical field of integrated circuits, and the method comprises the steps: analyzing a plurality of fault modes in the phase change memory array, and extracting the necessary and sufficient conditions of each fault mode, the necessary and sufficient conditions being the failure characteristics of a certain unit or a plurality of units in the array; deducing a test sequence suitable for the fault test of the phase change memory array according to the necessary and sufficient conditions; constructing a fault detection circuit based on the test sequence, and embedding the fault detection circuit into a phase change memory array; and performing fault testing on the phase change memory array by using the fault detection circuit, and judging the health state of each memory unit in the array to complete the fault testing. The algorithm provided by the invention can detect the special fault of the PCRAM, which cannot be identified by a traditional detection circuit, so that the fault coverage rate is greatly improved.

A phase-change memory structure with improved sidewall heating and the fabrication thereof may be presented. Phase-change materials can be switched between a first structural state, in which the material is in a generally amorphous solid phase, and a second structural state, in which the material is in a generally crystalline solid phase, in the active region of the cell. A sidewall heater may be presented herein in which the upper portion passes through a double-layer dielectric to form contact with a phase-change material layer, and the lower portion of the sidewall heater has conductive layers in contact with the lower electrode. The width of the sidewall heater may be an inverted T-shape to reduce the current required to reset the phase-change material.

A phase change memory includes a phase change structure. There is a heater coupled to a first surface of the phase change structure. A first electrode is coupled to a second surface of the phase change structure. A second electrode coupled to a second surface of the heater. A third electrode is connected to a first lateral end of the phase change structure and a fourth electrode connected to a second lateral end of the phase change structure.

A semiconductor device is provided. The semiconductor device includes a heater formed on a substrate; a hardmask formed on the heater; a phase change material layer formed on a first side of the heater and the hardmask; a first electrode formed on the phase change material layer on the first side; and a second electrode formed on the substrate on a second side of the heater and the hardmask.

The switch device comprises a lower electrode, an upper electrode, and a switch material layer disposed between the lower electrode and the upper electrode. When the switch device is in an on state, the switch material layer is in a liquid state and has a bandgap of 0; when the switch device is in an off state, the switch material layer is in a crystalline state, and a Schottky barrier is formed between the switch material layer and the upper electrode, as well as between the switch material layer and the lower electrode. The switch device employs the crystalline-liquid-crystalline phase change mechanism of the switch material, and can drive memory units, such as phase change memory units, resistive memory units, ferroelectric memory units, magnetic memory units, and the like, thereby enabling high-density three-dimensional information storage.

A phase change memory structure with improved sidewall heater and formation thereof may be presented. Phase change materials are capable of being switched between a first structural state in which the

The present application provides a phase change memory and a preparation method thereof, the method comprising: forming a gating layer and a phase change memory layer connected in series with the gating layer; the gating layer comprises a first sublayer and a second sublayer; wherein the element of the first sublayer is selected from at least one gating layer element in a first type of element set, and the element of the second sublayer is selected from at least one gating layer element in a second type of element set; the mobility of each gating layer element in the first type of element set is less than the mobility of each gating layer element in the second type of element set. In the method provided by the present application, a gating layer comprising a first sublayer and a second sublayer is formed, so that the mobility of each element in the first sublayer is less than the mobility of each element in the second sublayer, and the interface effect between the first sublayer and the second sublayer is utilized to alleviate the local phase separation or even crystallization caused by material diffusion, so as to improve the high temperature stability of the gating layer, thereby improving the high temperature stability of the phase change memory.

The application discloses an operating method of a phase change memory, a control circuit and the phase change memory, and relates to the technical field of memories. The method comprises the following steps: decoding an operation command to obtain a target operation address; determining a storage area where a phase change memory unit to be operated is located according to the target operation address; acquiring a timing adjustment parameter corresponding to the storage area where the phase change memory to be operated is located; adjusting a key stage timing of the phase change memory unit to be operated according to the timing adjustment parameter to obtain a target time length; and providing required energy for executing a target operation of the phase change memory unit to be operated by making the key stage timing last for the target time length. In this way, the required energy can be provided for the phase change memory unit to be operated located in different storage areas according to the timing adjustment parameter, so that the power consumption of the phase change memory for executing the target operation is reduced, and the cycle performance of the phase change memory is significantly improved.

The invention relates to a high-storage-density medium buffer layer sandwich structure phase change storage thin film material and a preparation method and application thereof.The phase change storage thin film material is of a sandwich structure, and the phase change storage thin film material is prepared by alternately arranging two different phase change layer materials and medium layer materials through a magnetron sputtering method; and a similar superlattice structure is formed. The structural general formula of the multilayer film structure is [M (a nm)-A (b nm)-N (c nm)] n, M and N are two different phase change layer materials, and A is a dielectric layer material.Compared with the prior art, the multilayer film structure has the advantages that the dielectric layer with the nanoscale thickness is introduced into the multilayer film structure, the interface stress between adjacent film layers can be effectively relieved, the lattice mismatch phenomenon is reduced, and therefore the stability of the multilayer film structure is remarkably improved. In addition, the introduction of the dielectric layer can also regulate and control the electrical characteristics of the thin film in the phase change process, enhance the distinction degree of multi-stage resistance states, further improve the storage density, and solve the problem that the storage capacity of a traditional phase change memory is limited.

The present invention discloses a phase change junction film, a phase change memory and a preparation method thereof. The phase change junction film comprises a structural phase change layer and a structural stabilization layer alternately stacked; wherein the structural phase change layer is a cubic phase M x Sb2Te3 layer, the structural stabilizing layer is a hexagonal Ti y Te 1‑y layer, M is one of scandium and yttrium. The present invention is based on the cubic phase of M x Sb2Te3 structure phase change layer and hexagonal Ti y Te 1‑y The phase-shifting heterojunction film, formed by alternating stacking of structurally stable layers, offers faster operating speeds, lower operating power consumption, and improved fatigue cycle life. It also possesses the performance advantages common to heterojunction materials, namely, extremely low resistance drift and resistance fluctuation under weaker atomic diffusion conditions.

The invention discloses a photoelectric temperature-time coupled phase change memory programming device and method. The device comprises a pump laser system, an electrical test system, a cold and hot temperature control system and control monitoring software, the pump laser system, the electrical test system, the cold and hot temperature control system and the control monitoring software operate cooperatively, under the unified coordination of the control monitoring software, the pump laser system emits laser pulses with specified parameters, the laser pulses cooperate with the displacement platform, gradual crystallization or non-crystallization switching is achieved in a specified laser irradiation area and path, and the laser pulses are emitted by the displacement platform. The cold and hot temperature control system reaches a specified environment temperature at a certain heating rate, and the electrical test system records the electrical response of the phase change memory device in a specified test duration in real time, so that the light-operated electrical test programming operation of the phase change memory device in a specific environment is realized. According to the invention, quantitative control of the product proportion of the crystal to the amorphous in the SET and RESET step-by-step switching process is realized through a light-operated electric measurement mode, and linear continuous and symmetrical change of the switching resistance value is obtained.

The invention provides a three-dimensional vertical structure phase change memory and a preparation method thereof. The preparation method comprises the following steps: forming a word line structure in a stacking structure on a substrate; symmetrical sunken structures are formed in the electrode layer of the word line structure; forming a gate layer in the recessed structure; filling an insulating medium, and forming a through hole structure in the insulating medium at two sides of the word line structure; sequentially forming an insertion layer and a phase change layer on the outer side of the gating layer; and forming a top electrode layer in the through hole structure. Aiming at the bottleneck of a laminated hole etching process, through hole processing is carried out on an insulating medium, so that the etching difficulty is reduced; the insulating medium forms a thermal isolation groove at the periphery of the storage unit to block a thermal diffusion path, so that the thermal crosstalk of adjacent units is reduced, and the data storage reliability is improved; the storage density is doubled by optimizing the position of the bit line circuit and the efficient arrangement of the multiple layers of storage units. According to the method, an efficient solution is provided for high-density nonvolatile storage requirements in the fields of artificial intelligence, cloud computing and the like.

The present invention is to provide a phase change memory unit and preparation method thereof. The phase change memory comprises a bottom electrode, a phase change cell, a heating electrode and a top electrode on a substrate from bottom to top. The phase change cell is a column vertically connected to the bottom electrode, which sequentially comprise a columnar phase change material layer, a hollow columnar heat dissipation layer and a hollow columnar switch layer from inside to outside. The top electrode, the heating electrode and the phase change material layer are connected sequentially from top to bottom, the switch layer is connected to the bottom electrode. The present invention adopts a heat dissipation layer wrapping around the phase change material layer to make the current density and the heat distribution more concentrated, thus to keep the effective phase transition region unchanged, reduce the volume of the effective phase transition region and the power consumption, and increase the device reliability.

In an embodiment, a non-volatile memory device is proposed. The device includes a plurality of local pull-up stages distributed along a group of memory portions in a memory array. Each local pull-up stage includes, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type. The local pull-up transistors of each local pull-up are configured to locally decouple the corresponding wordline from a node at a first reference potential in response to a wordline that extends through the group of memory portions being selected, and locally couple the corresponding wordline to the node at the first reference potential in response to all the wordlines that extend through the group of memory portions being deselected to restore locally a deselection voltage on a wordline previously selected.

The invention relates to programming for non-volatile memory. According to an embodiment, a circuit for generating an adaptive set pulse current for a phase change memory (PCM) cell is disclosed. The circuit includes: a first current digital-to-analog converter (IDAC) and a second IDAC, each IDAC configured to generate a bias current having a programmable curve, the programmable curve including: a constant current phase at a predefined set current; a first ramp down phase from a predefined set current to a minimum off current; a second ramp down phase from a minimum off current to zero; and a zero current phase, wherein the constant current phase of each IDAC begins in response to another IDAC starting a second ramp-down phase; and a programming circuit configured to select one of the bias currents from the first IDAC and the second IDAC and generate an adaptive set pulse current.

The invention relates to a phase change material, a phase change memory and a preparation method thereof, the phase change material comprises an In2Te3 component, a Sb2Te3 component and a doping element M, the chemical general formula of the phase change material is (In2Te3) x (Sb2Te3) yMz, x, y and z satisfy 0 < = x < = 5 and 15 < = ytt, and the doping element M is a doping element M. 20, 0 < = zlt; 10, and 5x + 5y + z = 100; the doping element M comprises one or more of B, C, N and O. By adjusting the proportion of Sb2Te3 to In2Te3 and the doping content of the light element, the phase change material with better thermal stability and higher data retention can be obtained, and the phase change memory based on the phase change material has nanosecond-level high speed, high thermal stability and high reliability.

A memory device having: a first local digit line configured to extend in a first direction; a second local digit line configured in parallel with the first local digit line; a plurality of unit cells stacked in the first direction and sandwiched between the first local digit line and the second local digit line, each respective unit cell among the plurality of unit cells configured to connect the first local digit line to the second local digit line in a second direction that is perpendicular to the first direction, the respective unit cell having a transistor and a memory cell; and a plurality of wordlines configured to extend in a third direction that is perpendicular to the first direction and the second direction, where transistors in the plurality of unit cells are connected to the wordlines.

The application discloses a self-adaptive control method of a phase change memory, the phase change memory, a storage medium and electronic equipment, and belongs to the technical field of semiconductors. The method comprises the following steps: writing a full 0 data mode into a storage unit within a minimum write-to-read time interval; performing a read operation on the storage unit to which the full 0 data mode is written, and obtaining detection data; obtaining at least one storage array bit error rate index according to the detection data; and based on a comparison result of the bit error rate index and a preset threshold, selecting a target voltage gear from a preconfigured voltage gear set to adjust the read voltage of the storage unit to a corresponding read voltage gear. The application realizes self-adaptive and accurate calibration of the read voltage through fast detection of the full 0 mode under the minimum write-to-read interval and global evaluation of the bit error rate, thereby guaranteeing the test efficiency and significantly improving the reliability and durability of the memory.