9893 results about "Memory cell" patented technology

Technology for reading memory cells in three-dimensional memory having multiple tiers. The memory system erases the tiers within each block independently. Then, memory cells in the tiers are programmed by units such as word lines. The memory system determines one or more read parameters for the selected tier based on the programmed / erased states of the other tiers in the block. For example, the memory system may select read reference levels for the selected tier based on the programmed / erased states of the other tiers. In an aspect, the one or more read parameters are used to determine the set of reference voltages for a bit error rate estimation scan (BES).

The present application relates to the technical field of data storage. Disclosed are a multi-source heterogeneous distributed system, a memory access method and a nonvolatile readable storage medium. The method comprises: a first unified interconnection bus unit receiving, by means of a protocol adaptation interface module, a read request sent by a first device, and setting the cache state of a first memory unit to be an invalid state; sending to a second unified interconnection bus unit of a second device a request message obtained by packaging the read request, the second unified interconnection bus unit reading data from a second memory unit; setting the cache state of the second memory unit to be a shared state, and sending to the first unified interconnection bus unit a response message, the first unified interconnection bus unit storing in the first memory unit data carried by the response message; and setting the cache state of the first memory unit to be a shared state. Thus, deploying a unified interconnection bus unit on each device can achieve a consistent memory communication between the devices, thereby achieving memory sharing, and further improving the performance of the multi-source heterogeneous distributed system.

The invention discloses a phase change memory and electronic equipment, the phase change memory comprises a comparator, a second switch, a third switch, a memory circuit, a selected digital line, a first switch and an unselected digital line, the memory circuit, the selected digital line, the first switch and the unselected digital line are connected in sequence, and the reference voltage of the unselected digital line is set in a reading operation through the first switch and the third switch; the reference voltage is in positive correlation with the second negative voltage, the second negative voltage is smaller than the first negative voltage, and compared with the reference voltage which is in positive correlation with the first negative voltage, the lower reference voltage can be generated, so that the overshoot current flowing through the memory cell at the opening moment is reduced, and the reading interference suffered by the memory cell is reduced.

A sparse processing method and apparatus for a sparse attention network, and an electronic device. The method specifically comprises: in a memory cell, using constraint conditions to construct a masked sparse representation (S301), wherein the constraint conditions are: the dimension of a mask matrix is [B,a,S], B represents the batch size, a represents the number of heads, S represents the sequence length, and each element in the S dimension represents a masked starting row of each column in the mask matrix; and a calculation unit acquiring the masked sparse representation from the memory cell, using the masked sparse representation to perform sparse processing on input data, and storing the sparse processing result into the memory cell (S302). According to the method, the constraint conditions are used to construct the masked sparse representation, so that memory consumption can be reduced from a quadratic order of the sequence length to a linear order of the sequence length, thereby remarkably reducing memory requirements during large model training, and improving the training efficiency.

A method of fabricating a semiconductor device includes forming a memory cell array stack including a vertical stack of pad portions over a first substrate, forming first bonding pads each coupled to a different one of the pad portions in the vertical stack, forming control circuits including a plurality of sub-word line drivers over a second substrate, forming multi-layer level metal wiring coupled to the sub-word line drivers, forming second bonding pads coupled to the multi-layer level metal wiring, and performing a wafer bonding process for electrical coupling between the memory cell array stack and the control circuits.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NOR architecture in which vertical NOR strings are formed of multiple memory cells connected in parallel between a source line and a bit line. Weights of the neural network are encoded as threshold voltages of the memory cells and activations are encoded as word line voltages applied to the memory cells of the NOR strings. The memory cells are operated in the subthreshold region, where the word line voltages are below the threshold voltages. The NOR structure naturally sums the resultant subthreshold currents of the individual memory cells to generate the product of the activations and the weights of the neural network by concurrently applying input voltages to multiple memory cells of a NOR string.

A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and a redundancy control circuit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.

Technology is disclosed for reading memory cells having threshold switching selectors. A sense amplifier may have a set of capacitors that may be used to exchange charge with a sense node connected to the selected word line. A capacitor may be used to pull excess charge from the sense node or to provide charge to the sense node. A control circuit drives a current to the selected word line to charge up the selected word line to switch on the threshold switching selector of the selected memory cell. A capacitor may be connected to the selected word line when, or soon after, the threshold switching selector switches on. The capacitor may draw away excess charge to prevent a snapback current from flowing through the memory cell thereby preventing mis-reads. The capacitor may reduce read latency by speeding the rate of voltage change on a word line.

The present invention relates to a reconfigurable logic-in-memory cell consisting of triple-gate feedback memory elements. The reconfigurable logic-in-memory cell according to one embodiment of the present invention includes a plurality of triple-gate feedback memory elements including a drain region, a channel region, a source region, and a gate region where first and second programming gate electrodes and a control gate electrode are formed on the channel region.

A method of operating a memory device includes applying a first read voltage to a first word line WLn corresponding to target memory cells, applying a first pass voltage to a second word line WLn−1 corresponding to memory cells adjacent to the target memory cells, and applying a second pass voltage to a third word line WLn+1 corresponding to memory cells adjacent to the target memory cells. The second pass voltage is higher than the first pass voltage.

A system includes a plurality of memory devices and a processing device operatively coupled with the plurality of memory devices, to perform operations including: receiving a request to perform a memory access operation at a first memory region of a first memory device; determining, based on a data structure referencing a namespace, a mapping between an identifier of the first memory region and an identifier of a metadata region associated with the first memory region; identifying, based on an operation type of the memory access operation, one or more corresponding actions associated with the metadata region; and, responsive to causing the memory access operation to be performed on a first plurality of memory cells at the first memory device, causing at least one of the one or more corresponding actions to be performed on a second plurality of memory cells corresponding to the metadata region.

According to one aspect of the present disclosure, a memory device is provided. The memory device may include an array of memory cells, including a plurality of memory cells. A preset number of memory cells form a code word. The memory device may include peripheral circuit coupled to the array of memory cells. The peripheral circuit may be configured to obtain the first result corresponding to the code word at the target read voltage. The peripheral circuit may be configured to adjust the target read voltage in accordance with the first result corresponding to the code words at the target read voltage. The peripheral circuit may be configured to obtain the first result corresponding to the code words at the adjusted read voltage. The peripheral circuit may be configured to determine a valley voltage in accordance with a plurality of the first results.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value, the word line is biased so that, for at least one of the threshold voltages, the memory cell will be in the linear operation region. Input values are encoded as a set of one or more voltage levels applied to a corresponding set of bit lines, each bit line connected memory cells also storing the weight value, connected to the word line, and connected to the source line.

A high-density ferroelectric memory, and a preparation method therefor and an application thereof, belonging to the field of semiconductor memories. In the memory, multiple memory cells are arranged in an array, and the two sides of the array of the memory cells are connected to substantially orthogonal word lines and bit lines, the memory cell of the present invention adopts a stacked structure of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor and a resistive switching selector connected in series; the voltage division of the distributed ferroelectric capacitor in the unselected cells is reduced by regulating the RC delay of the memory cell, so that its disturbance is reduced; and the capacitance value of the ferroelectric capacitor is stable, and the influence of the disturbance voltage can be effectively reduced by RC regulation. The storage window of the memory is improved and the bit error rate is reduced, without increasing additional area overhead.

A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.

Embodiments of the present disclosure relates to an integrated circuit including an array of memory cells having the word lines and high-voltage power lines positioned on one side of the transistors and the bit lines and low voltage power lines positioned on the other side of the transistor. The memory cells according to the present disclosure also improve routing efficiency, thus, removing bottleneck of further scaling both SRAM cell.

To provide a memory system and a memory device with high reliability.SOLUTION: A memory system of the embodiment includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to determine a first voltage based on information regarding a gradient of a distribution of threshold voltages of each of the plurality of memory cells, and to perform tracking operations. The memory controller causes the memory device to perform a plurality of read operations using a plurality of read levels for the plurality of memory cells in the tracking operation. The memory controller acquires the number of ON cells in each of the plurality of read operations. The memory controller sets a first potential difference of the plurality of read levels in a voltage range lower than the first voltage and a second potential difference of the plurality of read levels in a voltage range higher than the first voltage to be different from each other.SELECTED DRAWING: Figure 12

Technology for zoned read parameters. The read parameters may include read reference levels and / or offsets applied to base read reference levels. The memory system may assign memory cells located in a region (e.g., block) into zones based on a ranking of a target read level for each set of memory cells in the region. The memory system may assign word lines in a block into zones based on a ranking of a target read voltage and / or target read voltage offset for each word line. The memory system may read each particular set of memory cells (e.g., word line in the block) using a representative read voltage for the zone into which the particular word line is assigned.

An example system includes a memory device and a processing device operatively coupled to the memory device. The processing device is configured to: produce a first data item by performing, using a first boost voltage level, a first read strobe with respect to a set of memory cells storing encoded data item; apply an offset to the first boost voltage level to produce a second boost voltage level; produce a second data item by performing, using the second boost voltage level, a second read strobe with respect to the set of memory cells; and produce, based on the first data item and the second data item, decoded data item corresponding to the encoded data item.

A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure vertically overlying the first microelectronic device structure. The first microelectronic device structure comprises a first memory array region and a first control logic device region configured to effectuate control operations for memory cells of the first memory array region. The second microelectronic device structure comprises a second memory array region and a second control logic device region configured to effectuate control operations for memory cells of the second memory array region. Related memory devices, electronic systems, and methods are also described.

A memory device includes a peripheral circuit structure and a cell array structure, in which the cell array structure overlaps the peripheral circuit structure in a first direction, in which the cell array structure includes a merged sub array in which at least four sub array regions are merged, in which the merged sub array comprises a memory cell region including: a plurality of first bit lines and a plurality of second bit lines; and a plurality of first word lines and a plurality of second word lines, in which the peripheral circuit structure comprises a merged bank in which at least four banks are merged, and in the merged bank comprises: a first bit line sense amplifier (BLSA), a second BLSA, a first sub word line driver (SWD), a second SWD, and in which a spare space is defined between the first bit lines and the second bit lines.

A semiconductor device comprises a first memory cell disposed on a first side of the semiconductor device and connected to a transistor, and a second memory cell disposed on a second side of the semiconductor device and connected to the transistor. The first side of the semiconductor device is on top of the transistor and the second side of the semiconductor device is under the transistor.

The invention relates to the technical field of integrated circuit repair, in particular to a storage repair system based on a polymorphic BISR chain, the system divides storage units in a chip into a plurality of repair modules, and a plurality of off-chip registers contained in each repair module form a plurality of first off-chip register chains; when the memory unit in the chip is repaired, the memory unit can be repaired at the same time through the plurality of first off-chip register chains, so that the repair duration of the memory unit of the chip is determined according to the maximum chain length of each first off-chip register chain; compared with the prior art that the repair duration of the chip storage unit is determined according to the sum of the chain lengths of all the off-chip registers, the storage repair time is greatly shortened, the storage repair efficiency is further improved, in the storage repair process, the storage unit can adopt a parallel repair mode or a serial repair mode, and the repair efficiency is improved. Storage repair can be compatible with memory cells of different repair types.

A memory apparatus includes memory cells and a control means configured to adjust at least one of blind program pulses applied to word lines connected to the memory cells and bit line voltages applied to bit lines coupled to the memory cells in response to determining one of the word lines connected to the memory cells being programmed is susceptible to over-programming. The control means programs non-checkpoint ones of the memory cells associated with a checkpoint state to a verify low voltage for the checkpoint state and programs the non-checkpoint ones of the memory cells to respective non-checkpoint states associated with the checkpoint state by applying the blind program pulses to each non-checkpoint one of the memory cells without verifying whether the non-checkpoint ones of the memory cells have reached their respective non-checkpoint states while applying the bit line voltages to the bit lines associated therewith.

The invention provides a synthetic antiferromagnetic memory cell driven by spin orbit moment without magnetic field assistance, and belongs to the technical field of magnetic memory, the synthetic antiferromagnetic memory cell comprises a magnetic tunnel junction of a multilayer film structure, the magnetic tunnel junction comprises a heavy metal layer and a synthetic antiferromagnetic free layer located on the heavy metal layer; the tunneling insulating layer is located on the synthetic antiferromagnetic free layer, the reference layer is located on the tunneling insulating layer, and the metal electrode layer is located on the reference layer; wherein the synthetic antiferromagnetic free layer comprises an inclined vertical magnetic layer, a non-magnetic metal layer and a coupling magnetic layer which are stacked in sequence, and the inclined vertical magnetic layer and the coupling magnetic layer are subjected to antiferromagnetic coupling through the middle non-magnetic metal layer; the inclined perpendicular magnetic layer has inclined perpendicular anisotropy. According to the invention, deterministic magnetization flipping driven by spin orbit moment and resistance state control of the magnetic tunnel junction memory cell without the assistance of an external magnetic field are realized.

A memory device includes pages each composed of memory cells arrayed in columns on a substrate. A page write operation of retaining a hole group formed by impact ionization inside a channel semiconductor layer, and a page erase operation of discharging the hole group from the channel semiconductor layer are performed. A first impurity layer is connected to a source line, a second impurity layer to a bit line, a first gate conductor layer to a first selection gate line, a second gate conductor layer to a plate line, a third gate conductor layer to a second selection gate line, and a bit line to a sense amplifier circuit. Page data of a memory cell group selected in at least one page is read to the bit line. Zero volts or less is applied to the plate line of the memory cell connected to an unselected page.

Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs in a first vertical cross-section along a first direction. Insulating material is in the cavity above the flight of stairs. The insulating material comprises first material atop treads of the stairs of the flight of stairs. Individual of the treads comprise conducting material of one of the conductive tiers. Insulative second material of different composition from that of the first material is directly above the first material. The first material has an uppermost surface in the cavity that is below an uppermost surface of the insulative second material in the cavity. Conductive vias extend through the first material and the insulative second material. Individual of the conductive vias are directly above and directly against the conducting material of the respective tread. Other embodiments, including method, are disclosed.

A system, method, and computer program product are provided for cooperation memory system. The system includes a first semiconductor platform including at least one first circuit, and at least one additional semiconductor platform stacked with the first semiconductor platform and including at least one additional circuit. The system further includes an adjustment of at least one aspect of the system, for repairing one or more faulty components of the memory subsystem capable of including: a through-silicon via (TSV) between the first memory and the second memory, and a memory cell of at least one of the first memory or the second memory.

The invention discloses a rapid aging test method and device for a memory array, and relates to the technical field of memory array test. Comprising the following steps: in a read-write operation process, capturing an instantaneous current waveform of each storage unit in a memory array, extracting current characteristics from the instantaneous current waveform, constructing a difference matrix by utilizing the extracted current characteristics, and dynamically marking the storage units exceeding a threshold value. According to the invention, by analyzing the difference of the stored data volume before and after the instantaneous current waveform capture of the storage unit, the capacity recession condition of the storage unit is evaluated, and the capacity recession data is used as an auxiliary evaluation index and combined with the aging rate of the storage unit. According to the invention, comprehensive evaluation of the aging degree of the memory units is completed without applying external influence conditions to the memory array, so that the accuracy of the aging test is improved, the aging difference between the memory units can be effectively identified, and the key memory units are ensured to be processed and maintained in time.

A spin-orbit-torque (SOT) memory cell includes a first electrode embedded in dielectric material layers overlying a substrate; a magnetic-tunnel-junction-containing (MTJ-containing) pillar structure contacting a top surface of the first electrode and including a pinned layer and a free layer that overlies the pinned layer; a spin current metal line including a center portion that contacts the MTJ-containing pillar structure; and a selector element electrically connected to a first end of the spin current metal line.