5267 results about "Memory cell" patented technology

A high-density ferroelectric memory, and a preparation method therefor and an application thereof, belonging to the field of semiconductor memories. In the memory, multiple memory cells are arranged in an array, and the two sides of the array of the memory cells are connected to substantially orthogonal word lines and bit lines, the memory cell of the present invention adopts a stacked structure of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor and a resistive switching selector connected in series; the voltage division of the distributed ferroelectric capacitor in the unselected cells is reduced by regulating the RC delay of the memory cell, so that its disturbance is reduced; and the capacitance value of the ferroelectric capacitor is stable, and the influence of the disturbance voltage can be effectively reduced by RC regulation. The storage window of the memory is improved and the bit error rate is reduced, without increasing additional area overhead.

An example system includes a memory device and a processing device operatively coupled to the memory device. The processing device is configured to: produce a first data item by performing, using a first boost voltage level, a first read strobe with respect to a set of memory cells storing encoded data item; apply an offset to the first boost voltage level to produce a second boost voltage level; produce a second data item by performing, using the second boost voltage level, a second read strobe with respect to the set of memory cells; and produce, based on the first data item and the second data item, decoded data item corresponding to the encoded data item.

The invention provides a synthetic antiferromagnetic memory cell driven by spin orbit moment without magnetic field assistance, and belongs to the technical field of magnetic memory, the synthetic antiferromagnetic memory cell comprises a magnetic tunnel junction of a multilayer film structure, the magnetic tunnel junction comprises a heavy metal layer and a synthetic antiferromagnetic free layer located on the heavy metal layer; the tunneling insulating layer is located on the synthetic antiferromagnetic free layer, the reference layer is located on the tunneling insulating layer, and the metal electrode layer is located on the reference layer; wherein the synthetic antiferromagnetic free layer comprises an inclined vertical magnetic layer, a non-magnetic metal layer and a coupling magnetic layer which are stacked in sequence, and the inclined vertical magnetic layer and the coupling magnetic layer are subjected to antiferromagnetic coupling through the middle non-magnetic metal layer; the inclined perpendicular magnetic layer has inclined perpendicular anisotropy. According to the invention, deterministic magnetization flipping driven by spin orbit moment and resistance state control of the magnetic tunnel junction memory cell without the assistance of an external magnetic field are realized.

Disclosed are a memory device and a control method thereof. The memory device may be a high-capacity and high-performance three-dimensional NAND flash memory. The control method includes the following steps. Data for performing a programming operation on a specific memory cell area is obtained. A number of memory cells in a predetermined potential state in the data are counted as a first number value. The programming operation is performed on the specific memory cell area based on the data. A read operation is performed based on a reference voltage corresponding to the predetermined potential state. A number of memory cells in the predetermined potential state in the specific memory cell area after the programming operation are counted as a second number value. Whether the specific memory cell area has program disturbances is determined based on the first number value and the second number value.

Memory cell structures, semiconductor memory devices, and their fabrication methods are disclosed. In an embodiment, method for fabricating a semiconductor device includes: forming a lower interconnect over a base layer; forming a memory cell structure over the lower interconnect; and forming an upper interconnect over the memory cell structure, wherein the forming of the memory cell structure includes: forming an initial selection element material layer; performing a first doping process that provides first dopants into the initial selection element material layer to reform the initial selection element material layer into a first doped selection element material layer; performing a second doping process that provides second dopants into the first doped selection element material layer to reform the first doped selection element material layer into a second doped selection element material layer; and forming a selection element layer by patterning the second doped selection element material layer.

The invention discloses a semiconductor device and a manufacturing method thereof, electronic equipment and an access method, the semiconductor device comprises a plurality of vertically stacked memory cells and a vertically penetrating word line, and each memory cell comprises a first transistor and a second transistor. A first semiconductor layer of the first transistor comprises a first semiconductor sub-layer and a second semiconductor sub-layer which are distributed along a second direction, and a word line is arranged between the first semiconductor sub-layer and the second semiconductor sub-layer; the second semiconductor layer surrounds the word line; the first gate electrode partially surrounds the word line and the second semiconductor layer and is in contact with the second semiconductor layer, and the first gate electrode is further distributed on the side wall of the side, facing the word line, of the first semiconductor sub-layer and the side wall of the side, facing the word line, of the second semiconductor sub-layer; the plurality of first gate electrodes of the plurality of vertically stacked first transistors are distributed at intervals in different areas of the side wall of the word line in the direction perpendicular to the substrate. According to the scheme provided by the embodiment, the word line can control on and off of the second transistor and the first transistor, control lines can be reduced, and the device area can be reduced.

The invention provides a memory, an operation method of the memory and a memory system, and relates to the technical field of semiconductor chips. The memory comprises a memory array and a peripheral circuit coupled to the memory array, the memory array comprises memory blocks, and the memory blocks are coupled to the peripheral circuit through word lines. Wherein the storage block comprises a programmed storage unit and an unprogrammed storage unit, and the programmed storage unit comprises a first storage unit and a second storage unit. The peripheral circuit is configured to: perform a program operation on a third memory cell in the memory block, and apply a first voltage to a first word line coupled to the first memory cell at a first stage of a channel preparation stage of the program operation; and applying a second voltage to a second word line coupled to the second memory cell. Wherein the first word line is located between a third word line coupled with the third storage unit and the second word line, and the first voltage is larger than the second voltage.

The embodiments of the present disclosure disclose a memory and system, a programming method, the method comprising: applying an Nth pulse to a selected memory cell with a target state of an i-th state; after applying the Nth pulse, performing a first sub-verification and an Nth second sub-verification on the selected memory cell, obtaining a first sub-result and an Nth second sub-result; the first sub-result indicating whether the threshold voltage of the selected memory cell is less than a preset voltage, and the Nth second sub-result indicating whether the threshold voltage of the selected memory cell is less than a target threshold voltage of the i-th state; determining, according to the Nth second sub-result, a memory cell that needs to be applied with an N+1th pulse among the memory cells with the target state of the i-th state; the difference between the N+1th pulse and the Nth pulse being greater than or equal to the difference between the target threshold voltage and the preset voltage; applying the N+1th pulse to the memory cell that needs to be applied with the N+1th pulse; after applying the N+1th pulse, when the first sub-result indicates that the number of failed bits of the first sub-verification is less than a first preset value, determining that the programming of the i-th state is passed.

A three-dimensional (3D) memory device and a method of fabricating the same are provided. In some embodiments, the disclosed semiconductor device is a memory device and includes an array of memory cells in an array region, word lines extending in parallel in a first lateral direction, bit lines extending in parallel in a second lateral direction different from the first lateral direction; and interconnect structures in the array region and coupled with the bit lines, and arranged in staggered rows along the first lateral direction.

Certain aspects provide an apparatus for performing machine learning tasks, and in particular, to computation-in-memory architectures. One aspect provides a circuit for in-memory computation. The circuit generally includes: a plurality of memory cells on each of multiple columns of a memory, the plurality of memory cells being configured to store multiple bits representing weights of a neural network, wherein the plurality of memory cells on each of the multiple columns are on different word-lines of the memory; multiple addition circuits, each coupled to a respective one of the multiple columns; a first adder circuit coupled to outputs of at least two of the multiple addition circuits; and an accumulator coupled to an output of the first adder circuit.

The invention discloses an SRAM (Static Random Access Memory) memory cell, a static random access memory and a preparation method thereof, and belongs to the field of semiconductors. Channel directions of two transmission gate transistors are set as a first direction, channel directions of two pull-up transistors are set as a second direction, and channel directions of two pull-down transistors are set as a third direction; the third direction and the first direction are crystal orientations of the same family, and the two pull-up transistors are arranged in a sinking manner; active regions of the pull-up transistor and other transistors are staggered so as to improve the heat dissipation capability; in order to manufacture the structure, a corresponding preparation method is designed, in the preparation process, the grid electrode of the pull-up transistor is stepped, so that the grid electrode of the pull-up transistor can be connected with the active region of the transmission grid transistor through a metal silicification technology, the contact resistance is greatly reduced, and the performance of the device is improved. Therefore, the performance of the whole device is improved, and the read-write speed is higher than that of the prior art under the same condition.

The application discloses a low-orbit satellite congestion control method based on an artificial immune algorithm, which comprises the following steps: a satellite node periodically monitors the occupancy rate of an output queue in each direction, when congestion is detected, the satellite generates a congestion warning packet as an antigen and sends it to a directly adjacent node; the adjacent node receiving the congestion warning packet finds a matching item of an affected destination node in a historical memory cell library through the similarity between the current scene and the historical record, as the routing strategy of the destination node; when no match is found, the optimal bypass strategy is determined based on the direction of the congestion link and the position information of the satellite; the satellite comprehensively evaluates the generated control strategy within a time window; when the affinity continues to fail to reach a threshold, the satellite continuously monitors the queue occupancy rate change trend, and when it is found that a continuous multiple periods show an upward trend, the shunt proportion is increased; the application improves the response speed of the congestion control, network performance and service quality.

A three-dimensional (3D) memory device and a method of fabricating the same are provided. In some embodiments, the disclosed semiconductor device is a memory device and includes an array of memory cells in an array region, word lines extending in parallel in a first lateral direction, bit lines extending in parallel in a second lateral direction; and interconnect structures in the array region and coupled with the word lines, and arranged in staggered columns along the second lateral direction.

A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.

Methods, systems, and devices for enhanced error handling in memory systems are described. A memory system may enter a read error handling procedure to recover data from a memory cell. For example, the memory system may perform multiple read operations at respective first read levels to identify a voltage valley associated with the data in the memory cell. Based on identifying the voltage valley, the memory system may read the data from the memory cell according to a second read level, where the second read level may be based on one of the first read levels, a first learning rate parameter, and a first momentum parameter. The memory system may determine whether to exit the error handling procedure or continue with the error handling procedure based on whether the data was successfully decoded in response to the read operation at the second read level.

There are provided a semiconductor memory device and a manufacturing method of the same. The semiconductor memory device includes: a peripheral circuit structure with a page buffer group; a net-shaped first source pattern disposed on the peripheral circuit structure, the net-shaped first source pattern with a plurality of openings; a memory cell array disposed on the net-shaped first source pattern; a second source pattern disposed between the net-shaped first source pattern and the memory cell array; and a cell-array-side pad pattern, disposed between the net-shaped first source pattern and the second source pattern, extending toward the net-shaped first source pattern from the second source pattern, the cell-array-side pad pattern being bonded directly to the net-shaped first source pattern.

The present disclosure relates to methods, devices, systems, and techniques for managing three-dimensional (3D) semiconductor devices. An example semiconductor device includes an array of memory cells. A memory cell in the array of memory cells includes a first vertical transistor and a first capacitor stacked along a first direction. The first capacitor includes a first electrode including a filler structure and a conductive layer surrounding the filler structure. The first electrode of the first capacitor is in contact with a first supporting structure and a second supporting structure. The first electrode of the first capacitor and the first supporting structure are disposed along a second direction. The first electrode of the first capacitor and the second supporting structure are disposed along the second direction. The first supporting structure and the second supporting structure extend along the second direction by different lengths. The second direction is perpendicular to the first direction.

The invention provides an SRAM (Static Random Access Memory) storage unit anti-single particle radiation reinforcement method and system, and relates to the technical field of microelectronics and circuit structure design, a redundant node coupled with a main storage node of an SRAM storage unit is constructed, and the redundant node is used for redundant storage of the logic state of the main storage node; the polarity of a main storage node is reinforced by configuring the main storage node into a circuit structure fully surrounded by a single-type transistor; wherein the redundant node and the main storage node after polarity reinforcement are integrated into a reinforced SRAM (Static Random Access Memory) storage unit. According to the method, circuit-level fusion and collaborative design are carried out on redundancy reinforcement and polarity reinforcement, so that the single event upset resistance of the SRAM unit is improved, and an efficient and enforceable reinforcement design method is provided.

A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lower-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5. A higher of the upper-second-tiers that is above said lower upper-second-tier comprises silicon dioxide that has a silicon-to-oxygen atomic ratio less than or equal to 0.5. Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier. After the stop, the sacrificial material is removed from the lower channel openings and channel-material strings are formed in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.

The invention discloses a high-reliability storage unit fault-tolerant control system, which relates to the technical field of storage unit fault-tolerant control and comprises a dynamic charge mapping model module, a potential inversion driving link module, a multi-channel phase conjugate regulation and control module, a nonlinear charge turn-back channel module and a self-adaptive capacitance balance control module. And the dynamic charge mapping model module is used for constructing a dynamic charge mapping model, extracting a potential transition curve in a high-frequency read-write switching stage by taking a parasitic capacitance real-time response parameter of a parallel bit line in the storage unit as an input variable, and generating a dynamic coupling map for identifying a pseudo-synchronous charge accumulation region based on the potential transition curve. According to the invention, real-time suppression and energy balance of parasitic capacitance are realized through dynamic charge mapping and potential inversion, and potential stability of a bit line is maintained; and energy closed-loop control is realized through nonlinear charge turn-back and self-adaptive capacitance regulation and control, charge regeneration is prevented, so that the stability and the reliability of the storage unit are improved, and the service life of the storage unit is prolonged.

The invention relates to the technical field of nonvolatile memories, in particular to a 2T1FC ferroelectric memory cell with a memory gate line and a preparation method of the 2T1FC ferroelectric memory cell. The 2T1FC ferroelectric storage unit with the storage gate line comprises a ferroelectric capacitor and a storage transistor which realizes read-write operation of data through polarization modulation of the ferroelectric capacitor; the control transistor is used for enabling a bit line to perform gating access; and the storage gate line is used for controlling the gate of the storage transistor and improving the holding capability of the written data. According to the invention, the special storage gate line is used, so that self-charge dissipation after writing is prevented, and the non-volatility is enhanced; separation of the storage path and the control path minimizes accidental flipping in the read / write cycle; the service life of the device is prolonged by lower write-in current stress and an isolated gate structure; low-voltage writing with high retentivity can be realized, and the method is suitable for energy-limited edge AI equipment.

Control logic in a memory device executes a programming operation to program a memory cell of a set of memory cells to a programming level. A first erase sub-operation is executed to erase the memory cell to a first threshold voltage level, the first erase sub-operation including applying, to the memory cell, a first erase pulse having a first erase voltage level. A second erase sub-operation is executed to erase the memory cell to a second threshold voltage level, the second erase sub-operation including applying, to the memory cell, a second erase pulse having a second erase voltage level, where the first erase voltage level of the first erase pulse is lower than the second erase voltage level of the second erase pulse.

A memory device includes a memory cell array configured to store data, a page buffer circuit configured to store data in the memory cell array or read data stored in the memory cell array, and a scan register circuit configured to receive a pass / fail result of data from the page buffer circuit and store the pass / fail result in a plurality of scan registers. The scan register circuit obtains information about the scan register where the fail result is stored through a scan operation, and uses the information about the scan register where the fail result is stored to determine the number of fail bits and / or a position index indicating the position of the fail bits according to the operation mode.

A unit for accumulating multiplied bit values includes an array of bit-line processors. The unit is implemented in an in-memory associative processor, and each bit-line processor includes multiple memory cells coupled to a bit-line. The array of processors is arranged in rows and columns. The array passes bits of a first multiplicand vertically down a column and provides bits of a second multiplicand horizontally across a row. The array generates carry bits and passes them vertically to a subsequent processor in the same column. The array also generates sum bits and passes them diagonally to a subsequent processor in an adjacent column. The array includes multiplying processors, summing processors, and accumulator processors. Multiplying processors perform an XOR operation by simultaneously activating two memory cells and then perform a full adder operation. Summing processors perform a full adder operation. Accumulator processors perform a full adder operation that includes a feedback sum bit from a previous cycle.

This disclosure is directed to column driver circuitry of a memory device. A memory bank of the memory device may include multiple memory cells arranged along multiple column select lines and row select lines. The column driver circuitry may include column drivers coupled to the column select lines. A column driver may generate a column select signal with multiple voltage steps for accessing a target memory cell coupled to a respective column select line. The column decoder may include circuitry to adjust a voltage level and / or duration of each voltage step of the column select signal to provide a desired voltage level to a target memory cell based on a disposition of the target memory cell along a column select line. For example, the column decoder may output a higher voltage level followed by a lower voltage level to access the target memory cell. The higher voltage level and the lower voltage level may be above a threshold voltage level for accessing the target memory cell.

A memory device includes a memory cell array, a page buffer circuit including first to Nth page buffers, each page buffer including a sensing node, and a control logic configured to control page buffer operations, wherein the control logic is further configured to control the page buffer operations such that, in a first page buffer operation on a first page buffer included in a first group, a precharge period and a discharge period for a first sensing node of the first page buffer are performed, in a fifth page buffer operation on a fifth page buffer included in a second group, a precharge period and a discharge period for a fifth sensing node of the fifth page buffer are performed, and in a sensing period of the fifth page buffer operation, sensing operations on the first and fifth sensing nodes are performed together.

A magnetoresistive memory cell includes a magnetic polarizer layer having a hard magnetization along a hard magnetization direction, a first magnetic tunnel junction located on a first side of the magnetic polarizer layer and including a first reference layer having a first side facing the magnetic polarizer layer, a first free layer facing a second side of the first reference layer, and a first tunnel barrier layer located between the first free layer and the first reference layer. The memory cell also includes a second magnetic tunnel junction located on a second side of the magnetic polarizer layer and including a second reference layer having a second side facing the magnetic polarizer layer, a second free layer facing a first side of the second reference layer, and a second tunnel barrier layer located between the second free layer and the second reference layer.

The present: invention addresses the problem of providing a silicon nitride etching liquid composition which is capable of selectively etching Si3N4 with a practical etching selectivity with respect to SiO2, while suppressing regrowth of SiO2, and which is also capable of suppressing pattern collapse of an SiO2 film in the production of a 3D nonvolatile memory cell. A silicon nitride etching liquid composition for producing a 3D nonvolatile memory cell, which contains phosphoric acid, one or more silane coupling agents and water, but which does not contain ammonium ions.

Described herein are memory cells that include two transistors stacked above one another above a support structure where neither one of the transistors is coupled to a capacitor and where at least one of the two transistors is a thin-film transistor. In such 2T capacitorless memory cells, a first transistor may be referred to a write transistor, and a second transistor may be a read transistor. The first transistor may be a three-terminal device having two S / D terminals and a gate terminal, while the second transistor may be a four-terminal device having two S / D terminals and two gate terminals.