14125 results about "Memory cell" patented technology

Apparatuses, systems, and methods for half-page modes. A memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. In some memory devices, each half of the memory cells may be separately activated by different word line portions. In some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. The additional information may be provided along additional data terminals so as not to increase the data burst length.

A memory device includes a bank array including a plurality of memory cells, a row decoder connected to the bank array through a plurality of wordlines, and a column decoder connected to the bank array through a plurality of column select lines. The bank array may include a first region and a second region different from the first region. First metadata for first normal data stored in the first region is stored in the second region, and second metadata for second normal data stored in the second region is stored in the first region.

Apparatuses, systems, and methods for half-page modes. A memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. In some memory devices, each half of the memory cells may be separately activated by different word line portions. In some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. The additional information may be provided along additional data terminals so as not to increase the data burst length.

Apparatuses, systems, and methods for half-page modes. A memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. In some memory devices, each half of the memory cells may be separately activated by different word line portions. In some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. The additional information may be provided along additional data terminals so as not to increase the data burst length.

Apparatuses, systems, and methods for half-page modes. A memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. In some memory devices, each half of the memory cells may be separately activated by different word line portions. In some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. The additional information may be provided along additional data terminals so as not to increase the data burst length.

A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a read operation on a set of memory cells of the memory device; identifying a wordline group coupled to the set of memory cells of the memory device; identifying a threshold voltage offset bin associated with the set of memory cells; determining a current temperature associated with the set of memory cells; determining, based on the threshold voltage offset bin and the current temperature, a read mask identifier associated with the set of memory cells; determining, based on the read mask identifier and the wordline group, a set of threshold voltage offsets associated with the set of memory cells; and performing the read operation using the set of threshold voltage offsets.

Technology for reading memory cells in three-dimensional memory having multiple tiers. The memory system erases the tiers within each block independently. Then, memory cells in the tiers are programmed by units such as word lines. The memory system determines one or more read parameters for the selected tier based on the programmed / erased states of the other tiers in the block. For example, the memory system may select read reference levels for the selected tier based on the programmed / erased states of the other tiers. In an aspect, the one or more read parameters are used to determine the set of reference voltages for a bit error rate estimation scan (BES).

In certain aspects, a memory device includes a semiconductor layer, a peripheral circuit including a peripheral transistor in contact with the semiconductor layer, an array of memory cells disposed beside the semiconductor layer and the peripheral circuit, and bit lines coupled to the memory cells. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. Each of the bit lines extends in a second direction perpendicular to the first direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.

The present application relates to the technical field of data storage. Disclosed are a multi-source heterogeneous distributed system, a memory access method and a nonvolatile readable storage medium. The method comprises: a first unified interconnection bus unit receiving, by means of a protocol adaptation interface module, a read request sent by a first device, and setting the cache state of a first memory unit to be an invalid state; sending to a second unified interconnection bus unit of a second device a request message obtained by packaging the read request, the second unified interconnection bus unit reading data from a second memory unit; setting the cache state of the second memory unit to be a shared state, and sending to the first unified interconnection bus unit a response message, the first unified interconnection bus unit storing in the first memory unit data carried by the response message; and setting the cache state of the first memory unit to be a shared state. Thus, deploying a unified interconnection bus unit on each device can achieve a consistent memory communication between the devices, thereby achieving memory sharing, and further improving the performance of the multi-source heterogeneous distributed system.

The invention discloses a phase change memory and electronic equipment, the phase change memory comprises a comparator, a second switch, a third switch, a memory circuit, a selected digital line, a first switch and an unselected digital line, the memory circuit, the selected digital line, the first switch and the unselected digital line are connected in sequence, and the reference voltage of the unselected digital line is set in a reading operation through the first switch and the third switch; the reference voltage is in positive correlation with the second negative voltage, the second negative voltage is smaller than the first negative voltage, and compared with the reference voltage which is in positive correlation with the first negative voltage, the lower reference voltage can be generated, so that the overshoot current flowing through the memory cell at the opening moment is reduced, and the reading interference suffered by the memory cell is reduced.

A sparse processing method and apparatus for a sparse attention network, and an electronic device. The method specifically comprises: in a memory cell, using constraint conditions to construct a masked sparse representation (S301), wherein the constraint conditions are: the dimension of a mask matrix is [B,a,S], B represents the batch size, a represents the number of heads, S represents the sequence length, and each element in the S dimension represents a masked starting row of each column in the mask matrix; and a calculation unit acquiring the masked sparse representation from the memory cell, using the masked sparse representation to perform sparse processing on input data, and storing the sparse processing result into the memory cell (S302). According to the method, the constraint conditions are used to construct the masked sparse representation, so that memory consumption can be reduced from a quadratic order of the sequence length to a linear order of the sequence length, thereby remarkably reducing memory requirements during large model training, and improving the training efficiency.

A method of fabricating a semiconductor device includes forming a memory cell array stack including a vertical stack of pad portions over a first substrate, forming first bonding pads each coupled to a different one of the pad portions in the vertical stack, forming control circuits including a plurality of sub-word line drivers over a second substrate, forming multi-layer level metal wiring coupled to the sub-word line drivers, forming second bonding pads coupled to the multi-layer level metal wiring, and performing a wafer bonding process for electrical coupling between the memory cell array stack and the control circuits.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NOR architecture in which vertical NOR strings are formed of multiple memory cells connected in parallel between a source line and a bit line. Weights of the neural network are encoded as threshold voltages of the memory cells and activations are encoded as word line voltages applied to the memory cells of the NOR strings. The memory cells are operated in the subthreshold region, where the word line voltages are below the threshold voltages. The NOR structure naturally sums the resultant subthreshold currents of the individual memory cells to generate the product of the activations and the weights of the neural network by concurrently applying input voltages to multiple memory cells of a NOR string.

Systems, methods, and apparatus related to memory devices that perform matrix vector multiplication using memory cells. In one approach, a memory cell array has memory cells used to perform matrix vector multiplication based on summing output currents from the memory cells. A context of memory cells is determined by a controller (e.g., a memory controller internal or external to a memory chip having the array). The context can include, for example, a physical location of memory cells, weight patterns being programmed, and / or neighboring cell interference, etc. Based on the determined context, the controller dynamically determines adjustments (e.g., adjusted target threshold voltages or currents) for programming the memory cells to store weights prior to performing the matrix vector multiplication.

A memory system, an operation method thereof and a readable storage medium are provided according to examples of this disclosure. The memory system including: a memory device including a plurality of memory blocks, each of which including a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines; a memory controller coupled to the memory device and configured to: acquire a read retry voltage with both a first-type read retry table and a second-type read retry table; control the memory device to perform a read retry operation with the read retry voltage.

A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and a redundancy control circuit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.

Technology is disclosed for reading memory cells having threshold switching selectors. A sense amplifier may have a set of capacitors that may be used to exchange charge with a sense node connected to the selected word line. A capacitor may be used to pull excess charge from the sense node or to provide charge to the sense node. A control circuit drives a current to the selected word line to charge up the selected word line to switch on the threshold switching selector of the selected memory cell. A capacitor may be connected to the selected word line when, or soon after, the threshold switching selector switches on. The capacitor may draw away excess charge to prevent a snapback current from flowing through the memory cell thereby preventing mis-reads. The capacitor may reduce read latency by speeding the rate of voltage change on a word line.

The invention provides a memory fault processing method and device, electronic equipment and a readable storage medium, and in the method, the electronic equipment can determine a first storage unit with a fault and isolate the first storage unit. The electronic equipment can carry out pressure measurement on the first storage unit to obtain the fault level of the first storage unit, the electronic equipment executes corresponding operation on the first storage unit according to the fault level of the first storage unit, and when the fault level of the first storage unit indicates that the first storage unit is in a first risk level, the first storage unit is in a second risk level. The operations include de-isolating the first memory cell. According to the method and the device, after the faulted storage unit is isolated, the voltage of the storage unit can be measured, and the real fault level of the storage unit is obtained. Wherein when the fault level of the first storage unit is the first risk level, the electronic equipment can remove isolation of the first storage unit, the first storage unit can be continuously used, and the number of available storage units can be increased.

The present invention relates to a reconfigurable logic-in-memory cell consisting of triple-gate feedback memory elements. The reconfigurable logic-in-memory cell according to one embodiment of the present invention includes a plurality of triple-gate feedback memory elements including a drain region, a channel region, a source region, and a gate region where first and second programming gate electrodes and a control gate electrode are formed on the channel region.

A method of operating a memory device includes applying a first read voltage to a first word line WLn corresponding to target memory cells, applying a first pass voltage to a second word line WLn−1 corresponding to memory cells adjacent to the target memory cells, and applying a second pass voltage to a third word line WLn+1 corresponding to memory cells adjacent to the target memory cells. The second pass voltage is higher than the first pass voltage.

Methods, systems, and devices for row hammer mitigation for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute operations for row hammer mitigation across circuitry of the semiconductor system. A first interface block of a first die of the semiconductor system may exchange signaling with a second interface block of a second die of the semiconductor system to perform row hammer mitigation operations. The second die may implement counters to track quantities of access operations associated with respective rows of memory cells of the second die. The second interface block may transmit alert signaling to the first interface block based on a value of a counter, and the first interface block may evaluate the alert signaling and transmit refresh signaling to the second interface block to perform one or more refresh operations.

The invention relates to the technical field of data storage, and provides an optimal reading voltage determination method and device, a terminal and a storage medium, and the method comprises the steps: constructing an original threshold voltage curve corresponding to a target reading voltage grade according to the error bit number of the storage medium under each threshold voltage; obtaining error bit numbers of storage units corresponding to two storage states adjacent to the target read voltage level under each threshold voltage, and constructing a first threshold voltage curve and a second threshold voltage curve; and according to the first threshold voltage curve, the second threshold voltage curve and the original threshold voltage curve, determining an optimal reading voltage under the target reading voltage grade. According to the method and the device, the storage units are divided into different storage states, when the optimal read voltage under the target read voltage level is determined, only the error bit number of the two storage states adjacent to the target read voltage level needs to be considered, and the influence of implicated overturning and noise brought by other storage units is eliminated, so that the optimal read voltage is determined more accurately.

A memory cell for a display is disclosed. The memory cell has a current limiter on the power supply to reduce the power consumed by the memory cell during a write operation when the binary state of the memory cell is flipped. In a dense memory environment, in a display with a million or more memory cells, the incremental power reduction of each memory cell corresponds to a substantial reduction in the overall power consumed by the display.

A system includes a plurality of memory devices and a processing device operatively coupled with the plurality of memory devices, to perform operations including: receiving a request to perform a memory access operation at a first memory region of a first memory device; determining, based on a data structure referencing a namespace, a mapping between an identifier of the first memory region and an identifier of a metadata region associated with the first memory region; identifying, based on an operation type of the memory access operation, one or more corresponding actions associated with the metadata region; and, responsive to causing the memory access operation to be performed on a first plurality of memory cells at the first memory device, causing at least one of the one or more corresponding actions to be performed on a second plurality of memory cells corresponding to the metadata region.

According to one aspect of the present disclosure, a memory device is provided. The memory device may include an array of memory cells, including a plurality of memory cells. A preset number of memory cells form a code word. The memory device may include peripheral circuit coupled to the array of memory cells. The peripheral circuit may be configured to obtain the first result corresponding to the code word at the target read voltage. The peripheral circuit may be configured to adjust the target read voltage in accordance with the first result corresponding to the code words at the target read voltage. The peripheral circuit may be configured to obtain the first result corresponding to the code words at the adjusted read voltage. The peripheral circuit may be configured to determine a valley voltage in accordance with a plurality of the first results.

An array of memory cells includes a scan chain with one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The duration of the sequence equals at most a cycle of the SCLK signal. The scan chain applies the pulses to the memory cells backwards starting from the chain buffer memory cell. Memory cells may include a single latch. The array of memory cells may be included in a semiconductor memory subsystem. A scan chain that has a fault condition may be repaired by rerouting the scan chain to avoid the location of the fault condition and to add one or more redundant chain segments.

A memory apparatus and method of operation are provided. The apparatus includes memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states. The memory cells are disposed in memory holes grouped in blocks. A control means is configured to determine an amount of the memory cells of one of the blocks that are programmed during at least one read operation. The control means adjusts at least one read parameter based on the amount of the memory cells of the one of the blocks that are programmed. The control means is also configured to utilize the adjusted at least one read parameter while reading the memory cells to determine if the memory cells have the threshold voltage above one or more read levels associated with each of the plurality of data states in the at least one read operation.

Methods, systems, and computer program products for high-performance cluster computing. Multiple components are operatively interconnected to carry out operations for high-performance RDMA I / O transfers over an RDMA NIC. A virtual machine of a virtualization environment initiates a first I / O call to an HCI storage pool controller using RDMA. Responsive to the first I / O call, a second I / O call is initiated from the HCI storage pool controller to a storage device of an HCI storage pool. The first I / O call to the HCI storage pool controller is implemented through a first virtual function of an RDMA NIC that is exposed in the user space of the virtualization environment. Prior to the first RDMA I / O call, a contiguous unit of memory to use in an RDMA I / O transfer is registered with the RDMA NIC. The contiguous unit of memory comprises memory that is registered using non-RDMA paths such as TCP or iSCSI.

A memory system includes a plurality of memory cells each storing a first bit and a second bit and a control circuit. The control circuit is reads out first data, first partial data, and second partial data, each corresponding to the first bit, from the plurality of memory cells, read out second data, third partial data, and fourth partial data, each corresponding to the second bit, from the plurality of memory cells, generate first compressed data based on an OR operation of the first partial data and the third partial data, generate second compressed data based on an OR operation of the second partial data and the fourth partial data, and transmit the first data, the second data, the first compressed data, and the second compressed data to an external memory controller.

In a memory device including a ternary memory cell, the ternary memory cell may include: a first inverter and a second inverter cross-coupled in a first node and a second node and including a pull-up device and a pull-down device configured to have a constant current pass therethrough upon turn-off; a first read transistor and a first write transistor which are connected to each other in parallel between the first node and a first bit line; and a second read transistor and a second write transistor which are connected to each other in parallel between the second node and a second bit line, wherein the first read transistor and the second read transistor may have a read access current, which is less than or equal to the constant current, pass therethrough in response to an activated read word line.