81 results about "Read bit line" patented technology

The embodiment of the invention relates to the field of memories, and provides a sense amplifier which at least comprises a first transistor electrically connected between a first power supply node and a complementary read bit line, and the control end of the first transistor is connected to the control end of a third transistor; the second transistor is electrically connected between the second power supply node and the reading bit line, and the control end of the second transistor is connected to the control end of the fourth transistor; a third transistor electrically connected between the complementary read bit line and a third power supply node; a fourth transistor electrically connected between the read bit line and a fourth power supply node; the first calibration tube is connected between the complementary reading bit line and the control end of the third transistor; wherein the first power supply node is connected to a first power supply voltage through the first switching element; the second power supply node is connected to the first power supply voltage through the second switching element; the third power supply node is connected to a second power supply voltage through a third switching element; the fourth power supply node is connected to the second power supply voltage through a fourth switching element.

A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.

An on-chip static RAM (SRAM) is disclosed. In one embodiment, the on-chip SRAM includes an array of memory cells arranged in columns and rows, a read bit line for each column of the array of memory cells, and an output latch to store a bit for one of the array of memory cells when the on-chip SRAM is in a retention mode. In one embodiment, each memory cell in the column is connected to the read bit line for that column and the output latch includes a transistor that does not allow the read bit line for the column corresponding to the one of the array of memory cells to pre-charge when a data latch in the output latch is in a high state.

A storage array, a memory, a reading method thereof, and an electronic device are disclosed. The storage array includes multiple storage cell subarrays, a reference cell column, and a set of reference voltage generation circuits, reference cell switching circuits, and read word line control circuits. The storage cell subarrays and reference cell column in two storage arrays are electrically connected via read bit lines and symmetrically distributed around a read decision unit. The transistors of the reference cells and storage cells are isomorphic and have the same circuit structure. The memory includes at least one pair of open storage arrays, each pair comprising a first storage array, a second storage array, and a set of read decision units. Each storage array is electrically connected to one of the two input terminals of the read decision unit. During reading, the two storage arrays provide a read voltage and a reference voltage, respectively. The two input terminals of the read decision unit have similar RC parameters, and the drift generated by the voltages at the two input terminals is also matched. This application improves storage density and data reading reliability.

The embodiment of the invention provides a memory and an operation method thereof, relates to the technical field of storage, and realizes a simultaneous read-write function of the memory. According to the specific scheme, the memory comprises a time schedule controller, a memory array, a plurality of writing word lines, a plurality of reading word lines, a plurality of writing bit lines and a plurality of reading bit lines. The storage array comprises a plurality of storage units, the storage units located in the same row are coupled with the same writing word line and the same reading word line, and the storage units located in the same column are coupled with the same writing bit line and the same reading bit line. The time schedule controller is configured to apply a writing line voltage to a writing line corresponding to a first storage unit in the plurality of storage units in any clock period, and the writing line voltage is greater than the word line voltage. The time schedule controller is further configured to apply a read word line voltage to a read word line corresponding to a second storage unit in the plurality of storage units in a clock period, and the first storage unit and the second storage unit are storage units in different rows.

This application provides a storage circuit, a storage chip, and an electronic device. The storage circuit includes a sub-read circuit, read bit lines, at least one read auxiliary unit, and multiple static random access memory (SRAM) cells. The read bit lines are connected to the sub-read circuit, the at least one read auxiliary unit, and the multiple SRAM cells. The sub-read circuit performs read operations through the multiple SRAM cells. The read auxiliary unit is obtained by updating the circuit connections of the SRAM cells and is used to adjust the potential of the read bit lines. This not only improves the success rate of reading 1 operations and accelerates the speed of reading 0 operations, but also avoids excessive area overhead in the storage circuit.

The invention relates to a semiconductor device and an operating method thereof. A semiconductor device including one or more memory cells and a method of operating the same are disclosed. Each memory cell includes: a first transistor configured to write data; a second transistor configured to store data; and a third transistor configured to refresh data. The memory cell includes: a first transistor including a first gate connected to a write word line and one terminal connected to a memory node; a second transistor including a second gate connected to the storage node and one terminal connected to a read word line; and a third transistor including a third gate connected to the read word line and one terminal connected to the read bit line.

The invention discloses a three-dimensional fast read memory based on IGZO and a storage and calculation framework, and relates to the technical field of circuit design. The framework comprises a storage layer formed by stacking L layers of IGZO-3T0C arrays and used for storing target data, each layer of IGZO-3T0C array comprises a plurality of storage units, and L is a positive integer larger than 1; the discharge layer is composed of an IGZO array, is connected with the storage layer through a read bit line, and is used for carrying out discharge initialization on a read-out intermediate node in a to-be-read storage unit in the early stage of read operation; and the read-out layer consists of a CMOS (Complementary Metal Oxide Semiconductor) array, is connected with the storage layer through a read bit line, and is used for reading out the target data. According to the framework, the reading speed and the integration density can be improved, and the problems of electric leakage and crosstalk occurring after a reading layer is added to a traditional three-dimensional array composed of 2T0C units are solved, so that the energy efficiency is improved.

Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a first source / drain feature and a second source / drain feature. The semiconductor structure also includes a first plurality of metal lines comprising a write bit line and a complementary write bit line, wherein the first plurality of metal lines are positioned at a first metal interconnect layer, wherein the first metal interconnect layer is disposed over the first source / drain feature. The semiconductor structure also includes a read bit line positioned at a second metal interconnect layer, where the second metal interconnect layer is disposed under the first source / drain feature.

A storage system and circuits therefor. A storage system includes a bitcell array comprising a plurality of storage cells arranged in one or more columns and one or more rows; a read bitline associated with a first column to access storage cells of the first column, wherein the read bitline has a first keeper circuit coupled thereto; and a tracker bitline associated with the read bitline, wherein the tracker bitline has a second keeper circuit coupled thereto, and wherein the tracker bitline is configured such that a behaviour thereof is to substantially match a behaviour of the read bitline.

The present application relates to temperature tracking dynamic keeper for implementing read operations. A static random access memory (SRAM) system includes a plurality of SRAM memory cells, each of the plurality of SRAM memory cells coupled to a respective read bit line, and a dynamic keeper coupled to the read bit line. The dynamic keeper includes a first keeper supporting read operations for a first temperature range and a second keeper supporting read operations for a second temperature range, and a temperature sensitive control circuit that selects the first keeper or the second keeper based on temperature.

The invention relates to an in-memory computing unit, an operation method thereof and an in-memory computing array. The in-memory computing unit comprises a write transistor, a read transistor and a nonvolatile memory, a first electrode of the write transistor is connected with a grid electrode of the read transistor to form a storage node, a second electrode of the write transistor is connected to a write bit line, and the grid electrode is connected to a write word line; a first electrode of the read transistor is connected to a read word line, and a second electrode is connected with a first electrode of the nonvolatile memory; a second electrode of the non-volatile memory is connected to the read bit line. By integrating a write transistor, a read transistor, and a non-volatile memory, cell area overhead can be reduced.

A semiconductor memory device includes a write bit line and a read word line extending in a first horizontal direction and spaced apart from each other in a second horizontal direction, a write word line, a read bit line, and a source line between the write bit line and the read word line and extending in a vertical direction and being spaced apart in the first horizontal direction, a capacitor electrode having a first portion and a second portion, a capacitor dielectric layer, a first gate dielectric layer covering a side surface of the first portion, a first channel layer covering the first gate dielectric layer, a second gate dielectric layer covering a portion of a side surface of the write word line, and a second channel layer connected to the second portion of the capacitor electrode and to the write bit line and covering the second gate dielectric layer.

A configurable operation unit in a memory is provided, including a first input transistor, a first weight transistor, a first resistor, a second input transistor, a second weight transistor, and a second resistor. The first input transistor, the first weight transistor, and the first resistor are coupled in series between a first read bit line and a common signal line, wherein the first input transistor is coupled to a first input bit line, and the first weight transistor receives a first weight bit. The second input transistor, the second weight transistor, and the second resistor are coupled in series between the first read bit line and the common signal line, wherein the second input transistor is coupled to a second input bit line, and the second weight transistor receives a second weight bit.

This invention provides an in-memory computing system, method, and chip that supports fully parallel computation of deep convolution channels. The system includes: a parallel computing module comprising k×k multi-bit data units, each multi-bit data unit comprising q storage sub-units for storing k×k q-bit activation value storage data, and performing simulated multiplication and accumulation operations on the k×k q-bit activation value storage data and input weight parameters of size (k×k,1); a weight configuration circuit connected to the parallel computing module, used to perform bit-level simulation recombination of the q-bit weights in the simulated multiplication and accumulation operation output by the parallel computing module, obtaining a simulated multiplication and accumulation result of 1-bit input weight parameters and q-bit activation value storage data; an ADC quantization circuit connected to the weight configuration circuit, used to quantize the simulated multiplication and accumulation result, obtaining integer data output; and an activation value update circuit connected to the bit line and read bit line of the column where the parallel computing module is located, used to perform local cyclic updates of the activation value storage data within the parallel computing module. This invention can increase the parallelism of array computation and realize local cyclic updates of activation values ​​within the array, thereby improving energy efficiency.

A semiconductor device that is highly integrated and reliable is provided. A back gate electrode of a second transistor is electrically connected to a control signal line supplying a control signal controlling the threshold voltage of the second transistor. One of a source and a drain of the second transistor is electrically connected to a read word line supplying a read word signal. The other of the source and the drain of the second transistor is electrically connected to a read bit line reading a potential corresponding to data. In a memory cell selected in a data reading period, a low level is supplied as the read word signal and a high level is supplied as the control signal. In the memory cell not selected in the data reading period, a high level is supplied as the read word signal and a low level is supplied as the control signal.

The application relates to the technical field of memories, and particularly provides a ROM memory, a data reading method thereof and an electronic device, which comprise a storage circuit, a reference circuit and a comparison circuit; the storage circuit comprises a multiplexer and a storage array; the reference load of the reference circuit is greater than the minimum load of a reading bit line and smaller than the maximum load; the voltage-time variation slope of a reference voltage generated during reading is smaller than the slope when a storage unit reads 0 and greater than the slope when the storage unit reads 1; the reading bit line is a bit line corresponding to the multiplexer; the comparison circuit compares the reference voltage and a reading voltage, determines an output reading digital signal, and the reading voltage is an output voltage of a reading storage unit. The application solves the problem that a large-capacity ROM read-only memory has a high load and is prone to reading errors due to slow reading speed in the prior art.

The application provides a data processing method, system, device and medium, and mainly comprises the following steps: acquiring a sensor signal, sending the sensor signal to a read bit line of an SRAM array; determining that the voltage value of the read bit line is stable, and turning on a read word line of the SRAM array; acquiring a weight value of the sensor signal through the read word line, performing a multiplication operation according to the weight value, obtaining a first output voltage, and outputting the first output voltage to a shared bit line; performing binaryzation processing on the first output voltage to obtain second output data, and obtaining a convolution operation result from the second output data; the scheme can greatly reduce the hardware cost, power consumption and delay of data transmission without a series of intermediate analog-digital conversion and digital-analog conversion processing steps, can effectively improve the accuracy of the neural network algorithm, can also reduce the delay and power consumption caused by data transfer, can meet the requirements of low delay, high bandwidth and other high performance, and can be widely applied to the embedded technical field.

The invention provides a memory based on a transistor and a ferroelectric capacitor, a preparation method, a reading method and electronic equipment, relates to the field of memories, and aims to solve the problems that the integration level of a current memory still needs to be improved and the crosstalk is relatively large. Comprising a writing transistor, a reading transistor, a writing word line, a reading bit line, a reading induction line, a plurality of ferroelectric capacitors and a plurality of writing bit lines, the memory comprises a substrate, a first stack structure, a second stack structure, a third stack structure, an active layer, a ferroelectric layer and a conductive layer. The first stack structure comprises a plurality of write bit line layers and a plurality of first dielectric layers; the second stacking structure comprises a second dielectric layer, a reading bit line layer, a third dielectric layer and a grid electrode of the reading transistor which are stacked in sequence; the third stacking structure comprises a fourth dielectric layer, a reading induction line layer, a fifth dielectric layer, a writing word line layer, a sixth dielectric layer and a connecting layer which are stacked. According to the invention, the miniature capability of the array can be improved, and the integration level is further improved.

A sensing circuit and a control method of the sensing circuit are provided. The sensing circuit includes a data line, a complementary data line, a read bit line, a complementary read bit line, a read pass gate circuit and logic circuit. The logic circuit enables the read pass gate circuit when a voltage level on the read bit line and a voltage level on the complementary read bit line are pre-charged to a first voltage level, and disable the read pass gate circuit when one of the voltage level on the read bit line and the voltage level on the complementary read bit line is pull to a second voltage level different from the first voltage level. The read pass gate circuit is enabled to connect the data line to the read bit line and connect the complementary data line to the complementary read bit line.

The embodiment of the invention discloses a memory device and a forming method thereof. The memory device includes a cross-latch, first, second, third, and fourth transistors, and a first read bit line. The first transistor includes a first gate extending in a first direction and at a first level. The second transistor includes a second gate on a second level below the first level. A third transistor is coupled to the first storage node and includes a third gate on the first level. A fourth transistor is coupled to the first storage node and includes a fourth gate on the second level. A first read bit line extends in the second direction, is on the first metal layer over the front side of the substrate, and is coupled to the third and fourth transistors. The third and fourth transistors correspond to a first port of the device.

The invention belongs to the related technical field of hardware implementation of neural networks, and discloses a floating gate transistor-based and pre-nonlinear activated neural network in-memory computing system and a training method thereof, the in-memory computing system comprises a plurality of neural network hierarchies connected in series, and each hierarchy comprises a computing array, an input module and an output module; the calculation array is a transistor array formed by floating gate transistors; the input module obtains analog voltage and applies the analog voltage to the floating gate transistor; the floating gate transistor realizes non-linear activation and weighted calculation to obtain current and gathers and outputs the current through a bit line; and the output module is used for reading the current on the bit line, converting the current into a voltage signal and outputting the voltage signal from the output end of the corresponding level. According to the subversive calculation normal form, the non-linear activation step is arranged in front of the summation step, the normal form fundamentally eliminates the requirements for an independent non-linear activation function circuit and an analog-digital converter in the middle of the non-linear activation function circuit, and therefore the system architecture is greatly simplified, and the circuit area and power consumption are remarkably reduced.

This invention provides a memory device and a memory array. The memory device includes memory cells. Each memory cell includes a first switching element, a second switching element, and a storage element. The first switching element is used to receive a write bit line signal and is coupled to a storage node. The second switching element is used to receive a read bit line signal and is coupled to the storage node. The storage element is coupled to the storage node and is used to receive a voltage signal and store a first data bit, wherein the memory cell is used to store a second data bit, different from the first data bit, in the storage node.

The invention relates to the technical field of time-to-digital converters, and provides a time-to-digital converter based on a magnetic track memory, comprising: a magnetic track memory array having m rows and n columns of units, each unit representing a magnetic nanowire, all units in each row sharing the same word line, all units in each column share one writing bit line and one reading bit line; an output port of the word line driver is connected with a word line input port of the magnetic track memory array; an output port of the write-in and reset controller is connected with a write bit line input port of the magnetic track memory array; the input port of the SA array is connected with the read bit line output port of the magnetic track memory array; and the storage controller is used for generating a control signal and pulse current. The time-to-digital converter has the functions of time-to-digital signal conversion and nonvolatile storage, can realize high-precision time measurement and reliable storage, and is convenient to construct a large-scale time-to-digital converter array.

The application discloses a kind of asymmetric write dual-voltage magnetic random access memory (MRAM) structure, including magnetic random access array, write drive circuit, readout circuit, write bit line selection circuit, read bit line selection circuit, word line drive circuit and control circuit.The application is designed using two voltage domains transistor, to guarantee that memory can work normally under dual power supply voltage.When writing, control part works in low voltage domain, and write circuit part works in high voltage domain, which can shorten write delay and improve write yield;When reading, readout circuit and control part work in low voltage domain, which can reduce read power consumption and reduce read damage.At the same time, for the asymmetry of MRAM memory cell structure, the application proposes an asymmetric write mode, which effectively reduces the power waste in the writing process.Compared with the traditional MRAM memory, the application effectively improves the write yield and reduces the write delay while considering the area and energy efficiency.

This disclosure provides a voltage configuration method for a memory array, applicable to the field of circuit technology. The method includes: configuring the write word line and the write bit line to a first voltage in response to a read operation, such that the write transistor is in a turned-off state; configuring the read bit line to a second voltage, the second voltage being greater than the first voltage; determining a selection state of the read word line of the memory array, the selection state indicating whether a memory cell associated with the read word line performs a read operation; and configuring the voltage of the read word line according to the selection state and the second voltage to control the conduction state of the read transistor.

Each latch cell in a latch cell array is made of 12 MOS transistors including a first CMOS switch transferring write data and a second CMOS switch transferring read data. A test for rewriting a storage node on a write bit line side in each latch cell from a first logic level to a second logic level in a state in which the first and second CMOS switches are respectively controlled to be on in overlapping time periods is assumed. In this case, a disturb test circuit precharges a read bit line to the second logic level before the second CMOS switch is controlled to be on.

The invention provides a physical unclonable function generator, a generation method and electronic equipment, relates to the field of electronic devices, and aims to solve the problem that existing physical unclonable function generators have certain limitations. The physical unclonable function generator comprises a write transistor and a read transistor; a control electrode of the writing transistor is electrically connected with a writing word line, a first electrode of the writing transistor is electrically connected with a writing bit line, and a second electrode of the writing transistor is electrically connected with a control electrode of the reading transistor; a first electrode of the reading transistor is electrically connected with a reading word line, and a second electrode of the reading transistor is electrically connected with a reading bit line; and the controller is electrically connected with the write bit lines and the read bit lines of the plurality of gain units, and the controller is used for adjusting the write voltage of each gain unit and determining a key value according to the magnitude relationship between the read current of each gain unit and the reference current. The physical unclonable function generator provided by the invention has extremely high randomness and better entropy source quality.

The application provides an access circuit and a storage unit circuit. The access circuit comprises a first transistor and a second transistor. A first end of the first transistor is coupled to a read bit line. A second end of the first transistor is coupled to a read source line. A first end of the second transistor is coupled to a write bit line. A second end of the second transistor is coupled to a gate end of the first transistor as a storage end point. A gate end of the second transistor is coupled to a write word line. A base end of the first transistor is coupled to the gate end of the first transistor.