128 results about "Read bit line" patented technology

In a matrix of SOT-MRAM cells, a first row is selected for writing and a second row is selected for reading. A first SOT-MRAM cell of the first row and a second SOT-MRAM of the second row are in a first column, while a third SOT-MRAM cell of the first row and a fourth SOT-MRAM of the second row are in a second column. The currents for writing the first SOT-MRAM cell and the third SOT-MRAM cell are in opposite direction. A first sense amplifier is configured to detect a voltage change on the first read bit line which is charged with a first read current in the second SOT-MRAM cell. A second sense amplifier is configured to detect a voltage change on the second read bit line which is discharged with a second read current in a fourth SOT-MRAM cell.

The embodiment of the invention relates to the field of memories, and provides a sense amplifier which at least comprises a first transistor electrically connected between a first power supply node and a complementary read bit line, and the control end of the first transistor is connected to the control end of a third transistor; the second transistor is electrically connected between the second power supply node and the reading bit line, and the control end of the second transistor is connected to the control end of the fourth transistor; a third transistor electrically connected between the complementary read bit line and a third power supply node; a fourth transistor electrically connected between the read bit line and a fourth power supply node; the first calibration tube is connected between the complementary reading bit line and the control end of the third transistor; wherein the first power supply node is connected to a first power supply voltage through the first switching element; the second power supply node is connected to the first power supply voltage through the second switching element; the third power supply node is connected to a second power supply voltage through a third switching element; the fourth power supply node is connected to the second power supply voltage through a fourth switching element.

A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.

A dynamic random access memory (DRAM) array has a first portion configured as a data array and a second portion configured as a reference array. The DRAM array includes read bit lines which include a first plurality of read bit lines in the data array and a second plurality of read bit lines in the reference array. Read circuitry includes a plurality of sensing circuits, each sensing circuit coupled to a corresponding read bit line of the first plurality of read bit lines and configured to receive a first reference voltage generated by a first read bit line of the second plurality of read bit lines and a second reference voltage generated by a second read bit line of the second plurality of bit lines. The plurality of sensing circuits is configured to provide a corresponding bit of an output read value.

This disclosure presents a computing-in-memory (CIM) device, including two CIM blocks. These two blocks are connected to the same read bit lines and share an analog-to-digital converter array. The two CIM blocks can perform writing operations simultaneously in one mode. In this case, one block stores a weight matrix, while the other stores the transpose of the weight matrix. In another mode, one CIM block performs the write operation while the other conducts a multiply-accumulate operation. This CIM device can be applied in both inference and training phases.

An on-chip static RAM (SRAM) is disclosed. In one embodiment, the on-chip SRAM includes an array of memory cells arranged in columns and rows, a read bit line for each column of the array of memory cells, and an output latch to store a bit for one of the array of memory cells when the on-chip SRAM is in a retention mode. In one embodiment, each memory cell in the column is connected to the read bit line for that column and the output latch includes a transistor that does not allow the read bit line for the column corresponding to the one of the array of memory cells to pre-charge when a data latch in the output latch is in a high state.

A 3T gain cell includes a write transistor, a storage transistor and a read transistor. The write transistor has a first diffusion connected to a write bit line (WBL), a gate connected to a write word line (WWL) and a second diffusion. The storage transistor has a gate connected to said second diffusion of said write transistor, a first diffusion connected to a read bit line (RBL), and a second diffusion. The read transistor has a gate connected to a read word line (RWL) a first diffusion connected to said second diffusion of said storage transistor, and a second diffusion connected to a reference voltage.

The invention provides a static memory cell and a memory architecture which can improve the storage stability and reduce the area overhead at the same time. The static memory cell includes: a first inverter circuit having an output electrically connected to a first storage node and an input electrically connected to a second storage node; the output end of the second inverter circuit is electrically connected to the second storage node, and the input end of the second inverter circuit is electrically connected to the first storage node; a read operation transistor having a gate electrically connected to the first storage node, a drain electrically connected to a read bit line, and a source electrically connected to a read word line; and a write pass transistor having a drain electrically connected to the second storage node, a gate electrically connected to a write word line, and a source electrically connected to a write bit line.

An eDRAM cell for a CIM according to the present disclosure includes a first transistor which is connected between a read word line and a read bit line and has a gate connected to a storage node; a second transistor which is connected between a write bit line and the storage node and has a gate connected to a write word line; a first capacitor connected between the storage node and a ground; a third transistor which is connected between a local MAC bit line and a fourth transistor and has a gate connected to the storage node; and a fourth transistor which is connected between the third transistor and the ground and has a gate connected to a MAC word line.

The invention relates to the technical field of memories, and particularly provides an ROM (Read Only Memory), a data reading method thereof and electronic equipment, and the ROM comprises a storage circuit, a reference circuit and a comparison circuit, the storage circuit comprises a multiplexer and a storage array; the reference load of the reference circuit is larger than the minimum load and smaller than the maximum load of the read bit line, the voltage-time change slope of the reference voltage generated during reading is smaller than the slope when the memory unit reads 0 and larger than the slope when the memory unit reads 1, and the read bit line is a bit line corresponding to the multiplexer; the comparison circuit compares a reference voltage with a read voltage to determine to output a read digital signal, and the read voltage is an output voltage of a read memory cell. The problem that a large-capacity ROM read-only memory is low in reading speed and prone to misreading due to the fact that the load is high in the prior art is solved.

A storage array, a memory, a reading method thereof, and an electronic device are disclosed. The storage array includes multiple storage cell subarrays, a reference cell column, and a set of reference voltage generation circuits, reference cell switching circuits, and read word line control circuits. The storage cell subarrays and reference cell column in two storage arrays are electrically connected via read bit lines and symmetrically distributed around a read decision unit. The transistors of the reference cells and storage cells are isomorphic and have the same circuit structure. The memory includes at least one pair of open storage arrays, each pair comprising a first storage array, a second storage array, and a set of read decision units. Each storage array is electrically connected to one of the two input terminals of the read decision unit. During reading, the two storage arrays provide a read voltage and a reference voltage, respectively. The two input terminals of the read decision unit have similar RC parameters, and the drift generated by the voltages at the two input terminals is also matched. This application improves storage density and data reading reliability.

The embodiment of the invention provides a memory and an operation method thereof, relates to the technical field of storage, and realizes a simultaneous read-write function of the memory. According to the specific scheme, the memory comprises a time schedule controller, a memory array, a plurality of writing word lines, a plurality of reading word lines, a plurality of writing bit lines and a plurality of reading bit lines. The storage array comprises a plurality of storage units, the storage units located in the same row are coupled with the same writing word line and the same reading word line, and the storage units located in the same column are coupled with the same writing bit line and the same reading bit line. The time schedule controller is configured to apply a writing line voltage to a writing line corresponding to a first storage unit in the plurality of storage units in any clock period, and the writing line voltage is greater than the word line voltage. The time schedule controller is further configured to apply a read word line voltage to a read word line corresponding to a second storage unit in the plurality of storage units in a clock period, and the first storage unit and the second storage unit are storage units in different rows.

This application provides a storage circuit, a storage chip, and an electronic device. The storage circuit includes a sub-read circuit, read bit lines, at least one read auxiliary unit, and multiple static random access memory (SRAM) cells. The read bit lines are connected to the sub-read circuit, the at least one read auxiliary unit, and the multiple SRAM cells. The sub-read circuit performs read operations through the multiple SRAM cells. The read auxiliary unit is obtained by updating the circuit connections of the SRAM cells and is used to adjust the potential of the read bit lines. This not only improves the success rate of reading 1 operations and accelerates the speed of reading 0 operations, but also avoids excessive area overhead in the storage circuit.

The present disclosure provides a memory device, which includes a memory array, a read-clock generation circuit, and a local input / output circuit. The read-clock generation circuit receives a sense amplifier enable signal, a first sense amplifier pre-charge signal, and a latched write enable signal to generate a first read enable signal. The local input / output circuit includes multiple pairs of column-address pass gates, and a pair of read pass gates. The plurality of pairs of column-address pass gates are configured to receive data from a bit-line pair of the memory cells in a row selected by an address signal. The pair of read pass gates connects a read bit-line pair to the bit-line pair in response to the first read enable signal being in a low-logic state. The first read enable signal is de-asserted after the read bit-line pair connected to the pair of read pass gates are pre-charged.

The invention relates to a semiconductor device and an operating method thereof. A semiconductor device including one or more memory cells and a method of operating the same are disclosed. Each memory cell includes: a first transistor configured to write data; a second transistor configured to store data; and a third transistor configured to refresh data. The memory cell includes: a first transistor including a first gate connected to a write word line and one terminal connected to a memory node; a second transistor including a second gate connected to the storage node and one terminal connected to a read word line; and a third transistor including a third gate connected to the read word line and one terminal connected to the read bit line.

The invention discloses a three-dimensional fast read memory based on IGZO and a storage and calculation framework, and relates to the technical field of circuit design. The framework comprises a storage layer formed by stacking L layers of IGZO-3T0C arrays and used for storing target data, each layer of IGZO-3T0C array comprises a plurality of storage units, and L is a positive integer larger than 1; the discharge layer is composed of an IGZO array, is connected with the storage layer through a read bit line, and is used for carrying out discharge initialization on a read-out intermediate node in a to-be-read storage unit in the early stage of read operation; and the read-out layer consists of a CMOS (Complementary Metal Oxide Semiconductor) array, is connected with the storage layer through a read bit line, and is used for reading out the target data. According to the framework, the reading speed and the integration density can be improved, and the problems of electric leakage and crosstalk occurring after a reading layer is added to a traditional three-dimensional array composed of 2T0C units are solved, so that the energy efficiency is improved.

Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a first source / drain feature and a second source / drain feature. The semiconductor structure also includes a first plurality of metal lines comprising a write bit line and a complementary write bit line, wherein the first plurality of metal lines are positioned at a first metal interconnect layer, wherein the first metal interconnect layer is disposed over the first source / drain feature. The semiconductor structure also includes a read bit line positioned at a second metal interconnect layer, where the second metal interconnect layer is disposed under the first source / drain feature.

The invention discloses a semiconductor structure, a method for forming the same, and a three-dimensional memory, the semiconductor structure comprising: a substrate having a read word line and a read bit line; a read transistor, the read transistor comprising a first channel layer and a first gate layer, the first channel layer at least partially surrounding the first gate layer from the bottom to the top of the first gate layer, the read transistor being coupled to the read word line and the read bit line respectively; a write word line and a write bit line; a write transistor, the write transistor being located on the read transistor, the write transistor comprising a second channel layer and a second gate layer, the second channel layer at least partially surrounding the second gate layer from the bottom to the top of the second gate layer, the write transistor being coupled to the write bit line, the write word line, and the first gate layer respectively. According to the semiconductor structure of the embodiment of the present invention, the control capability and integration can be improved, which is conducive to further miniaturization.

A storage system and circuits therefor. A storage system includes a bitcell array comprising a plurality of storage cells arranged in one or more columns and one or more rows; a read bitline associated with a first column to access storage cells of the first column, wherein the read bitline has a first keeper circuit coupled thereto; and a tracker bitline associated with the read bitline, wherein the tracker bitline has a second keeper circuit coupled thereto, and wherein the tracker bitline is configured such that a behaviour thereof is to substantially match a behaviour of the read bitline.

The present application relates to temperature tracking dynamic keeper for implementing read operations. A static random access memory (SRAM) system includes a plurality of SRAM memory cells, each of the plurality of SRAM memory cells coupled to a respective read bit line, and a dynamic keeper coupled to the read bit line. The dynamic keeper includes a first keeper supporting read operations for a first temperature range and a second keeper supporting read operations for a second temperature range, and a temperature sensitive control circuit that selects the first keeper or the second keeper based on temperature.

The present disclosure relates to a memory cell, a memory structure, and a method for preparing the same. The memory cell comprises: a write transistor comprising a write word line, a write gate dielectric layer, and a write channel layer, wherein the write word line extends in a first direction, the write gate dielectric layer is located on the sidewall of the write word line, and the write channel layer is located on the sidewall of the write gate dielectric layer; a shared wire extending in a third direction; a first electrode arranged along the first direction with the shared wire, the first electrode and the shared wire being located on the same side of the write channel layer; a read transistor comprising a read gate dielectric layer, a read channel layer, and a read bit line, the read gate dielectric layer being located between the shared wire and the first electrode and extending to the sidewall of the first electrode, the read channel layer comprising a read channel portion, the read channel portion being located on the sidewall of the read gate dielectric layer, and one end of the read channel portion being connected to the shared wire and the other end being connected to the read bit line. The present disclosure can effectively improve storage density in an embodiment.

The invention relates to an in-memory computing unit, an operation method thereof and an in-memory computing array. The in-memory computing unit comprises a write transistor, a read transistor and a nonvolatile memory, a first electrode of the write transistor is connected with a grid electrode of the read transistor to form a storage node, a second electrode of the write transistor is connected to a write bit line, and the grid electrode is connected to a write word line; a first electrode of the read transistor is connected to a read word line, and a second electrode is connected with a first electrode of the nonvolatile memory; a second electrode of the non-volatile memory is connected to the read bit line. By integrating a write transistor, a read transistor, and a non-volatile memory, cell area overhead can be reduced.

The capacitor-free memory includes: a substrate; an isolation layer; a read bit line layer; a columnar first stack on an upper surface of the read bit line layer which including a first channel layer, a read word line layer, and a first hard mask layer; a first gate dielectric layer surrounding a side surface and an upper surface of the first stack, and the upper surface of the read bit line layer; a first gate layer covering a surface of the first gate dielectric layer; a columnar second stack on an upper surface of the first gate layer which including a second channel layer, a write bit line layer, and a second hard mask layer; a second gate dielectric layer surrounding a side surface of the second stack, an upper surface of the second stack, and the upper surface of the first gate layer; and a second gate layer.

A non-volatile magnetoresistive random-access memory device is provided. The device comprises a three-terminal spin-orbit torque magnetic tunnel junction (MTJ) with perpendicular anisotropy. The MTJ comprises a fixed ferromagnetic layer, a free ferromagnetic layer, a tunnel barrier between the fixed and free ferromagnetic layers, and a heavy metal layer under the free ferromagnetic layer. A read access transistor is connected to a first terminal of the fixed magnetic layer. A write access transistor is connected to a second terminal of the heavy metal layer. A ground voltage is connected to a third terminal of the heavy metal layer. A read bit line is connected to the read access transistor, and a read word line is connected to the gate of the read access transistor. A write bit line is connected to the write access transistor, and a write word line is connected to the gate of the write access transistor.

A semiconductor memory device includes a write bit line and a read word line extending in a first horizontal direction and spaced apart from each other in a second horizontal direction, a write word line, a read bit line, and a source line between the write bit line and the read word line and extending in a vertical direction and being spaced apart in the first horizontal direction, a capacitor electrode having a first portion and a second portion, a capacitor dielectric layer, a first gate dielectric layer covering a side surface of the first portion, a first channel layer covering the first gate dielectric layer, a second gate dielectric layer covering a portion of a side surface of the write word line, and a second channel layer connected to the second portion of the capacitor electrode and to the write bit line and covering the second gate dielectric layer.

A configurable operation unit in a memory is provided, including a first input transistor, a first weight transistor, a first resistor, a second input transistor, a second weight transistor, and a second resistor. The first input transistor, the first weight transistor, and the first resistor are coupled in series between a first read bit line and a common signal line, wherein the first input transistor is coupled to a first input bit line, and the first weight transistor receives a first weight bit. The second input transistor, the second weight transistor, and the second resistor are coupled in series between the first read bit line and the common signal line, wherein the second input transistor is coupled to a second input bit line, and the second weight transistor receives a second weight bit.

This invention provides an in-memory computing system, method, and chip that supports fully parallel computation of deep convolution channels. The system includes: a parallel computing module comprising k×k multi-bit data units, each multi-bit data unit comprising q storage sub-units for storing k×k q-bit activation value storage data, and performing simulated multiplication and accumulation operations on the k×k q-bit activation value storage data and input weight parameters of size (k×k,1); a weight configuration circuit connected to the parallel computing module, used to perform bit-level simulation recombination of the q-bit weights in the simulated multiplication and accumulation operation output by the parallel computing module, obtaining a simulated multiplication and accumulation result of 1-bit input weight parameters and q-bit activation value storage data; an ADC quantization circuit connected to the weight configuration circuit, used to quantize the simulated multiplication and accumulation result, obtaining integer data output; and an activation value update circuit connected to the bit line and read bit line of the column where the parallel computing module is located, used to perform local cyclic updates of the activation value storage data within the parallel computing module. This invention can increase the parallelism of array computation and realize local cyclic updates of activation values ​​within the array, thereby improving energy efficiency.

A memory and an access control method therefor, and an electronic device. The memory comprises: at least one storage array layer and a plurality of common bit lines (CBL) having one-to-one correspondence to each storage array layer. Each storage array layer comprises a plurality of read bit lines (BLr) and a plurality of write bit lines (BLw) extending in a first direction parallel to a substrate. The read bit lines (BLr) and the write bit lines (BLw) on the same layer are connected to a corresponding common bit line (CBL). Each write bit line (BLw) is connected to a corresponding common bit line (CBL) by means of a first write gating sub-circuit (11), and each read bit line (BLr) is connected to a corresponding common bit line by means of a first read gating sub-circuit (12). The first write gating sub-circuit (11) is further connected to a first write gating control line, and is configured to connect / disconnect the write bit line to / from the common bit line under the control of the first write gating control line. The first read gating sub-circuit (12) is further connected to a first read gating control line, and is configured to connect / disconnect the read bit line to / from the common bit line under the control of the first read gating control line.

A memory device includes: a first static random access memory (SRAM) cell that has: a first write-port pull-up (PU) transistor and a second write-port PU transistor arranged in a first direction; and a first read-port pull-down (PD) transistor and a first read-port pass-gate (PG) transistor. The memory device includes a second SRAM cell that has: a third write-port PU transistor and a fourth write-port PU transistor arranged in the first direction; and a second read-port PD transistor and a second read-port PG transistor. The memory device includes a first metal layer over the first SRAM cell and the second SRAM cell. The first metal layer includes a read bit-line conductor extending in the first direction and shared by the first SRAM cell and the second SRAM cell. The first read-port PD transistor and the second read-port PD transistor are arranged in the first direction.