20 results about "Read bit line" patented technology

A storage array, a memory, a reading method thereof, and an electronic device are disclosed. The storage array includes multiple storage cell subarrays, a reference cell column, and a set of reference voltage generation circuits, reference cell switching circuits, and read word line control circuits. The storage cell subarrays and reference cell column in two storage arrays are electrically connected via read bit lines and symmetrically distributed around a read decision unit. The transistors of the reference cells and storage cells are isomorphic and have the same circuit structure. The memory includes at least one pair of open storage arrays, each pair comprising a first storage array, a second storage array, and a set of read decision units. Each storage array is electrically connected to one of the two input terminals of the read decision unit. During reading, the two storage arrays provide a read voltage and a reference voltage, respectively. The two input terminals of the read decision unit have similar RC parameters, and the drift generated by the voltages at the two input terminals is also matched. This application improves storage density and data reading reliability.

This application provides a storage circuit, a storage chip, and an electronic device. The storage circuit includes a sub-read circuit, read bit lines, at least one read auxiliary unit, and multiple static random access memory (SRAM) cells. The read bit lines are connected to the sub-read circuit, the at least one read auxiliary unit, and the multiple SRAM cells. The sub-read circuit performs read operations through the multiple SRAM cells. The read auxiliary unit is obtained by updating the circuit connections of the SRAM cells and is used to adjust the potential of the read bit lines. This not only improves the success rate of reading 1 operations and accelerates the speed of reading 0 operations, but also avoids excessive area overhead in the storage circuit.

An in-memory computing system is provided in which a plurality of in-memory computing bit cells are coupled to a read bit line. Current from the read bit line is sequentially increased in accordance with a sequential binary multiplication in the in-memory computing bit cells. A transition detection circuit detects and counts current transitions to provide a multiplication and accumulation result from the sequential binary multiplication.

Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a first source / drain feature and a second source / drain feature. The semiconductor structure also includes a first plurality of metal lines comprising a write bit line and a complementary write bit line, wherein the first plurality of metal lines are positioned at a first metal interconnect layer, wherein the first metal interconnect layer is disposed over the first source / drain feature. The semiconductor structure also includes a read bit line positioned at a second metal interconnect layer, where the second metal interconnect layer is disposed under the first source / drain feature.

This invention provides an in-memory computing system, method, and chip that supports fully parallel computation of deep convolution channels. The system includes: a parallel computing module comprising k×k multi-bit data units, each multi-bit data unit comprising q storage sub-units for storing k×k q-bit activation value storage data, and performing simulated multiplication and accumulation operations on the k×k q-bit activation value storage data and input weight parameters of size (k×k,1); a weight configuration circuit connected to the parallel computing module, used to perform bit-level simulation recombination of the q-bit weights in the simulated multiplication and accumulation operation output by the parallel computing module, obtaining a simulated multiplication and accumulation result of 1-bit input weight parameters and q-bit activation value storage data; an ADC quantization circuit connected to the weight configuration circuit, used to quantize the simulated multiplication and accumulation result, obtaining integer data output; and an activation value update circuit connected to the bit line and read bit line of the column where the parallel computing module is located, used to perform local cyclic updates of the activation value storage data within the parallel computing module. This invention can increase the parallelism of array computation and realize local cyclic updates of activation values ​​within the array, thereby improving energy efficiency.

This invention provides a memory device and a memory array. The memory device includes memory cells. Each memory cell includes a first switching element, a second switching element, and a storage element. The first switching element is used to receive a write bit line signal and is coupled to a storage node. The second switching element is used to receive a read bit line signal and is coupled to the storage node. The storage element is coupled to the storage node and is used to receive a voltage signal and store a first data bit, wherein the memory cell is used to store a second data bit, different from the first data bit, in the storage node.

This disclosure provides a voltage configuration method for a memory array, applicable to the field of circuit technology. The method includes: configuring the write word line and the write bit line to a first voltage in response to a read operation, such that the write transistor is in a turned-off state; configuring the read bit line to a second voltage, the second voltage being greater than the first voltage; determining a selection state of the read word line of the memory array, the selection state indicating whether a memory cell associated with the read word line performs a read operation; and configuring the voltage of the read word line according to the selection state and the second voltage to control the conduction state of the read transistor.

Each latch cell in a latch cell array is made of 12 MOS transistors including a first CMOS switch transferring write data and a second CMOS switch transferring read data. A test for rewriting a storage node on a write bit line side in each latch cell from a first logic level to a second logic level in a state in which the first and second CMOS switches are respectively controlled to be on in overlapping time periods is assumed. In this case, a disturb test circuit precharges a read bit line to the second logic level before the second CMOS switch is controlled to be on.

The application provides an access circuit and a storage unit circuit. The access circuit comprises a first transistor and a second transistor. A first end of the first transistor is coupled to a read bit line. A second end of the first transistor is coupled to a read source line. A first end of the second transistor is coupled to a write bit line. A second end of the second transistor is coupled to a gate end of the first transistor as a storage end point. A gate end of the second transistor is coupled to a write word line. A base end of the first transistor is coupled to the gate end of the first transistor.

A semiconductor memory cell structure and method of fabricating same structure includes one or more bit cells including a stacked read transistor and write transistor, each bit cell further including read bit line(s), read word line(s), write bit line(s), write word line(s), and a storage node isolated from other bit cell structures. The bit cell(s) further include a read word line to storage node voltage coupler structure which is proximately located near the read word line and storage node, and the voltage coupler is configured as a winged gate or a wraparound read word line.

A memory cell, a data read-write circuit, a memory, and a memory manufacturing method are provided. The memory cell includes: a horizontal semiconductor layer extending along a first direction, and a write bit line, a write transistor, a read transistor, and a read word line which are located on the horizontal semiconductor layer and sequentially arranged along the first direction. The write bit line and the read word line each extend along a second direction intersecting the first direction. The read transistor extends along a third direction perpendicular to the first direction and the second direction and penetrates through the horizontal semiconductor layer. A source line, the read transistor, and a read bit line are arranged along the third direction. Simultaneous photolithography of multiple layers of stacked memory cells can be supported and meanwhile an area overhead of a single layer of memory cells is reduced.

A sensing circuit and a control method of the sensing circuit are provided. The sensing circuit includes a data line, a complementary data line, a read bit line, a complementary read bit line, a read pass gate circuit and logic circuit. The logic circuit enables the read pass gate circuit when a voltage level on the read bit line and a voltage level on the complementary read bit line are pre-charged to a first voltage level, and disable the read pass gate circuit when one of the voltage level on the read bit line and the voltage level on the complementary read bit line is pull to a second voltage level different from the first voltage level. The read pass gate circuit is enabled to connect the data line to the read bit line and connect the complementary data line to the complementary read bit line.

A non-volatile magnetoresistive random-access memory device is provided. The device comprises a three-terminal spin-orbit torque magnetic tunnel junction (MTJ) with perpendicular anisotropy. The MTJ comprises a fixed ferromagnetic layer, a free ferromagnetic layer, a tunnel barrier between the fixed and free ferromagnetic layers, and a heavy metal layer under the free ferromagnetic layer. A read access transistor is connected to a first terminal of the fixed magnetic layer. A write access transistor is connected to a second terminal of the heavy metal layer. A ground voltage is connected to a third terminal of the heavy metal layer. A read bit line is connected to the read access transistor, and a read word line is connected to the gate of the read access transistor. A write bit line is connected to the write access transistor, and a write word line is connected to the gate of the write access transistor.

An electrical device including a memory circuit and a general input output circuit. The memory circuit includes bit-cell circuits, each bit-cell circuit including a memory cell and a read port. The memory cell is electrically connected to a read word line at a read output voltage and is electrically connected to the read port by the read word line. The read port is further connected to a read bit-line complement signal at a write output logic voltage or at a read bit-line complement output voltage that is less than or equal to the write output logic voltage. The general input output circuit includes a bit-line pre-charge control circuit and a voltage level shifter circuit, wherein the read bit-line complement signal is connected to the bit-line pre-charge control circuit and to the voltage level shifter circuit.

Disclosed are an access circuit and a memory cell circuit. The access circuit includes a first transistor and a second transistor. A first end of the first transistor is coupled to a read bit-line. A second end of the first transistor is coupled to a read source line. A first end of the second transistor is coupled to a write bit-line. A second end of the second transistor is coupled to a gate terminal of the first transistor to serve as the storage endpoint. A gate terminal of the second transistor is coupled to the write word-line. A base terminal of the first transistor is coupled to the gate terminal of the first transistor.

A spin-orbit torque magnetic memory circuit and layout thereof are provided, wherein the spin-orbit torque magnetic memory circuit includes a read transistor pair having two parallel read transistors, a write transistor pair having two parallel write transistors, a spin-orbit torque magnetic memory cell having a magnetic tunnel junction and a spin-orbit torque layer, wherein one end of the magnetic tunnel junction is connected to a source of the read transistor pair and the other end is connected to the spin-orbit torque layer, one end of the spin-orbit torque layer is connected to a source line and the other end is connected to a source of the write transistor pair, a read bit line connected to drains of the read transistor pair, and a write bit line connected to drains of the write transistor pair.

This invention discloses apparatus and methods for providing efficient planar planning, power, and performance tradeoffs for memory access. Dual-read-port and single-write-port memory bit cells use two asymmetric read access circuits to transfer stored data on two read bit lines. The two read bit lines are pre-charged to different voltage reference levels. The layout of the memory bit cell places the two read bit lines on edges opposite to the single write bit line. The layout uses dummy gates placed above both P-type and N-type diffusions between these edges. Despite using asymmetric read access circuitry, the layout has the same number of P-type transistors as the N-type transistors. The layout also has one more contact gate pitch than the number of P-type transistors.

A static random access memory (SRAM) integrated circuit comprises a plurality of PMOS and NMOS transistors connected to a first storage node and a second storage node. The PMOS transistors are fabricated in an upper layer of the integrated circuit and the NMOS transistors are fabricated in a lower layer of the integrated circuit. A voltage supply rail, a write word line, a read bit line and a read word line are formed in the upper layer. A ground rail, a write bit line and a complementary write bit line are formed in the lower layer.

This disclosure relates to a memory cell, a memory, a method for fabricating the same, and an electronic device, relating to the field of storage technology, to improve the performance and reliability of the memory cell and the memory. The memory cell includes a write transistor and a read transistor. The write transistor includes a first gate, a first source-drain, and a second source-drain. The read transistor includes a second gate, a third source-drain, and a fourth source-drain. The first gate is electrically connected to the write word line, the first source-drain is electrically connected to the write bit line, and the second source-drain and the second gate are electrically connected. The read transistor further includes a third gate, insulated on one side of the connection between the second source-drain and the second gate. The third gate is electrically connected to the read word line, the fourth source-drain is electrically connected to the read bit line, and the third source-drain is electrically connected to the common source line.

A circuit includes a Vdd node, and a two-port Static Random-Access Memory (SRAM) cell pair having a first SRAM cell and a second SRAM cell having a same structure. The first SRAM cell is a ten-transistor SRAM cell that comprises a first pull-up transistor and a second pull-up transistor, a first pull-down transistor and a second pull-down transistor forming a latch with the first pull-up transistor and the second pull-up transistor, a first pass-gate transistor and a second pass-gate transistor connecting to the latch, a p-type isolation transistor including a first source / drain region connecting to a drain region of the first pull-up transistor, and a gate connecting to the Vdd node. The circuit further includes a read bit-line shared with the second SRAM cell. and a write bit-line pair connecting to gates of the first pass-gate transistor and the second pass-gate transistor.