Sense amplifier, operating method thereof, and memory

Abstract

The embodiment of the invention relates to the field of memories, and provides a sense amplifier which at least comprises a first transistor electrically connected between a first power supply node and a complementary read bit line, and the control end of the first transistor is connected to the control end of a third transistor; the second transistor is electrically connected between the second power supply node and the reading bit line, and the control end of the second transistor is connected to the control end of the fourth transistor; a third transistor electrically connected between the complementary read bit line and a third power supply node; a fourth transistor electrically connected between the read bit line and a fourth power supply node; the first calibration tube is connected between the complementary reading bit line and the control end of the third transistor; wherein the first power supply node is connected to a first power supply voltage through the first switching element; the second power supply node is connected to the first power supply voltage through the second switching element; the third power supply node is connected to a second power supply voltage through a third switching element; the fourth power supply node is connected to the second power supply voltage through a fourth switching element.

Description

Technical Field

[0001] This application relates to the field of memory, and more particularly to a memory that includes a sensing amplifier. Background Technology

[0002] During the operation of a sense amplifier (SA), insufficient sensing margin can lead to errors in the sensing amplification process, resulting in read / write data errors. Currently, the industry mainstream uses offset-cancellation sense amplifiers (OCSA) to compensate for the sensing margin loss caused by device mismatch, thereby improving the sensing margin of the sense amplifier.

[0003] Offset-canceling sense amplifiers compensate for the sensing margin loss caused by device mismatch in sense amplifiers. However, device mismatch is only one factor in the sensing margin loss, and the reduction in sensing margin loss resulting from reducing device mismatch is limited. Furthermore, in advanced manufacturing processes or product architecture designs, the proportion of other sensing margin loss factors also increases. Summary of the Invention

[0004] This application provides a sensing amplifier, a method for operating the sensing amplifier, and a memory containing the sensing amplifier, which at least helps to solve the problem of insufficient sensing margin of the sensing amplifier.

[0005] According to some embodiments of this application, one aspect of this application provides a sensing amplifier, including:

[0006] The first transistor is electrically connected between the first power node and the complementary read bit line, and its control terminal is connected to the control terminal of the third transistor.

[0007] The second transistor is electrically connected between the second power node and the read bit line, and its control terminal is connected to the control terminal of the fourth transistor.

[0008] The third transistor is electrically connected between the complementary readout bit line and the third power node;

[0009] The fourth transistor is electrically connected between the read bit line and the fourth power node;

[0010] The first calibration tube is connected between the complementary readout bit line and the control terminal of the third transistor;

[0011] The first power node is connected to the first power supply voltage via a first switching element; the second power node is connected to the first power supply voltage via a second switching element.

[0012] The third power node is connected to the second power supply voltage via a third switching element; the fourth power node is connected to the second power supply voltage via a fourth switching element.

[0013] According to some embodiments of this application, another aspect of this application also provides a method for operating a sensing amplifier, for operating the sensing amplifier as described in the first aspect, the method comprising:

[0014] Perform a pre-charge operation to pre-charge the bit line, the read bit line, the complementary bit line, and the complementary read bit line to a preset voltage;

[0015] Perform a calibration operation to calibrate the voltages at the input and output terminals of the inverter formed by the first and third transistors to the same voltage.

[0016] Perform a charge sharing operation to enable charge sharing between the memory cell and the bit line;

[0017] Perform a pre-amplification operation to transfer the voltage at the input of the inverter formed by the first and third transistors to the complementary bit line;

[0018] A sensing amplification operation is performed to amplify the voltage difference between the bit line and the complementary bit line.

[0019] According to some embodiments of this application, another aspect of this application provides a method for operating a sensing amplifier, used to operate a sensing amplifier including a cross-coupled first inverter and a second inverter, wherein the input terminal of the first inverter is connected to a bit line, and the input terminal of the second inverter is connected to a complementary bit line, the method comprising:

[0020] Perform a pre-charge operation to pre-charge all internal nodes of the sensing amplifier to a preset voltage;

[0021] Perform a calibration operation to calibrate the voltages at the input and output terminals of the first inverter to the same voltage;

[0022] Perform a charge sharing operation to enable charge sharing between the memory cell and the bit line;

[0023] Perform a pre-amplification operation to pre-amplify the voltage at the input terminal of the first inverter and transmit it to the complementary bit line;

[0024] A sensing amplification operation is performed to amplify the voltage difference between the bit line and the complementary bit line.

[0025] According to some embodiments of this application, another aspect of this application provides a memory, the memory including a plurality of sensing amplifiers as described in the first aspect, and a plurality of storage cells, wherein the sensing amplifiers are connected to the storage cells via bit lines.

[0026] The technical solution provided in this application has at least the following advantages: The sensing amplifier of this application includes two independently controllable inverters, and the input and output terminals of the first inverter are connected through a first calibration tube. Based on this circuit, the input and output of the inverter can be short-circuited, thereby enabling the utilization of the inverter's flip point. The flip point is used to further amplify the bit line sensing voltage, amplify the small charge-sharing voltage value, and thus improve the sensing margin of the sensing amplifier, which helps to improve the chip yield. Attached Figure Description

[0027] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0028] Figure 1 This is a schematic diagram of the structure of a memory.

[0029] Figure 2 This is a schematic diagram of a storage array structure;

[0030] Figure 3 A schematic diagram of the circuit structure of a sensing amplifier provided in an embodiment of this application;

[0031] Figure 4 A schematic diagram of another sensing amplifier circuit structure provided in an embodiment of this application;

[0032] Figure 5 A timing diagram of a sensing amplifier provided for an embodiment of this application;

[0033] Figure 6 A schematic diagram of the circuit structure of a sensing amplifier at each operating stage provided in an embodiment of this application;

[0034] Figure 7 A schematic diagram illustrating voltage changes during various operating stages of a sensing amplifier, provided as an embodiment of this application;

[0035] Figure 8 This is a schematic diagram of the circuit structure of another sensing amplifier provided in an embodiment of this application. Detailed Implementation

[0036] Hereinafter, exemplary embodiments of the present application will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily practice the present application. As will be appreciated by those skilled in the art, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present application. For example, the exemplary embodiments provided herein are thought to be implementable by combining them, in whole or in part. Specifically, an element described in a particular exemplary embodiment, even if not described in another exemplary embodiment, may be understood as a description relating to another exemplary embodiment, unless a contrary or contradictory description is provided therein.

[0037] Throughout this specification, when any part is referred to as being “connected” to another part, it includes both cases where any part and another part are “indirectly connected” to each other due to the presence of another part between them, and cases where any part and another part are “directly connected” to each other. For example, it should be understood that when an element is referred to as being “connected” or “linked” or “on another element” to another element, it may be directly connected or linked to or on that other element, or there may be an intermediate element present. Conversely, when an element is referred to as being “directly connected” or “directly linked” to another element, or referred to as being “in contact” or “in contact” with another element, there is no intermediate element at the point of contact (except for connecting wires such as metal wires). Furthermore, “electrical connection” conceptually includes both physical connection and physical disconnection.

[0038] It is understood that when an element is referred to using terms such as "first" and "second," the element is not subject to this limitation. These terms may be used solely for the purpose of distinguishing the element from other elements and may not limit the order or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element.

[0039] When a sense amplifier receives voltage (i.e., charge) during charge sharing, subtracting all sensing margin losses leaves a margin sufficient for successful data sensing and amplification; this margin is called the sensing margin. Sensing margin losses in a sense amplifier include losses such as recovery loss, sharing loss, array noise, and device mismatch. With advancements in manufacturing processes and increasingly smaller device sizes, device mismatch (such as PMOS and NMOS pair mismatches) accounts for a significant proportion. Existing offset-cancelled sense amplifiers (OCSA) can reduce margin losses caused by device mismatch, but this is only a part of the sensing margin loss. Even after improvements, a high probability of data errors remains, leading to slow improvements in memory yield. Furthermore, for advanced manufacturing processes and new product architecture designs (such as 3D DRAM), device mismatch is no longer the most critical factor affecting margin losses; for example, array noise accounts for an increasingly larger proportion of sensing margin losses, resulting in a weakening optimization capability of OCSA for sensing margin losses.

[0040] Based on this, this application provides a new sensing amplifier structure and its operation method. The sensing amplifier structure includes two independently controllable inverters, and the input and output terminals of the first inverter are connected through a first calibration tube. Based on this circuit, the input and output of the first inverter can be short-circuited, thereby enabling the utilization of the inverter's flip point. This flip point is used to further amplify the bit line sensing voltage, amplify the small charge-sharing voltage value, and amplify the voltage (charge amount) obtained during charge sharing, thereby improving the sensing margin of the sensing amplifier and helping to improve chip yield.

[0041] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0042] Taking DRAM (Dynamic Random Access Memory) as an example, such as Figure 1 As shown, a DRAM memory chip includes a data input / output buffer, input / output amplifiers, row decoders, column decoders, and a memory array. The data input / output buffer belongs to the peripheral circuitry, while the input / output amplifiers, row decoders, column decoders, and memory array belong to the array circuitry. Figure 2As shown, the memory array mainly consists of a memory array tile (MAT), a sense amplifier array composed of multiple sense amplifiers, and a sub-word line driver (SWD, not shown). The memory tile includes word lines (WL), bit lines (BL), and memory cells arranged in the array. Word lines in the memory array extend along the row direction, and bit lines extend along the column direction. The intersection of word lines and bit lines forms the memory cell of the memory array.

[0043] Each row address line is connected to multiple column address lines and memory cells. In order to detect the weak activation signal on the column address line, a sense amplifier is needed to amplify the signal. Figure 2 The illustration shows a dual-ended sense amplifier, one end of which is connected to a bit line BL of one memory pad and the other end to another bit line BL of another memory pad. The signal to be read is amplified by comparing the voltage difference between the two bit lines. It should be understood that, without conflicting with the inventive concept of this application, the technical solution of this application can also be applied to a single-ended sense amplifier.

[0044] Figure 2 The specific structure of the storage unit is also shown. Figure 2 Taking a DRAM memory cell with one transistor and one capacitor (1T1C) as an example, it should be understood that other types of memory cells, such as non-DRAM memory cells, or DRAM memory cells such as 2T0C, are also applicable to this invention.

[0045] Figure 3 This is a schematic diagram of a sensing amplifier provided in one embodiment of this application. Figure 3 As shown, the sensing amplifier includes: a first transistor M1, electrically connected between a first power node PCS1 and a complementary readout bit line SABLB, with its control terminal connected to the control terminal of a third transistor; a second transistor M2, electrically connected between a second power node PCS2 and a readout bit line SABLB, with its control terminal connected to the control terminal of a fourth transistor; a third transistor M3, electrically connected between the complementary readout bit line SABLB and the third power node NCS1; a fourth transistor M4, electrically connected between the readout bit line SABLB and the fourth power node NCS2; and a first calibration transistor M5, connected between the complementary readout bit line SABLB and the control terminal of the third transistor. The first power node PCS1 is connected to a first power supply voltage via a first switching element K1; the second power node PCS2 is connected to the first power supply voltage via a second switching element K2; the third power node NCS1 is connected to a second power supply voltage via a third switching element K3; and the fourth power node NCS2 is connected to the second power supply voltage via a fourth switching element K4.

[0046] In this embodiment, the first transistor M1 and the third transistor M3 can be connected as an inverter, with the gate serving as the input and the drain as the output. Similarly, the second transistor M2 and the fourth transistor M4 can also be connected as an inverter, with the gate serving as the input and the drain as the output. To avoid redundancy, in the following text of this embodiment, "first inverter" will refer to the inverter formed by the first transistor M1 and the third transistor M3, and "second inverter" will refer to the inverter formed by the second transistor M2 and the fourth transistor M4.

[0047] refer to Figure 3 The power supply terminals of the first inverter are connected to the first power node PCS1 and the third power node NCS1. The first power node PCS1 is connected to the first power supply voltage through the first switching element K1; the third power node NCS1 is connected to the second power supply voltage through the third switching element K3. The power supply terminals of the second inverter are connected to the second power node PCS2 and the fourth power node NCS2. The second power node PCS2 is connected to the first power supply voltage through the second switching element K2; the fourth power node NCS2 is connected to the second power supply voltage through the fourth switching element K4. Thus, the first to fourth power nodes are independent of each other and can be independently controlled by the first to fourth switching elements, thereby allowing the first and second inverters to be independently controlled in their switching states.

[0048] The control terminal of the first switching element receives the first switching signal SAP1, the control terminal of the second switching element receives the second switching signal SAP2, the control terminal of the third switching element receives the third switching signal SAN1, and the control terminal of the fourth switching element receives the fourth switching signal SAN2.

[0049] The first power supply voltage can be used to provide a high level, such as power supply voltages VCC and VDD, or a high level specifically for the memory array or sense amplifier; there are no restrictions here, and it is denoted as VARY. The second power supply voltage can be used to provide a low level, such as ground level or a negative voltage; there are no restrictions here, and it is denoted as VSS.

[0050] Continue to refer to Figure 3The first calibration transistor M5 is connected between the complementary readout bit line SABLB and the control terminal of the third transistor, thereby short-circuiting the input and output terminals of the first inverter. Since the first and second inverters can be independently controlled, and the input / output terminals of the first inverter can be short-circuited through the first calibration transistor M5, this circuit allows the first inverter to be turned on during a certain stage of the sense amplifier's operation for calibration, calibrating the voltages at the input and output terminals to their flip point. Based on the inverter's transition curve, the voltage at which its input voltage Vin equals its output voltage Vout is its flip point voltage. According to the inverter's transition curve, if the input voltage is higher than the flip point, the output voltage will decrease significantly; if the input voltage is lower than the flip point, the output voltage will increase significantly. If, after calibration, the sense amplifier performs charge sharing, causing a slight change in the voltage at the input terminal of the first inverter, then according to the inverter's transition curve, the voltage at the output terminal of the first inverter will be inverted and amplified, resulting in a larger voltage change. Therefore, in subsequent operations, the voltage difference that the sensing amplifier needs to amplify becomes larger, the sensing margin becomes larger, and thus the success rate of sensing amplification can be improved.

[0051] It should be noted that in some embodiments, the sensing amplifier is a single-ended sensing amplifier, and the first inverter is connected to the bit line BL. The bit line is connected to the memory cell and performs charge sharing operation with the memory cell. In other embodiments, the sensing amplifier is a single-ended sensing amplifier, and the second inverter is connected to the bit line BL. Alternatively, the first calibration transistor is connected between the input and output terminals of the second inverter. The bit line is connected to the memory cell and performs charge sharing operation with the memory cell, thereby amplifying the shared voltage through the flip point of the second inverter.

[0052] It is understood that in some embodiments, the sensing amplifier is a dual-ended sensing amplifier, with a first inverter connected to the bit line BL, which in turn connects to the memory cell for charge sharing. In other embodiments, the sensing amplifier is a dual-ended sensing amplifier, with a second inverter connected to the bit line BL. Alternatively or compatiblely, a second calibration transistor is connected between the input and output terminals of the second inverter. The bit line connects to the memory cell for charge sharing, thereby amplifying the shared voltage through the flip point of the second inverter.

[0053] In some embodiments, the first switching element K1 and the third switching element K3 can be turned on and off simultaneously, and the second switching element K2 and the fourth switching element K4 can be turned on and off simultaneously.

[0054] In some embodiments, the first to fourth switching elements may be common switching elements in the art, such as MOS transistors. This invention does not limit this; each switching element may be a simple MOS switch formed by a single transistor, or a switching module formed by multiple transistors. The first to fourth switching elements may be a combination of a simple MOS switch and a switching module.

[0055] In some embodiments, each sensing amplifier has a set of first to fourth switching elements K1-K4. In other embodiments, multiple sensing amplifiers may share a set of first to fourth switching elements K1-K4. For example, the first power node PCS1 of multiple sensing amplifiers is connected to the same first switching element K1, the second power node PCS2 of multiple sensing amplifiers is connected to the same second switching element K2, the third power node of multiple sensing amplifiers is connected to the same third switch NCS1, and the fourth power node NCS2 of multiple sensing amplifiers is connected to the same fourth switching element K4. This reduces the area required.

[0056] by Figure 3 For example, the first transistor M1 and the second transistor M2 can be PMOS transistors, and the third transistor M3 and the fourth transistor M4 can be NMOS transistors. The first switching element K1 and the second switching element K2 are PMOS transistors, and the third switching element K3 and the fourth switching element K4 are NMOS transistors.

[0057] Figure 3 In one embodiment, the first switching element K1 and the second switching element K2 are connected to the same first power supply voltage VARY, and the third switching element K3 and the fourth switching element K4 are connected to the same second power supply voltage VSS. It is understood that in other embodiments, the first switching element K1 may be connected to the first power supply voltage VARY1, and the second switching element K2 may be connected to a different first power supply voltage VARY2. The third switching element K3 may be connected to the second power supply voltage VSS1, and the fourth switching element K4 may be connected to a different second power supply voltage VSS2.

[0058] In some embodiments, such as Figure 4 As shown, the sensing amplifier further includes: a second calibration transistor M6, connected between the readout bit line SABL and the control terminal of the fourth transistor; a first isolation transistor M7, connected between the bit line BL and the readout bit line SABL; and a second isolation transistor M8, connected between the complementary bit line BLB and the complementary readout bit line SABLB.

[0059] It should be noted that, barring any conflicts, the various embodiments in this application can be combined with each other. For example, Figure 4The illustrated embodiment can also be used Figure 3 Compatible additional designs in the embodiments.

[0060] The second calibration transistor M6 is positioned between the readout bit line SABL and the control terminal of the fourth transistor, between the input and output terminals of the second inverter formed by the second transistor M2 and the fourth transistor M4. This allows the second inverter to utilize its flip point to invert and amplify the shared charge received at the input terminal, and then output it at the output terminal.

[0061] A first isolation transistor M7, whose gate receives an isolation signal, is connected between bit line BL and the read bit line SABL; a second isolation transistor M8 is connected between complementary bit line BLB and complementary read bit line SABLB. In some embodiments, the gate of the first isolation transistor M7 receives an isolation signal, and one of its source and drain is connected to bit line BL, while the other is connected to read bit line SABL; the gate of the second isolation transistor M8 receives an isolation signal, and one of its source and drain is connected to complementary bit line BLB, while the other is connected to complementary read bit line SABLB. The configuration of the first isolation transistor M7 and the second isolation transistor M8 allows the isolation signal to control whether the bit line and read bit line, and the complementary bit line and complementary read bit line are shorted.

[0062] In some embodiments, the gate of the second calibration transistor M6 receives the calibration signal CAL, one of its source and drain is connected to the readout bit line SABL, and the other is connected to the complementary bit line BL. The second calibration transistor M6 allows the sense amplifier to also be adapted to situations where the complementary bit line BLB shares charge with the memory cell. The input / output terminals of the second inverter formed by the second transistor M2 and the fourth transistor M4 can be shorted by the second calibration transistor M6. This circuit allows the second inverter to be turned on during a certain stage of the sense amplifier's operation for calibration, calibrating the voltages at the input and output terminals to their flip point. Based on the inverter's transition curve, the voltage at which its input voltage Vin equals its output voltage Vout is its flip point voltage. If, after calibration, the complementary bit line BLB shares charge with the memory cell, causing a slight change in the voltage at the input terminal of the second inverter, then according to the inverter's transition curve, the voltage at the output terminal of the second inverter will be inverted and amplified, resulting in a larger voltage change. Therefore, in subsequent operations, the voltage difference that the sensing amplifier needs to amplify becomes larger, the sensing margin becomes larger, and thus the success rate of sensing amplification can be improved.

[0063] In some embodiments, the first calibration transistor M5 can also receive the calibration signal CAL at its gate. Based on this design, the first calibration transistor M5 and the second calibration transistor M6 receive the same control signal at their gates, which can save the number of calibration signal lines CAL and reduce wiring complexity and chip area.

[0064] Continue to refer to Figure 4 In some embodiments, the sense amplifier may further include a pre-charge element for pre-charging the bit line BL, complementary bit line BLB, sense bit line SABL, and complementary sense bit line SABLB to a preset voltage, such as the pre-charge supply voltage VBLP, during the pre-charge phase. The pre-charge element may be as follows: Figure 4 As shown, it includes a precharge transistor M9, whose control terminal receives a precharge signal EQ. One end of its source and drain is connected to the precharge voltage VBLP, and the other end is connected to the complementary read bit line SABLB, or the read bit line SABL, or the bit line BL, or the complementary bit line BLB.

[0065] It is understood that in other embodiments, the pre-charge element may also include two pre-charge transistors, or multiple transistors such as three pre-charge transistors. For example, the pre-charge element may include two pre-charge transistors, one connected between the read bit line SABL and the complementary read bit line SABLB, with the control terminal receiving an equalization signal that may be the same as or different from the pre-charge signal; the other connected between the pre-charge power supply voltage VBLP and the complementary read bit line SABLB or the read bit line SABL, with the control terminal receiving the pre-charge signal. This invention does not limit this; any implementation of the pre-charge function is acceptable.

[0066] In some embodiments, the first transistor and the third transistor form a first inverter, and the switching point voltage of the first inverter is the same as the pre-charge power supply voltage VBLP. The switching point voltage of the first inverter can be adjusted by designing the threshold voltage and width-to-length ratio of the first and third transistors, thereby making the switching point voltage of the first inverter the same as the pre-charge power supply voltage VBLP. Based on this, if the calibration operation of the first inverter is performed after pre-charging, the inverter can quickly reach the switching point after pre-charging, shortening the calibration time and reducing the current consumed by the sensing amplifier.

[0067] Similarly, the second transistor and the fourth transistor form a second inverter, and the switching point voltage of the second inverter can also be the same as the pre-charge power supply voltage VBLP. The switching point voltage of the second inverter can be adjusted by designing the threshold voltage and width-to-length ratio of the second and fourth transistors, thereby making the switching point voltage of the second inverter the same as the pre-charge power supply voltage VBLP. Based on this, if the calibration operation of the second inverter is performed after pre-charging, the inverter can quickly reach the switching point after pre-charging, shortening the calibration time and reducing the current consumed by the sensing amplifier.

[0068] In some embodiments, Figure 3 The sensing amplifier of or 4 can be used as follows Figure 5 The operating method is shown. The operating method includes:

[0069] Step S1: Perform a pre-charge operation to pre-charge the bit line BL, read bit line SABL, complementary bit line BLB, and complementary read bit line SABLB to a preset voltage VBLP.

[0070] Specifically, at time T0, the precharge signal EQ is set to high, turning on the precharge element. Simultaneously, the calibration signal CAL and the isolation signal ISO are set to high, turning on all calibration transistors and isolation transistors. Furthermore, the first switch signal SAP1 and the second switch signal SAP2 are set to high, while the third switch signal SAN1 and the fourth switch signal SAN2 are set to low, turning off the first to fourth switch elements. Thus, during the T0-T1 time period, the bit line BL, the read bit line SABL, the complementary bit line BLB, and the complementary read bit line SABLB are precharged to a preset voltage VBLP through the precharge element.

[0071] Step S2: Perform a calibration operation to calibrate the voltages at the input and output terminals of the inverter formed by the first and third transistors to the same voltage.

[0072] Specifically, at time T1, the pre-charge components are turned off, all isolation transistors are turned off, and the calibration signal CAL is kept high. The first switch signal SAP1 is set low, the third switch signal SAN1 is set high, the second switch signal SAP2 is kept high, and the fourth switch signal SAN2 is kept low. This turns on the first calibration transistor M5, turns on the first and third switching elements K1 and K3, and turns off the second and fourth switching elements K2 and K4. Thus, at time T1, the first inverter composed of the first transistor M1 and the third transistor M3 is turned on, and its input and output terminals are connected through the first calibration transistor M5. During the T1-T2 time period, through the self-adjustment of the inverter, the voltages at the input and output terminals of the inverter formed by the first and third transistors are calibrated to the same switching point voltage. Simultaneously, the second inverter formed by the second transistor M2 and the fourth transistor M4 is turned off to prevent additional current from flowing through the second inverter, which could cause calibration errors and wasted power.

[0073] Those skilled in the art will understand that, for a PMOS transistor, the PMOS transistor is turned on when the input signal at its control terminal is a low-level signal, and turned off when the input signal at its control terminal is a high-level signal. For an NMOS transistor, the NMOS transistor is turned on when the input signal at its control terminal is a high-level signal, and turned off when the input signal at its control terminal is a low-level signal.

[0074] Step S3: Perform a charge sharing operation to enable charge sharing between the memory cell and the bit line BL.

[0075] Specifically, at time T2, the first inverter is turned off by setting the first switch signal SAP1 to high and the third switch signal SAN1 to low; simultaneously, the calibration signal CAL is set to low, turning off the first calibration transistor M5; all isolation transistors and the second inverter remain off. At this time, the word line WL is set to high, turning on the transistor M10 of the memory cell, and sharing charge between the bit line and the memory cell's storage capacitor SN. After the charge sharing phase ends, the word line WL is set to low, turning off the transistor M10 of the memory cell. After charge sharing, the voltage on the bit line BL changes.

[0076] Step S4: Perform a pre-amplification operation to transfer the voltage at the input terminal of the inverter formed by the first transistor and the third transistor to the complementary bit line BLB.

[0077] Specifically, at time T3, the word line is turned off, and the first isolation transistor M7, the second isolation transistor M8, the first calibration transistor M5, the first switching element K1, and the third switching element K3 are turned on, thereby turning on the first inverter. The bit line BL voltage at the input of the first inverter is amplified by the inversion of the first inverter and then output to the second isolation transistor M8, and then transmitted to the complementary bit line BLB. Based on the inverter's transfer curve, the weak voltage change on the bit line is amplified by the inversion and output to the output terminal, and finally transmitted to the complementary bit line BLB, thereby realizing the pre-amplification of the voltage change, thus providing a sufficiently large voltage difference for subsequent sensing amplification.

[0078] In other embodiments, if step S3 is to share the complementary bit line BLB with the corresponding memory cell, then in steps S2 and S4, the second inverter formed by the first transistor and the third transistor and the second calibration transistor M6 are turned on respectively, and the voltage change on the complementary bit line BLB is inverted and amplified by the second inverter and then transmitted to the bit line BL.

[0079] Step S5: Perform a sensing amplification operation to amplify the voltage difference between the bit line and the complementary bit line.

[0080] Specifically, at time T4, all isolation transistors and the first inverter are kept on, the second inverter is turned on, and all calibration transistors are kept off, so that the first and second inverters form a cross-coupled amplifier to sense and amplify the voltage after pre-amplification in step S5. Due to the operations in the aforementioned steps, before the sense amplification operation, the voltage difference between the sense amplifier bit line BL and the complementary bit line BLB increases, the sense basis increases, and the sense margin increases, thereby improving the success rate of sense amplification.

[0081] In other implementations, the switching of the tubes in all the above steps may include pre-opening and pre-closing, without causing erroneous operation.

[0082] In some embodiments, step S5 may be followed by step S6, a write-back operation, in which the data read from the bit line is written back to the storage unit.

[0083] Figure 6 It shows Figure 5 Circuit diagrams showing the signals corresponding to each operational stage. Figure 7 The diagram shows the voltage changes on bit line BL, complementary bit line BLB, read bit line SABL, and complementary read bit line SABLB when bit line BL charge sharing is used and the data stored in the memory cell connected to bit line BL is "1".

[0084] Reference Figure 5 , Figure 6 and Figure 7During the pre-charge phase of S1, the sensing amplifier is pre-charged, and the voltages of bit line BL, complementary bit line BLB, readout bit line SABL, and complementary readout bit line SABLB are all pre-charged to VBLP.

[0085] During the S2 calibration phase, the power supply to the first inverter connected to BL is turned on, and the input and output terminals of the first inverter are shorted, making the input voltage Vin of the first inverter equal to the output voltage Vout, as follows. Figure 7 As shown, the voltages of bit line BL and complementary readout bit line SABLB stabilize at the flip point.

[0086] During the charge sharing phase of S3, the first and second inverters are not turned on. The bit line BL shares the charge with the memory cell. The voltage on the bit line BL is raised, and the voltage on the complementary read bit line SABLB remains at the flip point voltage. The voltages on the read bit line SABLB and the complementary bit line BLB remain unchanged.

[0087] During the pre-amplification stage of S4, the first inverter Inverter1 is turned on. Due to the inverter's transfer curve, the voltage on bit line BL is used as the input of the first inverter and is amplified in reverse to the output of the first inverter. Therefore, the voltage on the complementary read bit line SABLB drops rapidly, and drops more than the rise in the bit line BL voltage. Since all isolation transistors are turned on, bit line BL and read bit line SABLB reach the same potential, and complementary bit line BLB and complementary read bit line SABLB reach the same potential.

[0088] During the sensing amplification stage of S5, the first inverter Inverter1 and the second inverter Inverter2 are turned on, forming a cross-coupled structure connected end to end. The voltage difference on bit line BL, complementary bit line BLB, readout bit line SABL, and complementary readout bit line SABLB is further amplified and finally stabilized on data "0" and "1".

[0089] Through this circuit structure and operation method, since the first and second inverters can be independently controlled to open and close, and the input / output terminals of the first inverter can be shorted through the first calibration transistor M5, this circuit allows the first inverter to be turned on during the calibration phase of the sensing amplifier for calibration. The voltages at the input and output terminals are calibrated to their inversion points. If, after calibration, the sensing amplifier performs a charge-sharing operation, causing a slight change in the voltage at the input terminal of the first inverter, then according to the inverter's transfer curve, the voltage at the output terminal of the first inverter will be inverted and amplified, resulting in a larger voltage change. Therefore, in subsequent operations, the voltage difference that the sensing amplifier needs to amplify becomes larger, the sensing margin increases, and thus the success rate of sensing amplification can be improved.

[0090] This application also provides a method for operating a sensing amplifier, which can be applied to, for example... Figure 8 In the circuit structure shown, it should be noted that, under the premise of compatibility, Figure 8 The embodiments can also adopt the same and similar product designs as those in the previous embodiments, or the operation method of the sensing amplifier can be directly applied to the products in the previous embodiments.

[0091] In this embodiment, the operation method of the sensing amplifier is used to operate a sensing amplifier including a cross-coupled first inverter INV1 and a second inverter INV2, wherein the input terminal of the first inverter is connected to a bit line, and the input terminal of the second inverter is connected to a complementary bit line. The operation method includes:

[0092] Perform a pre-charge operation to pre-charge all internal nodes of the sensing amplifier to a preset voltage;

[0093] Perform a calibration operation to calibrate the voltages at the input and output terminals of the first inverter to the same voltage;

[0094] Perform a charge sharing operation to enable charge sharing between the memory cell and the bit line;

[0095] Perform a pre-amplification operation to pre-amplify the voltage at the input terminal of the first inverter and transmit it to the complementary bit line;

[0096] A sensing amplification operation is performed to amplify the voltage difference between the bit line and the complementary bit line.

[0097] According to the above method, during the calibration phase, after the voltages at the input and output terminals of the inverter are calibrated to the same voltage, a pre-amplification operation is added after the charge sharing ends. Since the input terminal of the inverter is connected to the bit line, the voltage change of the bit line will cause the same voltage change at the input terminal of the first inverter. According to the transfer curve of the inverter, the weak voltage change at the input terminal will be inverted and amplified at the output terminal. Thus, the first inverter amplifies the small voltage of charge sharing in reverse, thereby obtaining a larger charge sharing voltage value. This provides a better amplification basis for the sensing amplification in the sensing amplification stage, improves the sensing margin, reduces the probability of data reading and writing errors of the sensing amplifier, and improves the reliability of the memory.

[0098] Figure 8The diagram shows a first inverter INV1 and a second inverter INV2. Both INV1 and INV2 can be gated inverters, and their opening and closing are controlled by a control signal. Furthermore, this embodiment does not limit the number of PMOS and NMOS pairs in the inverters. The PMOS and NMOS pairs in the first inverter INV1 and the second inverter INV2 can be, as in the previous embodiment, a single pair of PMOS and NMOS transistors, or multiple pairs of PMOS and NMOS transistors.

[0099] Figure 8 The diagram illustrates a cross-coupled configuration of the first inverter INV1 and the second inverter INV2. Cross-coupling means that the outputs of the two inverters are connected to the inputs of the other, forming a feedback circuit structure. This cross-coupling can create a bistable circuit. Figure 8 In the example, the input terminal of the first inverter INV1 is connected to the output terminal of the second inverter INV2 through the first isolation transistor M7, and the input terminal of the second inverter INV2 is connected to the output terminal of the first inverter INV1 through the second isolation transistor M8.

[0100] Specifically, when performing a precharge operation, the internal nodes of the precharge may include bit line BL, complementary bit line BLB, read bit line SABL, and complementary read bit line SABLB, and the preset voltage of the precharge may include the precharge voltage VBLP.

[0101] Specifically, the sensing amplifier includes a first calibration tube M5 electrically connected between the input and output terminals of the first inverter INV1. During calibration, the first inverter INV1 is opened by the control signal of the gated inverter, and the voltages at the input and output terminals of the first inverter INV1 are calibrated to the same voltage by opening the first calibration tube M5.

[0102] In some embodiments, the sensing amplifier includes a first isolation transistor M7 connected between the input terminal of the first inverter and the output terminal of the second inverter, and a second isolation transistor M8 connected between the output terminal of the first inverter and the input terminal of the second inverter. During pre-amplification, since the input terminal of the first inverter INV1 is connected to the bit line BL, after the bit line BL shares charge with the memory cell during the charge sharing phase, the voltage at the input terminal of the first inverter INV1 also changes in the same way as the bit line BL. Therefore, during the pre-amplification phase, the voltage at the input terminal of the first inverter INV1 (i.e., the voltage on the bit line BL) can be pre-amplified. Then, through the activated first isolation transistor M7 and second isolation transistor M8, the voltage at the input terminal of the first inverter is pre-amplified and transmitted to the complementary bit line BLB. During sensing amplification, the first inverter INV1 and the second inverter INV2 are enabled by the control signal of the gated inverter, amplifying the voltage difference between the bit line BL and the complementary bit line BLB.

[0103] In some embodiments, this application also provides a memory comprising a plurality of sensing amplifiers as described in any of the preceding embodiments, and the memory further comprising a plurality of memory cells, wherein the sensing amplifiers are connected to the memory cells via bit lines BL. It is understood that in a single-ended sensing amplifier, the sensing amplifier is connected to the memory cell only via bit line BL and performs charge sensing and amplification. In a dual-ended sensing amplifier, the sensing amplifier is also connected to another memory cell via a complementary bit line BLB, and amplifies the signal by amplifying the voltage difference between bit line BL and the complementary bit line BLB.

[0104] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A sensing amplifier, characterized in that, include: The first transistor is electrically connected between the first power node and the complementary read bit line, and its control terminal is connected to the control terminal of the third transistor. The second transistor is electrically connected between the second power node and the read bit line, and its control terminal is connected to the control terminal of the fourth transistor. The third transistor is electrically connected between the complementary readout bit line and the third power node; The fourth transistor is electrically connected between the read bit line and the fourth power node; The first calibration tube is connected between the complementary readout bit line and the control terminal of the third transistor; The first power node is connected to the first power supply voltage via a first switching element; the second power node is connected to the first power supply voltage via a second switching element. The third power node is connected to the second power supply voltage via a third switching element; the fourth power node is connected to the second power supply voltage via a fourth switching element.

2. The sensing amplifier according to claim 1, characterized in that, Also includes: The second calibration tube is connected between the readout bit line and the control terminal of the fourth transistor; A first isolation transistor is connected between the bit line and the readout bit line; A second isolation transistor is connected between the complementary bit line and the complementary readout bit line.

3. The sensing amplifier according to claim 1 or 2, characterized in that, It also includes a pre-charge element configured to pre-charge the alignment line, the readout bit line, the complementary bit line, and the complementary readout bit line to a preset voltage; The first transistor and the third transistor form a first inverter, and the switching point voltage of the first inverter is the same as the preset voltage.

4. A method for operating a sensing amplifier, for operating the sensing amplifier as described in claim 2, the method comprising: Perform a pre-charge operation to pre-charge the bit line, the read bit line, the complementary bit line, and the complementary read bit line to a preset voltage; Perform a calibration operation to calibrate the voltages at the input and output terminals of the inverter formed by the first and third transistors to the same voltage. Perform a charge sharing operation to enable charge sharing between the memory cell and the bit line; Perform a pre-amplification operation to transfer the voltage at the input of the inverter formed by the first and third transistors to the complementary bit line; A sensing amplification operation is performed to amplify the voltage difference between the bit line and the complementary bit line.

5. The operating method according to claim 4, characterized in that, Performing the calibration operation includes: turning on the first calibration tube, the first switching element, and the third switching element, and calibrating the voltages at the input and output terminals of the inverter formed by the first transistor and the third transistor to the same voltage.

6. The operating method according to claim 4, characterized in that, Performing the pre-amplification operation includes: turning on the first isolation transistor, the second isolation transistor, the first switching element, and the third switching element; pre-amplifying the voltage at the input terminal of the inverter formed by the first transistor and the third transistor and transmitting it to the complementary bit line.

7. A method of operating a sensing amplifier, for operating a sensing amplifier comprising a first inverter and a second inverter with cross-coupled components, wherein, The input terminal of the first inverter is connected to a bit line, and the input terminal of the second inverter is connected to a complementary bit line. The operation method includes: Perform a pre-charge operation to pre-charge all internal nodes of the sensing amplifier to a preset voltage; Perform a calibration operation to calibrate the voltages at the input and output terminals of the first inverter to the same voltage; Perform a charge sharing operation to enable charge sharing between the memory cell and the bit line; Perform a pre-amplification operation to pre-amplify the voltage at the input terminal of the first inverter and transmit it to the complementary bit line; A sensing amplification operation is performed to amplify the voltage difference between the bit line and the complementary bit line.

8. The operating method according to claim 7, characterized in that, The sensing amplifier includes a first calibration tube electrically connected between the input and output terminals of the first inverter. The calibration operation includes: turning on the first calibration tube and energizing the first inverter to calibrate the voltages at the input and output terminals of the first inverter to the same voltage.

9. The operating method according to claim 8, characterized in that, The sensing amplifier includes a first isolation transistor connected between the input terminal of the first inverter and the output terminal of the second inverter, and a second isolation transistor connected between the output terminal of the first inverter and the input terminal of the second inverter. Performing the pre-amplification operation includes: turning on the first isolation transistor, the second isolation transistor, and the first calibration transistor, and energizing the first inverter to pre-amplify the voltage at the input terminal of the first inverter and transmit it to the complementary bit line.

10. A memory, characterized in that, The memory includes a plurality of sensing amplifiers as described in any one of claims 1-3, and further includes a plurality of storage cells, wherein the sensing amplifiers are connected to the storage cells via bit lines.

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