1266 results about "Hard mask" patented technology

The invention discloses a manufacturing method of a semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, forming a dummy gate on the substrate, and forming a hard mask layer on the dummy gate; forming side wall structures on two sides of the dummy gate; forming a contact hole etching stop layer on the substrate, the side wall structure and the pseudo gate, wherein the material of the contact hole etching stop layer is the same as that of the hard mask layer; forming an interlayer dielectric layer on the contact hole etching stop layer, and planarizing the interlayer dielectric layer to the residual preset thickness of the hard mask layer; oxidizing the hard mask layer, a part of the contact hole etching stop layer and a part of the side wall structure to form a surface oxide layer; synchronously removing the surface oxide layer and a part of the interlayer dielectric layer, wherein the surface of the dummy gate is flush with the surfaces of the interlayer dielectric layers on the two sides; and removing the dummy gate to form a metal gate. According to the manufacturing method of the semiconductor device provided by the invention, the height of the formed metal gate can be ensured, the manufacturing process is simple, and the controllability is high.

A method includes providing a first channel layer of a first transistor and a second channel layer of a second transistor over a substrate, forming a dipole layer over the first channel layer and the second channel layer, forming a patterned hard mask covering the second channel layer and exposing the first channel layer, removing the dipole layer from the first channel layer, removing the patterned hard mask, performing a thermal drive-in process, forming an interfacial dielectric layer on the first channel layer and the dipole layer, and forming a high-k dielectric layer on the interfacial dielectric layer. The dipole layer includes a p-dipole material.

The invention provides a semiconductor structure and a preparation method thereof, and the method comprises the steps: providing a semiconductor material layer which is used for forming at least two grooves; a first hard mask layer is formed on one side of the semiconductor material layer, the first hard mask layer is etched to form at least two openings, and the openings are used for defining the key size of the groove; forming an etching guide structure in the opening, wherein the upper surface of the etching guide structure is higher than the upper surface of the first hard mask layer; forming a dielectric layer covering the first hard mask layer and the etching guide structure, wherein the upper surface of the dielectric layer is flush with the upper surface of the etching guide structure; forming a photoresist layer on one side, deviating from the first hard mask layer, of the dielectric layer, and performing exposure of different depths on the photoresist layer at the corresponding position of the opening to form photoresist grooves of different depths; and performing one-time etching on the etching guide structure and the semiconductor material layer based on the photoresist grooves with different depths so as to form grooves with different depths in the semiconductor material layer.

A trench in a semiconductor substrate is lined with a first insulation layer. A hard mask layer deposited on the first insulation layer is used to control performance of an etch that selectively removes a first portion of the first insulating layer from an upper trench portion while leaving a second portion of first insulating layer in a lower trench portion. After removing the hard mask layer, an upper portion of the trench is lined with a second insulation layer. An opening in the trench that includes a lower open portion delimited by the second portion of first insulating layer in the lower trench portion and an upper open portion delimited by the second insulation layer at the upper trench portion, is then filled by a single deposition of polysilicon material forming a unitary gate / field plate conductor of a field effect rectifier diode.

A semiconductor device is provided. The semiconductor device includes a first region having a first gate structure disposed on a substrate and a second region having a second gate structure disposed on the substrate, a hard mask formed on the substrate, the first gate structure, and the second gate structure, a deep trench formed in the substrate between the first region and the second region, and formed to penetrate the hard mask to reach an inside of the substrate, and a planarized gap-fill insulating layer formed on the second gate structure and formed inside the deep trench. A topmost surface of the planarized gap-fill insulating layer and a topmost surface of the hard mask are coplanar.

Semiconductor structures and methods of forming the same are provided. An exemplary method incudes forming a first dielectric layer over a first conductive feature, forming a conductive via extending through the first dielectric layer and coupled to the first conductive feature, forming a hard mask layer over the conductive via, patterning the hard mask layer to form a first opening exposing the first dielectric layer; forming a sacrificial layer to partially fill the first opening, forming a porous dielectric layer on the sacrificial layer, after the forming of the porous dielectric layer, selectively removing the sacrificial layer to form an air gap, forming a second dielectric layer over the porous dielectric layer, and replacing a portion of the patterned hard mask layer disposed directly over the conductive via with a second conductive feature.

The invention provides a manufacturing method of a type-II superlattice medium-wave infrared focal plane array chip and an infrared detector, and belongs to the field of infrared focal plane array chips. The problem that in the prior art, the surface leakage current of an infrared focal plane array chip is large due to the fact that the mesa etching depth is large is solved. The method comprises the following steps: growing and cleaning an epitaxial material; hard mask deposition, mesa photoetching and etching: obtaining a required mesa pattern on the hard mask through a photoetching technology, then etching an epitaxial material, etching the epitaxial material to form the mesa pattern, the mesa pattern comprising an upper electrode region and a lower electrode region, etching the upper electrode region to the boundary of the barrier layer and the absorption region, and etching the lower electrode region to the boundary of the barrier layer and the absorption region; etching a lower electrode region to the lower ohmic contact layer; manufacturing a metal electrode; a connecting piece is manufactured on the metal electrode to be connected with a reading circuit, and manufacturing of the infrared focal plane array chip is completed; the invention is applied to the II-type superlattice medium-wave infrared detector.

The invention discloses a manufacturing method of a trench gate semiconductor power device. The manufacturing method comprises the following steps: forming a first hard mask layer on a first epitaxial layer; and performing graphical etching on the first hard mask layer to open the forming region of the gate trench. And etching the first epitaxial layer to form a gate trench. And after the first hard mask layer is removed, performing a first thermal oxidation process to form a first field oxide layer on the inner side surface of the gate trench and the outer surface of the gate trench. And performing a first CVD growth process to form a second field oxide layer, and overlapping the first field oxide layer and the second field oxide layer to form a third field oxide layer. And performing a first CMP process to remove the third field oxide layer outside the gate trench. And forming a first polycrystalline silicon layer to completely fill the gate trench and extend out of the gate trench. And performing a second CMP process to flatten the first polycrystalline silicon layer. The structure consistency of the gate trench region and the platform region can be improved at the same time, and the performance and the yield of the device can be comprehensively improved.

A method includes forming a fin protruding from a substrate, the fin including an epitaxial stack over a fin base and a hard mask layer over the epitaxial stack, the epitaxial stack including first and second semiconductor layers of different material compositions, performing a first etching process to etch the hard mask layer, the first etching process including applying a first combination of etchants, performing a second etching process to etch the epitaxial stack, the second etching process including applying a second combination of etchants, and performing a third etching process to etch the fin base, the third etching process including applying a third combination of etchants. The first, second, and third combinations of etchants are different from each other.

The invention relates to an epitaxial structure of a low-specific on-resistivity GaN HEMT and a preparation method thereof, and the preparation method comprises the steps: S1, sequentially growing an initial layer, a buffer layer, a channel layer, a first insertion layer, a first barrier layer, a second insertion layer and a second barrier layer on a substrate from bottom to top, and obtaining a thick barrier epitaxial wafer; s2, preparing a hard mask layer, patterning and etching the hard mask layer, then transferring the hard mask layer to the upper surface of the thick barrier epitaxial wafer, and etching the thick barrier epitaxial wafer to the upper surface of the second insertion layer; s3, secondarily growing a p-GaN layer on the upper surface of the second insertion layer in the gate region; and S4, removing the polycrystalline GaN in a non-gate region, depositing metal on the p-GaN layer to manufacture a gate, and depositing metal on two sides of the structure to manufacture a source and a drain respectively. By selectively growing the p-GaN layer in the grid region, two-dimensional electron gas in a channel is effectively exhausted, and the carrier concentration of the region below the grid is remarkably reduced.

A method of forming an electronic device includes forming a patterned stack including a first electrode layer deposited over a substrate, a ferroelectric material layer disposed over the first electrode layer, and a hard mask layer disposed over the ferroelectric material layer; forming a sidewall spacer along a sidewall of the patterned stack, the sidewall spacer including a metal oxide; etching the sidewall spacer selectively relative to the hard mask layer to expose a portion of a sidewall of the ferroelectric material layer; and depositing a second electrode layer over the ferroelectric material layer after removing the hard mask layer.

The invention provides a method for forming a semiconductor structure, which comprises the following steps of: providing a semiconductor substrate which comprises a first dielectric layer and a metal plug positioned in the first dielectric layer; sequentially forming a first isolation layer, a second dielectric layer, a second isolation layer and a hard mask layer on the top surface of the first dielectric layer; etching and removing the hard mask layer, the second isolation layer and a part of the second dielectric layer in a region corresponding to the metal plug to form an opening; the hard mask layer is removed; and etching is continued along the opening so as to expose the metal plug. The invention also provides a semiconductor structure. According to the semiconductor structure and the forming method provided by the invention, hole defects can be prevented from being formed in the metal layer when the opening is filled with the metal layer.

The invention provides a semiconductor device and a manufacturing method thereof, and the manufacturing method comprises the steps: providing a semiconductor structure which comprises a substrate with a PMOS region and an NMOS region, and the substrate is provided with a grid electrode and a side wall material layer which comprises a first material layer and a second material layer; forming a first mask layer covering the surface of the semiconductor structure; forming an anti-reflection layer, a second mask layer and an opening on the first mask layer, wherein the opening exposes a part of the first mask layer; removing the exposed first mask layer; removing the second mask layer and a part of the anti-reflection layer in the NMOS region; grooves are formed in the two sides of the grid electrode of the PMOS region, and the exposed part of the first mask layer and the exposed part of the second material layer located in the NMOS region are removed; forming a stress semiconductor layer in the groove to fill the groove; and etching to remove the remaining first mask layer and the side wall material layer on the top surface of the gate, and forming side wall layers on the two sides of the gate. According to the invention, the hard mask layer in the NMOS region does not need to be removed independently, and the production cost is saved.

A method of fabricating a variable resistance memory device includes preparing a substrate having a cell area and a peripheral area, forming magnetic tunnel junction structures in the cell area, forming an interlayer insulating layer covering the cell area and the peripheral area, forming a hard mask conformally covering the interlayer insulating layer, etching a portion of the hard mask to form first recesses in the cell area and a second recess in the peripheral area, forming a plurality of first openings in the interlayer insulating layer by using the first recesses of the hard mask in the cell area in a selective etch process and forming a second opening in the interlayer insulating layer by using the second recess of the hard mask in the peripheral area in the selective etch process, and completely removing the hard mask in the cell area and the peripheral area.

A method for forming a semiconductor device can include receiving a substrate having a metal mask layer thereon and a first mask layer over the metal mask layer, where the first mask layer is patterned having holes that open to the metal mask layer, and where the metal mask layer contains tungsten, silicon, and nitrogen, passivating a surface of the metal mask layer in the holes using a first chemistry to form a passivation layer on the surface of the metal mask layer, where the first chemistry contains sulfur and hydrogen, and performing an anisotropic etch with a second chemistry to remove first passivation portions of the passivation layer and first metal portions of the metal mask layer at bottoms of the holes to increase hole depths of the holes in the metal mask layer, and where the second chemistry contains boron and chlorine.

Provided is a mask blank.The mask blank has a structure where a thin film for pattern formation, a first hard mask film, and a second hard mask film are stacked in this order on a main surface of a substrate, the thin film for pattern formation contains a transition metal, the first hard mask film contains oxygen and one or more elements selected from silicon and tantalum, the second hard mask film contains a transition metal, a content of transition metal of the second hard mask film is less than the content of transition metal of the thin film for pattern formation, a region where the first hard mask film is formed on the main surface is smaller than a region where the thin film for pattern formation is formed, and the second hard mask film and the thin film for pattern formation are in contact with each other at least in part.

Methods of forming gate structures for stacked multi-gate devices are provided. A method according to the present disclosure includes forming a gate dielectric layer to wrap around a bottom channel member and a top channel member, depositing a dipole layer over the gate dielectric layer, forming a dummy layer such that the top channel member is disposed above the top surface of the dummy layer, removing the dipole layer around the top channel member, forming a self-assembled monolayer (SAM) on the top surface of the dummy layer, depositing a hard mask layer to wrap over the top channel member, removing the SAM and the dummy layer, performing a thermal drive-in process to drive a dipole dopant species from the dipole layer into the gate dielectric layer around the bottom channel member, removing the hard mask layer, and removing the dipole layer.

A method for forming a semiconductor device can include forming a metal mask layer on a substrate, where the metal mask layer contains tungsten, and forming a patterned mask directly on the metal mask layer, where the forming of the patterned mask includes forming a barrier layer directly on the metal mask layer, where the barrier layer contains nitrogen, forming a dielectric layer directly on the barrier layer, where the dielectric layer contains oxygen, and patterning and etching the dielectric layer and the barrier layer to form holes through the dielectric layer and the barrier layer, such that the holes open to the metal mask layer.

The invention provides an infrared detector deep mesa etching process based on three layers of masks and an infrared detector, and belongs to the field of infrared detector mesa etching. The process comprises the following steps: spin-coating a stress buffer layer on the surface of a superlattice epitaxial layer, and curing and forming; depositing a hard mask serving as an etching barrier layer; depositing an inorganic oxide; spin-coating photoresist to form a composite patterned top layer, and then forming a mesa pattern through a photoetching process; taking the mesa pattern as a mask, and transferring the mesa pattern to the hard mask through reactive ion etching; etching the stress buffer layer by adopting plasma until the surface of the superlattice epitaxial layer is exposed; the three layers of masks are used as blocking, deep etching is carried out through inductively coupled plasma, and the etching depth is 5.6-6 microns; a post-processing step; according to the process provided by the invention, high-quality and high-aspect-ratio mesa etching can be realized on the premise of not introducing extra pollution and remarkably increasing the cost, and the process is suitable for preparing a deep-mesa and high-aspect-ratio device.

The invention belongs to the technical field of semiconductors, and particularly relates to a method for improving the height difference of an NMOS (N-channel Metal Oxide Semiconductor) and a PMOS (P-channel Metal Oxide Semiconductor), a semiconductor structure and a device, which comprises the following steps of: providing an intermediate product which comprises a PMOS region and an NMOS region, and forming a polycrystalline silicon gate structure and a first oxide layer covering the polycrystalline silicon gate structure on each of the PMOS region and the NMOS region, the polycrystalline silicon gate structure comprises a gate polycrystalline silicon layer, a hard mask layer, a silicon oxide layer and a silicon nitride layer which are sequentially formed from inside to outside; grinding the first oxide layer to enable the surface of the first oxide layer to be flush; thinning the remaining first oxide layer to expose the top of the silicon nitride layer; etching to remove the top of the silicon nitride layer and a part of the side wall so as to expose the top of the silicon oxide layer; and thinning the remaining first oxide layer, and removing the silicon oxide layer and the top of the hard mask layer until the top surface of the gate polycrystalline silicon layer is reached. According to the invention, the height difference between the NMOS region and the PMOS region is effectively reduced.

A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a first spin orbit torque (SOT) layer on the MTJ, forming an inter-metal dielectric (IMD) layer around the first SOT layer, forming a second SOT layer on the IMD layer, forming a first hard mask on the second SOT layer, patterning the first hard mask along a first direction, and then patterning the first hard mask along a second direction.

A hole structure forming method comprises the following steps: providing a substrate, and sequentially forming a hard mask layer and a photoresist mask layer on the substrate; the method comprises the following steps of: etching a hard mask layer by using a photoresist mask layer to form a groove which at least penetrates through the hard mask layer, carrying out in-situ thermal chemical reaction treatment on the side wall of the groove so as to form a protective layer of which the compactness is higher than that of the hard mask layer on the side wall of the hard mask layer, and then taking the residual hard mask layer as a mask, and etching the substrate by adopting a dry etching process to form the deep hole. The protection layer is formed through in-situ thermal chemical reaction growth, and the structure of the protection layer is compact, so that in the process of performing dry etching on the substrate to form the deep hole, the protection layer can effectively resist the damage of etching plasma to the side wall of the hard mask layer in the dry etching process, the deep hole with better side wall morphology can be formed, and the service life of the deep hole is prolonged. The consistency of the width sizes of the top and the bottom of the deep hole is improved, and the electrical performance and the reliability of the finally formed semiconductor structure are improved.

The invention provides a composition, application thereof and a preparation method of a semiconductor device. The composition comprises the following components in percentage by mass: 5-50% of a first aprotic organic solvent; 5%-30% of a second aprotic organic solvent; 0.01%-5% of an acid; 0.15%-5% of a corrosion inhibitor; 10%-85% of water; the corrosion inhibitor comprises amino acid with the molecular weight larger than or equal to 100. The composition provided by the invention can be mixed with an oxidizing agent for use, etching residues on the surface of a patterned substrate can be effectively cleaned after mixing, a part of a hard mask on the patterned substrate can be selectively removed while a metal material in the patterned substrate is effectively protected, and the etching selection ratio of the hard mask to the metal material is improved.

The invention discloses a manufacturing method of a shallow trench isolation structure and the shallow trench isolation structure. The manufacturing method of the shallow trench isolation structure comprises the following steps: forming a hard mask layer with a protection structure on a semiconductor layer; forming a groove which penetrates through the hard mask layer and extends into the semiconductor layer; forming an isolation medium in the groove, wherein the protection structure is adjacent to the isolation medium in the groove; and removing the hard mask layer to form a shallow trench isolation structure, wherein in the process of removing the hard mask layer, the side wall of the isolation medium in the groove is protected by the protection structure, so that a gap is prevented from being formed between the semiconductor layer and the side wall of the isolation medium.

A semiconductor device is provided. The semiconductor device includes a heater formed on a substrate; a hardmask formed on the heater; a phase change material layer formed on a first side of the heater and the hardmask; a first electrode formed on the phase change material layer on the first side; and a second electrode formed on the substrate on a second side of the heater and the hardmask.

The invention provides a semiconductor structure and a forming method thereof, the semiconductor structure comprises an SO I substrate, the SO I substrate comprises a bottom silicon layer, an insulating layer and a top silicon layer, the SO I substrate comprises a strip-shaped waveguide area and a ridge-shaped waveguide area, and a hard mask layer is formed on the surface of the SO I substrate; a strip-shaped waveguide is formed in the top silicon layer of the strip-shaped waveguide area, and a ridge-shaped waveguide is formed in the top silicon layer of the ridge-shaped waveguide area. According to the semiconductor structure and the forming method thereof, the influence of the etching load effect can be optimized, the etching depth accuracy of the ridge waveguide region and the grating region is improved, and the device performance is improved.

An optical filter for an optical sensor and a method of forming the same are disclosed, on one hand, by sequentially forming a plurality of filters on a substrate having an optoelectronic element, forming a hard mask on the plurality of filters that is patterned according to element configuration and filter adjoining unstable regions, etching back separation, and forming a plurality of optical filters on the substrate by etching back separation. A critical portion of an adjacent filter is removed to achieve high-precision and ideal reconfiguration of a pattern. The present invention has the advantage of being able to improve optical performance by filling the reconfigured gap with an optical member capable of imparting anti-crosstalk and light-focusing effects, etc. On the other hand, after the low-refractive-index grid structure is formed, an upper cover layer is more easily formed on the surface of the flat substrate, invasion of impurities brought by the next process can be prevented, and meanwhile the upper cover layer can serve as a barrier layer of a subsequent micro-lens array so as to improve the forming quality of micro-lenses.

The invention discloses a manufacturing method of a semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, and forming a dummy gate and a hard mask layer on the substrate; forming side wall structures on two sides of the dummy gate; forming a contact hole etching stop layer, wherein the material of the contact hole etching stop layer is the same as that of the hard mask layer; forming an interlayer dielectric layer on the contact hole etching stop layer, and planarizing the interlayer dielectric layer to the residual preset thickness of the hard mask layer by adopting a first planarization process; performing first plasma modification treatment, and at least forming a first modified layer on the surface of the interlayer dielectric layer; second plasma modification processing is carried out, and at least the hard mask layer and a part of the contact hole etching stop layer are modified into a second modified layer; synchronously removing the first modified layer and the second modified layer, and exposing the dummy gate; and removing the dummy gate to form a metal gate. According to the invention, residual metal in the interlayer dielectric layer is avoided, the height consistency of the metal gate is improved, and the reliability of the semiconductor device is improved.

A polishing composition, includes an abrasive; a pH adjuster; a barrier film removal rate enhancer; a low-k removal rate inhibitor; an azole-containing corrosion inhibitor; and a ruthenium removal rate enhancer. A method of polishing a substrate includes the steps of: applying the polishing composition described herein to a surface of a substrate, wherein the surface comprises ruthenium or a hard mask material; and bringing a pad into contact with the surface of the substrate and moving the pad in relation to the substrate.

Semiconductor devices and methods are provided. In an embodiment, a method includes providing a workpiece including a first hard mask layer on a top surface of a substrate, performing an ion implantation process to form a doped region in the substrate, after the performing of the ion implantation process, annealing the workpiece at temperature T1. The method also includes selectively removing the first hard mask layer, after the selectively removing of the first hard mask layer, performing a pre-bake process at temperature T2, and, after the performing of the pre-bake process, epitaxially growing a vertical stack of alternating channel layers and sacrificial layers on the substrate, where the temperature T2 is lower than the temperature T1.