741 results about "Hard mask" patented technology

The invention discloses a manufacturing method of a trench gate semiconductor power device. The manufacturing method comprises the following steps: forming a first hard mask layer on a first epitaxial layer; and performing graphical etching on the first hard mask layer to open the forming region of the gate trench. And etching the first epitaxial layer to form a gate trench. And after the first hard mask layer is removed, performing a first thermal oxidation process to form a first field oxide layer on the inner side surface of the gate trench and the outer surface of the gate trench. And performing a first CVD growth process to form a second field oxide layer, and overlapping the first field oxide layer and the second field oxide layer to form a third field oxide layer. And performing a first CMP process to remove the third field oxide layer outside the gate trench. And forming a first polycrystalline silicon layer to completely fill the gate trench and extend out of the gate trench. And performing a second CMP process to flatten the first polycrystalline silicon layer. The structure consistency of the gate trench region and the platform region can be improved at the same time, and the performance and the yield of the device can be comprehensively improved.

The invention relates to an epitaxial structure of a low-specific on-resistivity GaN HEMT and a preparation method thereof, and the preparation method comprises the steps: S1, sequentially growing an initial layer, a buffer layer, a channel layer, a first insertion layer, a first barrier layer, a second insertion layer and a second barrier layer on a substrate from bottom to top, and obtaining a thick barrier epitaxial wafer; s2, preparing a hard mask layer, patterning and etching the hard mask layer, then transferring the hard mask layer to the upper surface of the thick barrier epitaxial wafer, and etching the thick barrier epitaxial wafer to the upper surface of the second insertion layer; s3, secondarily growing a p-GaN layer on the upper surface of the second insertion layer in the gate region; and S4, removing the polycrystalline GaN in a non-gate region, depositing metal on the p-GaN layer to manufacture a gate, and depositing metal on two sides of the structure to manufacture a source and a drain respectively. By selectively growing the p-GaN layer in the grid region, two-dimensional electron gas in a channel is effectively exhausted, and the carrier concentration of the region below the grid is remarkably reduced.

A method of forming an electronic device includes forming a patterned stack including a first electrode layer deposited over a substrate, a ferroelectric material layer disposed over the first electrode layer, and a hard mask layer disposed over the ferroelectric material layer; forming a sidewall spacer along a sidewall of the patterned stack, the sidewall spacer including a metal oxide; etching the sidewall spacer selectively relative to the hard mask layer to expose a portion of a sidewall of the ferroelectric material layer; and depositing a second electrode layer over the ferroelectric material layer after removing the hard mask layer.

The invention provides a semiconductor device and a manufacturing method thereof, and the manufacturing method comprises the steps: providing a semiconductor structure which comprises a substrate with a PMOS region and an NMOS region, and the substrate is provided with a grid electrode and a side wall material layer which comprises a first material layer and a second material layer; forming a first mask layer covering the surface of the semiconductor structure; forming an anti-reflection layer, a second mask layer and an opening on the first mask layer, wherein the opening exposes a part of the first mask layer; removing the exposed first mask layer; removing the second mask layer and a part of the anti-reflection layer in the NMOS region; grooves are formed in the two sides of the grid electrode of the PMOS region, and the exposed part of the first mask layer and the exposed part of the second material layer located in the NMOS region are removed; forming a stress semiconductor layer in the groove to fill the groove; and etching to remove the remaining first mask layer and the side wall material layer on the top surface of the gate, and forming side wall layers on the two sides of the gate. According to the invention, the hard mask layer in the NMOS region does not need to be removed independently, and the production cost is saved.

The invention provides an infrared detector deep mesa etching process based on three layers of masks and an infrared detector, and belongs to the field of infrared detector mesa etching. The process comprises the following steps: spin-coating a stress buffer layer on the surface of a superlattice epitaxial layer, and curing and forming; depositing a hard mask serving as an etching barrier layer; depositing an inorganic oxide; spin-coating photoresist to form a composite patterned top layer, and then forming a mesa pattern through a photoetching process; taking the mesa pattern as a mask, and transferring the mesa pattern to the hard mask through reactive ion etching; etching the stress buffer layer by adopting plasma until the surface of the superlattice epitaxial layer is exposed; the three layers of masks are used as blocking, deep etching is carried out through inductively coupled plasma, and the etching depth is 5.6-6 microns; a post-processing step; according to the process provided by the invention, high-quality and high-aspect-ratio mesa etching can be realized on the premise of not introducing extra pollution and remarkably increasing the cost, and the process is suitable for preparing a deep-mesa and high-aspect-ratio device.

A semiconductor device is provided. The semiconductor device includes a heater formed on a substrate; a hardmask formed on the heater; a phase change material layer formed on a first side of the heater and the hardmask; a first electrode formed on the phase change material layer on the first side; and a second electrode formed on the substrate on a second side of the heater and the hardmask.

The invention provides a semiconductor structure and a forming method thereof, the semiconductor structure comprises an SO I substrate, the SO I substrate comprises a bottom silicon layer, an insulating layer and a top silicon layer, the SO I substrate comprises a strip-shaped waveguide area and a ridge-shaped waveguide area, and a hard mask layer is formed on the surface of the SO I substrate; a strip-shaped waveguide is formed in the top silicon layer of the strip-shaped waveguide area, and a ridge-shaped waveguide is formed in the top silicon layer of the ridge-shaped waveguide area. According to the semiconductor structure and the forming method thereof, the influence of the etching load effect can be optimized, the etching depth accuracy of the ridge waveguide region and the grating region is improved, and the device performance is improved.

The invention discloses a manufacturing method of a semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, and forming a dummy gate and a hard mask layer on the substrate; forming side wall structures on two sides of the dummy gate; forming a contact hole etching stop layer, wherein the material of the contact hole etching stop layer is the same as that of the hard mask layer; forming an interlayer dielectric layer on the contact hole etching stop layer, and planarizing the interlayer dielectric layer to the residual preset thickness of the hard mask layer by adopting a first planarization process; performing first plasma modification treatment, and at least forming a first modified layer on the surface of the interlayer dielectric layer; second plasma modification processing is carried out, and at least the hard mask layer and a part of the contact hole etching stop layer are modified into a second modified layer; synchronously removing the first modified layer and the second modified layer, and exposing the dummy gate; and removing the dummy gate to form a metal gate. According to the invention, residual metal in the interlayer dielectric layer is avoided, the height consistency of the metal gate is improved, and the reliability of the semiconductor device is improved.

Exemplary semiconductor processing methods may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include forming a plasma of the oxygen-containing precursor to produce oxygen-containing plasma effluents. The methods may include contacting a substrate housed in the processing region with the oxygen-containing plasma effluents. The substrate may include a boron-and-nitrogen-containing material overlying a carbon-containing material. The boron-and-nitrogen-containing material comprises a plurality of openings. The methods may include etching the carbon-containing material.

The present application relates to the technical field of microelectrode preparation, and particularly relates to a transparent microelectrode array chip preparation method, comprising the following steps: S1. pretreating a glass substrate to improve the substrate surface cleanliness and adsorbability of the electrode film; S2. evaporating an ITO film on the surface of the pretreated glass substrate by using a magnetron sputtering process, as a transparent electrode; S3. spin-coating a photoresist on the surface of the ITO film and performing a patterning treatment, and then etching the ITO film to form a preset electrode structure by using a dry etching process, and then removing the photoresist and cleaning and drying; S4. coating an insulating layer on the surface of the substrate by using a PECVD process, patterning the insulating layer and etching by using a dry etching process to realize windowing, and then removing the photoresist and cleaning and drying; and realizing photoelectric synchronous detection. Avoiding metal residue interference: photoresist masks are used throughout the etching process to replace traditional metal hard masks.

The present application provides a mask manufacturing method, a mask manufactured thereby, and a display device manufacturing method. The mask manufacturing method includes the steps of forming an organic substance layer on a mask substrate, patterning a hard mask on the organic substance layer, etching the organic substance layer to form a mask piece including a through hole, removing the hard mask disposed on the mask piece, forming a conductive substance layer on the mask piece, and etching the conductive substance layer to form a conductive layer.

Disclosed are a semiconductor device and a method for manufacturing thereof. The semiconductor device includes: a substrate, including a plurality of bit lines and gate structures; a first dielectric layer, located between adjacent gate structures; a plurality of connectors, located in the first dielectric layer and connected to the substrate; a plurality of contact structures, located between adjacent bit lines; a plurality of capacitor structures, located on the contact structures; a hard mask layer, covering the top surfaces of the connectors; and a second dielectric layer, including a first portion located above the hard mask layer and a second portion located above the contact structures, the vertexes of the first portion and the second portion of the second dielectric layer being at different horizontal heights.

The application relates to a semiconductor structure preparation method and a semiconductor structure. The semiconductor structure preparation method forms a first anti-reflection layer to protect a first gate structure in a first area. After etching a second area to form grooves on both sides of a second gate structure, all the first anti-reflection layer is removed, first etching is performed to remove part of a hard mask layer on the top of the first gate structure, second etching is performed to remove a first insulating layer on a substrate of the first area, and part of the hard mask layer of the first gate structure is removed. The hard mask layer of the first gate structure is etched twice, so that the thickness of the hard mask layer of the first gate structure removed is close to the thickness of the hard mask layer of the second gate structure removed in the process of etching the second area to form the grooves, thereby reducing the height difference between the first gate structure and the second gate structure, and improving the gate height load effect caused by the process asymmetry of the second area etching to form the grooves.

This application relates to a semiconductor structure and a method for manufacturing the same. The manufacturing method includes: providing a substrate, including a first region and a second region; forming at least two first gate structures in the first region and a second gate structure in the second region; simultaneously forming first sidewalls on the sidewalls of the first gate structures and second sidewalls on the sidewalls of the second gate structures; forming a hard mask layer; the hard mask layer covers the second sidewalls, the second gate structures, and the substrate of the second region, and at least exposes the substrate between adjacent first sidewalls; etching the substrate between adjacent first gate structures in the first region based on the hard mask layer to form sigma trenches between adjacent first gate structures; forming a silicon-germanium layer within the sigma trenches; and chemically etching to remove the hard mask layer. This application is advantageous in improving the consistency of sidewall thickness between different device regions and effectively avoiding hard mask material residue problems, thereby effectively improving device yield.

This invention relates to organometallic compounds, compositions comprising the organometallic compound, lithography methods using the organometallic compound, an optical element, optically active device or optical or semiconductor device obtainable by the lithography methods, hard masks obtainable by the lithography method, uses of the compounds or compositions, a method for the preparation of the compound.

The invention discloses a preparation method of a three-dimensional titanium dioxide micro-nano structure, which belongs to the technical field of micro-nano structure preparation, and comprises the following steps: evaporating a titanium dioxide film on a clean glass substrate; spin-coating positive photoresist on the titanium dioxide thin film; carrying out electron beam exposure on the photoresist, customizing a pattern, and carrying out developing and fixing treatment on the photoresist; evaporating a chromium (Cr) film on the developed and fixed sample; stripping the residual photoresist, and obtaining a patterned chromium hard mask on the titanium dioxide thin film; performing reactive ion beam etching on the titanium dioxide film; and removing the chromium hard mask from the etched sample to obtain the three-dimensional titanium dioxide nano-column array micro-nano structure. The titanium dioxide micro-nano structure prepared by the method has high degree of freedom, and regular regulation and control of nano structure unit parameters can be realized by changing reactive ion beam etching process parameters.

In an embodiment a method for processing an optoelectronic device includes providing a functional semiconductor layer stack on a growth substrate having an active layer for emitting light arranged between a first doped layer and a second doped layer, the second doped layer having a thickness, depositing a hard mask on the second doped layer, structuring the hard mask as to expose surface areas of the second doped layer, wherein the exposed surface areas are recessed with regard to a surface of the second doped layer beneath remaining portions of the hard mask and a remaining thickness of a material of the second doped layer at the exposed surface areas is less than 600 nm, diffusing a dopant into the material of the second doped layer at the exposed surface areas as to perform a quantum well intermixing within regions of the active layer beneath the exposed surface areas and applying a first contact material at least on unexposed areas of the doped second layer.

A method of processing a substrate that includes: forming a conformal etch stop layer (ESL) over a staircase pattern of the substrate, the staircase pattern including staircases, each of the staircases including a conductive surface; forming a dielectric layer over the ESL; planarizing a top surface of the dielectric layer; forming a patterned hardmask over the dielectric layer; and etching the dielectric layer selectively to the ESL using the patterned hardmask as an etch mask to form a plurality of recesses, each of the plurality of recesses landing on each of the staircases, the ESL protecting the conductive surface from the etching, the etching including exposing the substrate to a plasma generated from a process gas including a fluorocarbon, O2, and WF6, a flow rate of WF6 being between 0.01% and 1% of a total gas flow rate of the process gas.

A method for fabricating an MRAM device is disclosed. The method includes: depositing a first dielectric layer and a second dielectric layer over a semiconductor substrate; depositing a bottom electrode layer over the second dielectric layer, and forming an MTJ stack and a hard mask layer over the bottom electrode layer; patterning the hard mask layer and forming at least one MTJ pillar by etching the MTJ stack with the patterned hard mask layer serving as a mask; depositing a first ILD layer over a top surface of the hard mask layer and on sidewalls of the hard mask layer and MTJ pillar; performing a first etch-back process on the first ILD layer, such that a surface of the first ILD layer on each side of the hard mask layer and the MTJ pillar forms a slope of 40°-70° with respect to a surface of the semiconductor substrate.

This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself, relating to the field of semiconductor technology. The method includes: providing a wafer, the wafer including a substrate, and a base layer disposed on the substrate; forming a hard mask layer on the base layer, the hard mask layer comprising, from bottom to top, a first silicon oxide layer, a polysilicon layer, a second silicon oxide layer, and a carbon layer; forming an anti-reflection layer and a photoresist layer with a preset pattern on the hard mask layer; etching the anti-reflection layer and the hard mask layer using the photoresist layer as a mask to transfer the preset pattern to the hard mask layer; and etching the base layer using the hard mask layer as a mask to form a target structure with the preset pattern in the base layer. This disclosure improves upon the problems of hard mask layer deformation and pattern failure in high aspect ratio etching processes, ensuring accurate transfer of the pattern to the base layer to fabricate a high-quality target structure and improve product performance.

The invention provides a photomask manufacturing method based on guided self-assembly. Advanced node high-end photomasks with high graphic quality can be prepared with high production flux. Comprising the following steps of: preparing a guide template, namely sequentially laminating and spin-coating a carbon film and an antireflection layer on a photomask substrate, forming a specified pattern in the antireflection layer, and preparing the guide template by coating a neutral layer or a molecular brush and annealing; a block copolymer guiding self-assembly step: coating a neutral layer or a molecular brush on the guiding template, annealing, coating a block copolymer, annealing, guiding the block copolymer to carry out self-assembly, forming a first block pattern and a second block pattern, and selectively removing the first block pattern; and a pattern transfer step: transferring the second block pattern to the spin-coated carbon film, and further transferring the pattern transferred to the spin-coated carbon film to the photomask substrate by taking the pattern of the spin-coated carbon film as a hard mask layer, thereby forming a specified pattern in the photomask substrate.

This disclosure provides a semiconductor structure and a method for fabricating the same. The method includes providing a substrate including an insulating region, an active region, and a first upper surface, the active region being adjacent to the insulating region, wherein the insulating region has an insulating trench filled with a dielectric material, and the active region has a gate trench filled with a gate electrode material; forming a hard mask on the substrate; and performing an etching process to partially remove portions of the dielectric material and the gate electrode material exposed by the hard mask, thereby forming a second upper surface of the dielectric material and a third upper surface of the gate electrode material, wherein the second upper surface and the third upper surface are substantially on the same plane and substantially lower than the first upper surface.

A method for forming a semiconductor device structure includes forming fin base structures over a first region and a second region of a substrate and channel layers over the fin base structures. The distances between the fin structures in the first region and the second region are different. The method also includes filling an isolation material between the fin base structures and recessing the isolation material to form a first isolation structure in the first region and a second isolation structure in the second region. The method also includes depositing a hard mask layer over the first isolation structure and the second isolation structure. The thicknesses of the hard mask layer in the first region and the second region are different, and the top surfaces of the hard mask layer in the first region and the second region are substantially at the same level.

The application provides an infrared detector deep mesa etching process based on a three-layer mask and an infrared detector, and belongs to the field of infrared detector mesa etching. The process comprises the following steps: spin-coating a stress buffer layer on the surface of a superlattice epitaxial layer and curing the stress buffer layer; depositing a hard mask as an etching barrier layer; depositing an inorganic oxide; spin-coating a photoresist to form a composite patterned top layer, and then forming a mesa pattern through a photolithography process; taking the mesa pattern as a mask, transferring the mesa pattern to the hard mask through reactive ion etching; etching the stress buffer layer by using plasma until the surface of the superlattice epitaxial layer is exposed; taking the three-layer mask as a barrier, performing deep etching by using inductively coupled plasma, and the etching depth is 5.6-6 microns; and performing a post-processing step. The process of the application can realize high-quality and high-aspect-ratio mesa etching without introducing additional pollution and significant cost increase, and is suitable for the preparation of deep mesa and high-aspect-ratio devices.

The invention relates to the technical field of semiconductor processing, in particular to a self-alignment double patterning method and a semiconductor device. The self-alignment double patterning method comprises the steps that a substrate is provided, a hard mask layer and an initial side wall layer are formed on the substrate, the initial side wall layer comprises an asymmetric part, and the asymmetric part comprises a first side face and a second side face which are arranged oppositely and have asymmetry; forming a dielectric layer, wherein the dielectric layer covers the hard mask layer and the initial side wall layer; etching a part of the dielectric layer to expose an asymmetric part; the asymmetric part is removed, so that the top surface of the initial side wall layer is flush with the top surface of the dielectric layer; the remaining dielectric layer is etched to form a side wall layer, and the side wall layer comprises a first side face and a second side face which are arranged oppositely and have symmetry; and sequentially etching the hard mask layer and the substrate to form a required pattern in the substrate. According to the invention, the problem of asymmetry of the left and right shapes of the side wall in the current self-alignment double patterning method can be relieved.

Embodiments of the present disclosure generally relate to non-plasma methods of processing a substrate. More specifically, the methods disclosed herein incorporate microwave oxidation that is used to selectively etch materials during semiconductor device manufacturing. The method for etching a semiconductor device structure is disclosed includes performing a microwave oxidation etch process on the semiconductor device structure, wherein a hard mask is disposed over at least a portion of the semiconductor device structure. The microwave oxidation etch process includes flowing a first process gas over the semiconductor device structure and delivering a microwave energy to the first process gas without generating a plasma. The method further includes performing a preclean process on the semiconductor device structure. The preclean process includes flowing a second process gas over the semiconductor device structure.

Described herein are a cleaning composition, a wet-etch composition including the cleaning composition and one or more oxidants, and a method of using the wet-etch composition. Also described herein are a process for the manufacture of a semiconductor device from a semiconductor substrate and a kit including the cleaning composition and one or more oxidants.

This disclosure relates to methods and structures for adjusting gate dielectrics. One method includes forming a plurality of semiconductor nanostructures and forming a hard mask including a top portion over the plurality of semiconductor nanostructures; an inner portion between the plurality of semiconductor nanostructures; and sidewall portions on the sidewalls of the plurality of semiconductor nanostructures. The method further includes etching the sidewall portions of the hard mask, wherein at least the top portion of the hard mask is retained; performing a first oxidation process to oxidize the sidewall portions of the semiconductor nanostructures to form a first oxide layer; removing the top and inner portions of the hard mask; and performing a second oxidation process to oxidize the top and bottom portions of the semiconductor nanostructures to form a second oxide layer. The second oxide layer includes the first oxide layer. The second oxide layer surrounds the remainder of the plurality of semiconductor nanostructures.

A method includes forming a first multilayer stack in a first device region, forming a first gate stack over the first multilayer stack, forming a second multilayer stack in a second device region, forming a second gate stack over the second multilayer stack, etching the first multilayer stack to form a first source / drain recess, and etching the second multilayer stack to form a second source / drain recess. The method further includes forming a hard mask in the second source / drain recess, and forming a lower source / drain region in the first source / drain recess. After the lower source / drain region is formed, the hard mask is removed from the second source / drain recess. A first upper source / drain region and a second upper source / drain region are formed in the first source / drain recess and the second source / drain recess, respectively.

Embodiments of the present disclosure generally relate to methods for etching a carbon hard mask to have improved etching selectivity and profile control. In some embodiments, a method is provided for processing a carbon hard mask layer, which includes positioning a workpiece within a process area of ​​a processing chamber, wherein the workpiece has a carbon hard mask layer positioned on or throughout the underlying layer, and processing the carbon hard mask layer by exposing the workpiece to a sequential penetration synthesis (SIS) process to produce an alumina-carbon hybrid hard mask denser than the carbon hard mask layer. The SIS process includes exposing the carbon hard mask layer to an aluminum precursor to penetrate the carbon hard mask layer with the aluminum precursor, purging and removing gaseous residues, exposing the carbon hard mask layer to an oxidizing agent to penetrate the carbon hard mask layer with the oxidizing agent to produce an alumina coating positioned on the inner surface of the carbon hard mask layer, and purging the process area to remove gaseous residues.