2149 results about "Hard mask" patented technology

The invention provides a forming method of a double-shallow-trench isolation structure with different depths and a semiconductor device, and the method comprises the steps: S1, providing a substrate which comprises a first region and a second region; s2, sequentially forming a first dielectric layer, a first hard mask layer and a second hard mask layer on the substrate, wherein the first hard mask layer and the second hard mask layer are made of different materials; s3, forming a first initial opening in the second hard mask layer of the first region, performing etching by taking the second hard mask layer as a mask, and stopping forming a first opening on the surface of the first dielectric layer; s4, forming a second initial opening in the second hard mask layer of the second region, etching by taking the second hard mask layer as a mask, and stopping on the surface of the substrate to form a second opening; s5, removing the second hard mask layer; and S6, etching the first opening and the second opening at the same time by taking the first hard mask layer as a mask, forming a first shallow trench below the first opening, and forming a second shallow trench below the second opening. The depth difference between the first shallow trench and the second shallow trench is determined by the thickness of the first dielectric layer.

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, forming a gate structure and a side wall on the substrate, and enabling the gate structure to comprise a gate dielectric layer, a dummy gate, a first hard mask layer, a second hard mask layer and an amorphous carbon layer; forming a first patterned photoresist layer covering the NMOS region; forming grooves in the substrate at two sides of the gate structure in the PMOS region, and reserving an amorphous carbon layer with a partial thickness on the second hard mask layer; the first patterned photoresist layer is removed; and removing the amorphous carbon layer by adopting an ashing process. In the process of forming the groove in the PMOS region, the amorphous carbon layer protects the second hard mask layer below the amorphous carbon layer from being thinned, and after the amorphous carbon layer is removed, the thickness of the second hard mask layer in the two regions can be ensured to be consistent, so that the height of the dummy gate is ensured to be consistent, and the electrical performance of the device is improved.

The invention provides a method for adjusting the height of a grid electrode and a semiconductor structure, and belongs to the field of semiconductors. The method of adjusting gate height includes providing a semiconductor substrate. And etching back the hard mask layer in the NMOS region to reduce the thickness of the hard mask layer in the NMOS region. And after back etching, gate structures are respectively formed in the PMOS region and the NMOS region. And filling a dielectric layer, wherein the dielectric layer covers the gate structure of the NMOS region. And patterning a groove, etching the groove in the PMOS region, and when the groove is etched in the PMOS region, the thickness lost by the hard mask layer in the PMOS region is basically equal to the thickness lost by etching the hard mask layer in the NMOS region. By depositing the hard mask layer and etching the hard mask layer, the thickness of the hard mask layer in the PMOS region is basically equal to that of the hard mask layer in the NMOS region, so that the height of the formed grid electrode in the PMOS region is basically equal to that of the grid electrode in the NMOS region, and the performance of the device can be improved.

The invention provides a germanium-silicon groove preparation method, which comprises the following steps of: forming a PMOS (P-channel Metal Oxide Semiconductor) gate structure and an NMOS (N-channel Metal Oxide Semiconductor) gate structure on a semiconductor substrate, arranging a first silicon nitride layer, a silicon oxide layer and a second silicon nitride layer in hard mask layers of the PMOS gate structure and the NMOS gate structure, exposing the second silicon nitride layer through a gate side wall, and covering a germanium-silicon mask layer, a patterned photoresist protection NMOS gate structure is formed, the germanium-silicon mask layer exposed in the PMOS region is etched, a groove is formed, and at least part of the second silicon nitride layer is reserved at the top of the PMOS gate to protect the silicon oxide layer; according to the method, the first silicon nitride layer and the germanium-silicon mask layer are etched, germanium-silicon deposition is carried out, and the residual second silicon nitride layer and the germanium-silicon mask layer are removed together through wet etching, so that the height difference of the hard mask layer caused by the conventional process of the PMOS gate and the NMOS gate is eliminated, the process load is avoided, the process steps are simplified, and the process cost is reduced.

The invention provides a superlattice infrared detector chip manufacturing method, and belongs to the technical field of infrared detector manufacturing. The problem that the product performance or the product yield is low due to the fact that the precision fluctuation of the photoetching technology when the hard mask is removed is not considered in the current hard mask removing scheme is solved; comprising the following steps: forming a hard mask: growing the hard mask with a certain thickness on the surface of a wafer made of a superlattice material; photoetching an upper electrode table top; etching a hard mask: taking the photoresist as a mask, and etching the hard mask by adopting an ICP (Inductively Coupled Plasma) technology to obtain an upper electrode mesa mask pattern; degumming and cleaning an upper electrode table board; photoetching a lower electrode table board: adopting photoresist as a mask of a lower electrode table board area, and manufacturing the lower electrode table board area through a photoetching technology; carrying out ICP etching on the table board; performing wet etching on the table board; degumming and cleaning a lower electrode table board; forming a passivation layer film; opening holes in the passivation layer; manufacturing a gold electrode; the method is applied to preparation of the superlattice infrared detector chip.

The invention provides a preparation method of a shallow trench isolation structure and a semiconductor structure, and particularly relates to the technical field of semiconductors. The preparation method of the shallow trench isolation structure comprises the steps that a substrate is provided, the substrate comprises a substrate body and trench oxide formed in the substrate body, and the portion, protruding out of the substrate body, of the trench oxide is provided with a recess; forming a patterned hard mask layer on the substrate, wherein the patterned hard mask layer is provided with an opening in a region corresponding to the trench oxide; forming an oxide layer on the patterned hard mask layer, wherein the oxide layer covers the trench oxide and fills the recess; planarizing the oxide layer by taking the patterned hard mask layer as a stop layer; and removing the patterned hard mask layer. The method can effectively improve the sinking problem in the shallow trench isolation structure and improve the reliability of the device.

A semiconductor structure is provided. The semiconductor structure includes a substrate, a target layer on the substrate, and a hard mask layer doped with a group IV-A element on the target layer. The number of sp3 orbital bonds in the hard mask layer is greater than the number of sp2 orbital bonds.

The invention discloses a manufacturing method of a semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, forming a dummy gate on the substrate, and forming a hard mask layer on the dummy gate; forming side wall structures on two sides of the dummy gate; forming a contact hole etching stop layer on the substrate, the side wall structure and the pseudo gate, wherein the material of the contact hole etching stop layer is the same as that of the hard mask layer; forming an interlayer dielectric layer on the contact hole etching stop layer, and planarizing the interlayer dielectric layer to the residual preset thickness of the hard mask layer; oxidizing the hard mask layer, a part of the contact hole etching stop layer and a part of the side wall structure to form a surface oxide layer; synchronously removing the surface oxide layer and a part of the interlayer dielectric layer, wherein the surface of the dummy gate is flush with the surfaces of the interlayer dielectric layers on the two sides; and removing the dummy gate to form a metal gate. According to the manufacturing method of the semiconductor device provided by the invention, the height of the formed metal gate can be ensured, the manufacturing process is simple, and the controllability is high.

Various embodiments of improved process flows and methods are provided herein for etching high aspect ratio (HAR) features in carbon-containing hard mask layers. In the disclosed embodiments, the improved process flows and methods combine sidewall passivation and mask de-clogging steps in a single plasma process step to improve throughput when etching HAR features (such as vias, contact holes, trenches, etc.) within a carbon-containing hard mask layer. In doing so, the improved process flows and methods disclosed herein protect the sidewall surfaces of the carbon-containing hard mask layer and prevent bowing during the HAR etch process, while also reducing processing time and improving throughput.

The invention provides a semiconductor device and a preparation method thereof. According to the preparation method of the semiconductor device, after a silicon germanium groove structure is formed, a sacrificial layer is adopted as a sacrificial medium, and a hard mask layer is formed on the surface of each exposed gate structure so as to fill the height difference of the surfaces of the gate structures. And carrying out planarization treatment on the hard mask layer by adopting a chemical mechanical polishing process, so that the heights of the gate structures are recovered to the same horizontal plane. Based on this, the gate structures with the same height not only are beneficial to carrying out chemical mechanical grinding of a larger window by adopting the same load parameter in the subsequent preparation process, but also are beneficial to etching and cleaning the pseudo gate and fully filling the polycrystalline silicon in the subsequent technological process of removing the pseudo gate and filling the polycrystalline silicon; and a better process effect is ensured, so that ideal key parameters can be obtained, and the device yield is improved.

The invention provides a method for forming a strained silicon layer and a semiconductor structure, which comprises the steps of covering a semiconductor layer and a gate stack structure to form an etching stop layer, and the semiconductor layer comprises a first device region and a second device region which are separated from each other; forming an auxiliary side wall surrounding the side wall of the gate stack structure on the etching stop layer; forming a patterned hard mask layer; taking the patterned hard mask layer as an etching mask, and performing selective etching on the second device region through a wet etching process to form a sigma trench; and growing a strained silicon layer in the sigma groove. According to the invention, on the premise of not sacrificing the consistency of the critical dimensions of the sigma trench, the etching load effect caused by dry etching in the forming process of the sigma trench is avoided.

Methods for making thin-films on semiconductor substrates, which may be patterned using EUV, include: mixing a vapor stream of an organometallic precursor with a vapor stream of a counter-reactant so as to form a polymerized organometallic material; and depositing the organometallic polymer-like material onto the surface of the semiconductor substrate. The mixing and depositing operations may be performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD component, such as a discontinuous, ALD-like process in which metal precursors and counter-reactants are separated in either time or space.

A method for forming a semiconductor structure is provided. The method includes providing a semiconductor substrate with a tunnel dielectric layer, a conductive layer and a hard mask layer; etching the semiconductor layer, the tunnel dielectric layer, the conductive layer and the hard mask layer to define stack structures and trenches; forming a liner on the sidewalls of the stack structures; forming an isolation structure in the trenches; removing the hard mask layer to form openings exposing the conductive layer; filling the openings with a conductive material to form a floating gate which includes a lower portion covered by the liner and an upper portion not covered by the liner; recessing the isolation structure to expose the sidewalls of the upper portion of the floating gate; forming an inter-gate dielectric (IGD) layer on the isolation structure and the floating gate; and forming a control gate on the IGD layer.

The invention belongs to the technical field of back contact cell preparation, and particularly relates to a back contact cell of an opening semiconductor without etching and a preparation method thereof, and the method comprises the steps: S103, carrying out the polishing or texturing of the back surface of a silicon wafer obtained in S102; s104, depositing an intrinsic crystalline silicon layer on the back surface of the silicon wafer; s105, the non-target deposition area is masked through a hard mask plate, and N-type crystalline silicon layers which are alternately arranged are deposited on the back face; replacing the mask of the hard mask plate to form a P-type crystalline silicon layer and an overlapping region; s106, depositing a conductive film layer on the back surface of the silicon wafer; s107, an opening is formed in the conductive film layer to form an isolation groove, and the width W4 of the isolation groove is controlled to range from 0.03 mm to 0.15 mm; and S108, forming a metal electrode on the back surface. According to the invention, the back semiconductor does not need to be opened by etching, the technological process is greatly simplified, etching damage is avoided, and the cell conversion efficiency, the cell stability and the production yield are improved.

The invention provides an IGBT (Insulated Gate Bipolar Translator) device structure and a preparation method thereof. The preparation method comprises the following steps: forming a plurality of gate trenches in an active region, and forming a gate oxide layer and a polycrystalline silicon layer; forming a grid line mask pattern; forming a polysilicon gate line, and reserving a gate line mask pattern on the polysilicon gate line; a hard mask medium is deposited, a first window and a second window which expose the surface of the active area are formed, and the second window exposes the grid line mask pattern on the grid line; etching is carried out, based on the etching selection ratio, the semiconductor substrate in the first window is partially removed to form an emitter region contact hole, and the grid line mask pattern in the second window is not removed to protect the grid line; and removing the grid line mask pattern in the second window by a wet method to form a grid line contact hole. According to the invention, the preparation of the emitter region contact hole and the line contact hole only needs to use one mask plate for photoetching and etching, compared with the traditional process, one mask plate is effectively reduced, the process flow is simplified, the production period is shortened, and the production efficiency is improved while the tape-out cost is reduced.

In a method of manufacturing a semiconductor device, a first conductive layer is formed over a first interlayer dielectric (ILD) layer disposed over a substrate, a second ILD layer is formed over the first conductive layer, a via is formed in the second ILD layer to contact an upper surface of the first conductive layer, a hard mask pattern is formed over the second ILD layer, the second ILD layer and the first conductive layer are patterned by using the hard mask pattern as an etching mask, thereby forming patterned second ILD layers and first wiring patterns, after the patterning, the hard mask pattern is removed, and a third ILD layer is formed between the patterned second ILD layers and the first wiring patterns.

The invention provides a dual damascene process method, and relates to the technical field of semiconductors. The dual damascene process method comprises the following steps: sequentially forming a dielectric layer, a patterned first hard mask layer, a first planarization layer and a patterned second hard mask layer on a substrate; performing dry etching by using the second hard mask layer to form a through hole stopped on the surface of the substrate; removing the second hard mask layer and the first planarization layer; performing dry etching by using the first hard mask layer to form a groove; removing the first hard mask layer; and forming a metal layer to fill the through hole and the groove so as to obtain the dual damascene structure. According to the process method, the connectivity of the formed through hole can be ensured, and a low-resistance channel of a metal interconnection structure is subsequently formed in the bottom area of the through hole; meanwhile, the first hard mask layer is removed after the through hole is formed, accurate transmission of the key size of the through hole can be ensured, the accuracy of the key size of the subsequently formed metal interconnection structure is improved, and therefore the yield of a chip product and the performance of a device are improved.

The invention discloses a manufacturing method of a SiC groove terminal structure, and belongs to the technical field of semiconductor manufacturing. Comprising the following steps: forming a plurality of P + regions in an N-epitaxial layer to divide the N-epitaxial layer into a terminal region and a plurality of cellular regions, forming a first Pwell region in the terminal region, and respectively forming a JFET injection region, a second Pwell region and an N + region in the cellular regions; defining a gradual change groove terminal ring in the terminal area and defining a grid electrode groove pattern on the cellular area through photoresist; forming a plurality of terminal region grooves of which the depths are gradually increased in the direction of the cellular region in the terminal region through the pattern, and forming a grid electrode groove in the cellular region; and forming side walls on the terminal region trench and the gate trench, and forming a P-type protection region at the bottom. And removing the side wall and the hard mask layer, and further forming a grid electrode, a source electrode and a drain electrode. According to the method, a mask plate required by the process is not added, a single groove and deep pplus scheme is compatible, and the problem of electric field concentration of a deep pplus transition region during reverse voltage withstanding is solved.

The invention relates to a method for forming a semiconductor structure. The forming method comprises the following steps: after a hard mask lamination covering a gate structure and a substrate is formed, protecting an NMOS (N-channel Metal Oxide Semiconductor) forming region by using a graphical mask, and performing first anisotropic etching to expose the substrate on two sides of the gate structure in a PMOS (P-channel Metal Oxide Semiconductor) forming region; removing the patterned mask, performing second anisotropic etching, and removing a part of the nitride film in the hard mask laminated layer in the NMOS forming region while forming a source drain groove in the PMOS forming region; protecting the substrate in the NMOS forming region by using an oxide film in the hard mask lamination, forming a sigma-shaped groove in the PMOS forming region, and performing heteroepitaxy; and finally, removing the residual hard mask laminated layer and the gate upper oxide layer and the gate upper nitride layer in the gate structure by using a maskless process. According to the method, a photomask process is only used when the patterned mask is formed, so that the cost of a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process can be reduced, the damage to the substrate can be reduced, and the performance of a device can be improved.

The invention relates to the technical field of polymer encryption materials, and discloses a stress resolution encryption material, a preparation method thereof, a structural color anti-counterfeit label and an encryption method. The stress resolution encryption material has a hard mask / flexible substrate double-layer structure, and the preparation method comprises the following steps: reacting an acrylic acid-co-acrylate copolymer solution with an anthracene derivative to obtain a hard mask material solution; the preparation method comprises the following steps: dissolving acrylate, diacetone acrylamide and an emulsifier in a solvent, and carrying out polymerization reaction under the action of an initiator to obtain an emulsion; curing and drying the emulsion to obtain a latex film; and coating the surface of the latex film with the hard film material solution. According to the stress resolution encryption material, stress programming exposure is carried out through the light source and the photomask, recording of structural color pattern information is achieved, the stress resolution encryption material has the strain resolution characteristic, and the optical performance of the surface changes along with changes of external stimulus. When the strain resolution encrypted information is read, external equipment is not needed, and the strain resolution encrypted information can be stretched by hands and identified by naked eyes.

The invention discloses a manufacturing method of a memory device and the memory device, and the manufacturing method comprises the steps: providing a semiconductor substrate which comprises a substrate and a hard mask layer on the substrate; a plurality of first grooves are formed in the active area of the substrate from the hard mask layer, one part of the first grooves are located in the storage area, the other part of the first grooves are located in the leading-out area, and the parts, in the substrate, of the first grooves are defined as base body grooves; forming a gate insulating layer and a semi-floating gate at the bottom of the groove of the substrate; one part of the semi-floating gate is in contact with the substrate, and the other part of the semi-floating gate is isolated from the substrate through a gate insulating layer; and forming an inter-gate dielectric layer and a first gate layer in the first groove, forming a control gate of the memory unit in the first groove of the memory region, and forming a lead-out wire of the memory unit in the first groove of the lead-out region, namely, enabling the lead-out region to be in contact with the outside, and solving the problem of voltage drop caused by large buried gate resistance.

A method for forming a semiconductor structure is provided. The method includes providing a substrate with a word line region and a select gate region adjacent to each other, sequentially forming a stack layer and a hard mask layer on the substrate, and forming patterned mandrels on the hard mask layer. The method includes forming sidewall spacers on the patterned mandrels, and forming a patterned photoresist over the select gate region. The method further includes sequentially patterning the hard mask layer and the stack layer to form word lines in the word line region and a select gate in the select gate region, respectively. There is a first spacing between the word lines, and a second spacing between the select gate and the first word line of the word lines closest to the select gate. The second spacing is greater than the first spacing.

A method of semiconductor fabrication includes forming a plurality of mandrel recesses in a mandrel layer over a hard mask layer, performing a first patterning process on a spacer layer that is deposited over the mandrel layer to form a first opening pattern, performing a second patterning process to etch portions of the mandrel layer to form a second opening pattern, performing a third patterning process to form a third opening pattern in the hard mask layer based on the first opening pattern and the second opening pattern, and forming, through the hard mask layer, metal lines that are in a semiconductor layer under the hard mask layer and that are arranged in a pattern which corresponds to the third opening pattern.

A method includes providing a first channel layer of a first transistor and a second channel layer of a second transistor over a substrate, forming a dipole layer over the first channel layer and the second channel layer, forming a patterned hard mask covering the second channel layer and exposing the first channel layer, removing the dipole layer from the first channel layer, removing the patterned hard mask, performing a thermal drive-in process, forming an interfacial dielectric layer on the first channel layer and the dipole layer, and forming a high-k dielectric layer on the interfacial dielectric layer. The dipole layer includes a p-dipole material.

The invention provides a semiconductor structure and a preparation method thereof, and the method comprises the steps: providing a semiconductor material layer which is used for forming at least two grooves; a first hard mask layer is formed on one side of the semiconductor material layer, the first hard mask layer is etched to form at least two openings, and the openings are used for defining the key size of the groove; forming an etching guide structure in the opening, wherein the upper surface of the etching guide structure is higher than the upper surface of the first hard mask layer; forming a dielectric layer covering the first hard mask layer and the etching guide structure, wherein the upper surface of the dielectric layer is flush with the upper surface of the etching guide structure; forming a photoresist layer on one side, deviating from the first hard mask layer, of the dielectric layer, and performing exposure of different depths on the photoresist layer at the corresponding position of the opening to form photoresist grooves of different depths; and performing one-time etching on the etching guide structure and the semiconductor material layer based on the photoresist grooves with different depths so as to form grooves with different depths in the semiconductor material layer.

A memory array includes a first bit-line stack disposed over a substrate, a first spacer, a first data storage structure, and a word line. The first bit-line stack includes a first bit line disposed over the substrate; and a first hard mask layer partially covering a top surface of the first bit line. The first spacer is disposed on a lower sidewall of a first sidewall of the first bit line. The first hard mask layer and the first spacer expose a top corner of the first bit line. The first data storage structure covers the top corner of the first bit line. The word line covers a sidewall of the first data storage structure.

The invention discloses an adversarial sample generation method and device for a face forgery detection model. The method comprises the following steps: obtaining a real category attention graph and a false category attention graph of an original sample by using a white-box face counterfeiting detection model, fusing the real category attention graph and the false category attention graph to obtain a fused attention graph, and processing the fused attention graph to obtain a dual hard mask; generating global disturbance of the original sample by using a spatial domain disturbance generator obtained by pre-training; cutting the global disturbance by using the dual hard mask to obtain local disturbance; and superposing the local disturbance to the original sample to obtain an adversarial sample. According to the scheme, the face forgery detection model can be attacked from a real area and a false area, a high attack success rate is achieved for the white box face forgery detection model and the black box face forgery detection model, and the attack effect of the confrontation sample is improved.

The invention provides an inclined grating preparation method and device, and relates to the technical field of grating manufacturing. The method comprises the steps of performing ion beam etching on a hard mask film layer of a to-be-etched part based on a first inclination angle of an inclined table for placing the to-be-etched part to obtain a mask etching part; and performing reactive ion beam etching on the material layer of the mask etching piece based on the second inclination angle of the inclined table on which the mask etching piece is placed to obtain an inclined grating structure. The device comprises a controller used for determining a first inclination angle and a second inclination angle of an inclined table based on a design structure of a to-be-etched part; controlling an inclined table to move to a first inclination angle, and controlling first etching equipment to perform ion beam etching on the hard mask layer of the to-be-etched part to obtain a mask etching part; and controlling the tilting table to move to a second tilting angle, and controlling the second etching equipment to perform reactive ion beam etching on the material layer of the mask etching piece to obtain the tilting grating structure.

The invention provides a method for improving the thickness of an oxide on the side wall of a deep trench, and the method comprises the steps: providing a substrate, forming an epitaxial layer on the substrate, and sequentially forming a pad oxide layer, an etching stop layer, a polycrystalline silicon layer and a hard mask layer on the epitaxial layer; a photoresist layer is formed on the hard mask layer, the exposure focal length is adjusted to open the photoresist layer so as to define the forming position of the deep groove, the exposed hard mask layer is opened through etching to form an opening pattern, the side wall of the opening pattern is in an inclined shape, and the section of the opening pattern is in a trapezoid shape with the wide upper portion and the narrow lower portion; a deep groove is formed through etching, and the remaining photoresist layer is removed; forming a thermal oxide layer on the side walls of the polycrystalline silicon layer and the deep trench by using a thermal oxidation method, wherein the thermal oxide layer at the side wall of the polycrystalline silicon layer is in a convex shape; etching the thermal oxide layer to enable the thermal oxide layer to be reserved on the side wall of the deep groove; and forming a filling layer for filling the residual deep groove by using a deposition and grinding method. The method can improve the thickness of the oxide layer on the side wall of the deep trench.

The invention provides a manufacturing method for integrating a BCD device and an SGT device by using selective epitaxy, which comprises the following steps of: providing a highly doped substrate of a first conduction type, forming a hard mask layer on the substrate, etching the substrate on the formation region of the BCD device to form a groove, forming an oxide layer on the exposed substrate, and forming an SGT device on the oxide layer, etching to remove the oxide layer at the bottom of the groove, forming a low-doped epitaxial layer which fills the groove and is of the second conductive type, and grinding the epitaxial layer and the hard mask layer to the substrate; forming a partial structure of the SGT device on the substrate on the forming region of the SGT device; forming a shallow trench isolation structure to define an active region of the BCD device; forming a first well of the SGT device by ion implantation, wherein the first well is of a second conductive type; a well region and a drift region of the BCD device are formed by ion implantation. According to the invention, BCD and SGT processes are integrated, single-chip integration can be realized, the manufacturing cost is reduced, and the product competitiveness is improved.