1672 results about "Hard mask" patented technology

The invention provides a method for adjusting the height of a grid electrode and a semiconductor structure, and belongs to the field of semiconductors. The method of adjusting gate height includes providing a semiconductor substrate. And etching back the hard mask layer in the NMOS region to reduce the thickness of the hard mask layer in the NMOS region. And after back etching, gate structures are respectively formed in the PMOS region and the NMOS region. And filling a dielectric layer, wherein the dielectric layer covers the gate structure of the NMOS region. And patterning a groove, etching the groove in the PMOS region, and when the groove is etched in the PMOS region, the thickness lost by the hard mask layer in the PMOS region is basically equal to the thickness lost by etching the hard mask layer in the NMOS region. By depositing the hard mask layer and etching the hard mask layer, the thickness of the hard mask layer in the PMOS region is basically equal to that of the hard mask layer in the NMOS region, so that the height of the formed grid electrode in the PMOS region is basically equal to that of the grid electrode in the NMOS region, and the performance of the device can be improved.

The invention provides a germanium-silicon groove preparation method, which comprises the following steps of: forming a PMOS (P-channel Metal Oxide Semiconductor) gate structure and an NMOS (N-channel Metal Oxide Semiconductor) gate structure on a semiconductor substrate, arranging a first silicon nitride layer, a silicon oxide layer and a second silicon nitride layer in hard mask layers of the PMOS gate structure and the NMOS gate structure, exposing the second silicon nitride layer through a gate side wall, and covering a germanium-silicon mask layer, a patterned photoresist protection NMOS gate structure is formed, the germanium-silicon mask layer exposed in the PMOS region is etched, a groove is formed, and at least part of the second silicon nitride layer is reserved at the top of the PMOS gate to protect the silicon oxide layer; according to the method, the first silicon nitride layer and the germanium-silicon mask layer are etched, germanium-silicon deposition is carried out, and the residual second silicon nitride layer and the germanium-silicon mask layer are removed together through wet etching, so that the height difference of the hard mask layer caused by the conventional process of the PMOS gate and the NMOS gate is eliminated, the process load is avoided, the process steps are simplified, and the process cost is reduced.

A semiconductor structure is provided. The semiconductor structure includes a substrate, a target layer on the substrate, and a hard mask layer doped with a group IV-A element on the target layer. The number of sp3 orbital bonds in the hard mask layer is greater than the number of sp2 orbital bonds.

The invention discloses a manufacturing method of a semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, forming a dummy gate on the substrate, and forming a hard mask layer on the dummy gate; forming side wall structures on two sides of the dummy gate; forming a contact hole etching stop layer on the substrate, the side wall structure and the pseudo gate, wherein the material of the contact hole etching stop layer is the same as that of the hard mask layer; forming an interlayer dielectric layer on the contact hole etching stop layer, and planarizing the interlayer dielectric layer to the residual preset thickness of the hard mask layer; oxidizing the hard mask layer, a part of the contact hole etching stop layer and a part of the side wall structure to form a surface oxide layer; synchronously removing the surface oxide layer and a part of the interlayer dielectric layer, wherein the surface of the dummy gate is flush with the surfaces of the interlayer dielectric layers on the two sides; and removing the dummy gate to form a metal gate. According to the manufacturing method of the semiconductor device provided by the invention, the height of the formed metal gate can be ensured, the manufacturing process is simple, and the controllability is high.

Various embodiments of improved process flows and methods are provided herein for etching high aspect ratio (HAR) features in carbon-containing hard mask layers. In the disclosed embodiments, the improved process flows and methods combine sidewall passivation and mask de-clogging steps in a single plasma process step to improve throughput when etching HAR features (such as vias, contact holes, trenches, etc.) within a carbon-containing hard mask layer. In doing so, the improved process flows and methods disclosed herein protect the sidewall surfaces of the carbon-containing hard mask layer and prevent bowing during the HAR etch process, while also reducing processing time and improving throughput.

The invention provides a method for forming a strained silicon layer and a semiconductor structure, which comprises the steps of covering a semiconductor layer and a gate stack structure to form an etching stop layer, and the semiconductor layer comprises a first device region and a second device region which are separated from each other; forming an auxiliary side wall surrounding the side wall of the gate stack structure on the etching stop layer; forming a patterned hard mask layer; taking the patterned hard mask layer as an etching mask, and performing selective etching on the second device region through a wet etching process to form a sigma trench; and growing a strained silicon layer in the sigma groove. According to the invention, on the premise of not sacrificing the consistency of the critical dimensions of the sigma trench, the etching load effect caused by dry etching in the forming process of the sigma trench is avoided.

Methods for making thin-films on semiconductor substrates, which may be patterned using EUV, include: mixing a vapor stream of an organometallic precursor with a vapor stream of a counter-reactant so as to form a polymerized organometallic material; and depositing the organometallic polymer-like material onto the surface of the semiconductor substrate. The mixing and depositing operations may be performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD component, such as a discontinuous, ALD-like process in which metal precursors and counter-reactants are separated in either time or space.

The invention belongs to the technical field of back contact cell preparation, and particularly relates to a back contact cell of an opening semiconductor without etching and a preparation method thereof, and the method comprises the steps: S103, carrying out the polishing or texturing of the back surface of a silicon wafer obtained in S102; s104, depositing an intrinsic crystalline silicon layer on the back surface of the silicon wafer; s105, the non-target deposition area is masked through a hard mask plate, and N-type crystalline silicon layers which are alternately arranged are deposited on the back face; replacing the mask of the hard mask plate to form a P-type crystalline silicon layer and an overlapping region; s106, depositing a conductive film layer on the back surface of the silicon wafer; s107, an opening is formed in the conductive film layer to form an isolation groove, and the width W4 of the isolation groove is controlled to range from 0.03 mm to 0.15 mm; and S108, forming a metal electrode on the back surface. According to the invention, the back semiconductor does not need to be opened by etching, the technological process is greatly simplified, etching damage is avoided, and the cell conversion efficiency, the cell stability and the production yield are improved.

The invention provides a dual damascene process method, and relates to the technical field of semiconductors. The dual damascene process method comprises the following steps: sequentially forming a dielectric layer, a patterned first hard mask layer, a first planarization layer and a patterned second hard mask layer on a substrate; performing dry etching by using the second hard mask layer to form a through hole stopped on the surface of the substrate; removing the second hard mask layer and the first planarization layer; performing dry etching by using the first hard mask layer to form a groove; removing the first hard mask layer; and forming a metal layer to fill the through hole and the groove so as to obtain the dual damascene structure. According to the process method, the connectivity of the formed through hole can be ensured, and a low-resistance channel of a metal interconnection structure is subsequently formed in the bottom area of the through hole; meanwhile, the first hard mask layer is removed after the through hole is formed, accurate transmission of the key size of the through hole can be ensured, the accuracy of the key size of the subsequently formed metal interconnection structure is improved, and therefore the yield of a chip product and the performance of a device are improved.

A method includes providing a first channel layer of a first transistor and a second channel layer of a second transistor over a substrate, forming a dipole layer over the first channel layer and the second channel layer, forming a patterned hard mask covering the second channel layer and exposing the first channel layer, removing the dipole layer from the first channel layer, removing the patterned hard mask, performing a thermal drive-in process, forming an interfacial dielectric layer on the first channel layer and the dipole layer, and forming a high-k dielectric layer on the interfacial dielectric layer. The dipole layer includes a p-dipole material.

The invention provides a semiconductor structure and a preparation method thereof, and the method comprises the steps: providing a semiconductor material layer which is used for forming at least two grooves; a first hard mask layer is formed on one side of the semiconductor material layer, the first hard mask layer is etched to form at least two openings, and the openings are used for defining the key size of the groove; forming an etching guide structure in the opening, wherein the upper surface of the etching guide structure is higher than the upper surface of the first hard mask layer; forming a dielectric layer covering the first hard mask layer and the etching guide structure, wherein the upper surface of the dielectric layer is flush with the upper surface of the etching guide structure; forming a photoresist layer on one side, deviating from the first hard mask layer, of the dielectric layer, and performing exposure of different depths on the photoresist layer at the corresponding position of the opening to form photoresist grooves of different depths; and performing one-time etching on the etching guide structure and the semiconductor material layer based on the photoresist grooves with different depths so as to form grooves with different depths in the semiconductor material layer.

The invention provides an inclined grating preparation method and device, and relates to the technical field of grating manufacturing. The method comprises the steps of performing ion beam etching on a hard mask film layer of a to-be-etched part based on a first inclination angle of an inclined table for placing the to-be-etched part to obtain a mask etching part; and performing reactive ion beam etching on the material layer of the mask etching piece based on the second inclination angle of the inclined table on which the mask etching piece is placed to obtain an inclined grating structure. The device comprises a controller used for determining a first inclination angle and a second inclination angle of an inclined table based on a design structure of a to-be-etched part; controlling an inclined table to move to a first inclination angle, and controlling first etching equipment to perform ion beam etching on the hard mask layer of the to-be-etched part to obtain a mask etching part; and controlling the tilting table to move to a second tilting angle, and controlling the second etching equipment to perform reactive ion beam etching on the material layer of the mask etching piece to obtain the tilting grating structure.

The invention provides a preparation method of a shallow trench isolation structure and a semiconductor device, and the preparation method comprises the following steps: providing a substrate which comprises a substrate and a patterned hard mask layer on the substrate; depositing a hard mask oxide layer on the substrate, wherein the hard mask oxide layer covers the surface of the hard mask layer and the side wall and the bottom wall of the pattern; etching the substrate to form a plurality of first grooves corresponding to the patterns on the hard mask layer, wherein the first grooves extend to the substrate, and hard mask oxide layers are reserved on the side walls of the patterns of the hard mask layer; removing the hard mask oxide layer on the side wall of the pattern of the hard mask layer through wet etching to form a second groove; forming a liner oxide layer on the side wall and the bottom wall of the second groove; filling the second groove; removing the hard mask layer; and growing a sacrificial oxide layer in the active region. According to the preparation method of the shallow trench isolation structure, the unfilled corner problem of shallow trench isolation can be reduced, the electric leakage of a semiconductor device is improved, and the overall performance of the semiconductor device is improved.

Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The method includes forming a stack of semiconductor layers on a substrate, depositing a hard mask over the stack of semiconductor layers, forming, over the hard mask, a first photoresist layer that defines first openings that expose portions of the hard mask that are to be etched, etching the portions of the hard mask to form a hard mask fin structure, forming, over a first portion of the hard mask fin structure, a second photoresist layer that defines a second opening that exposes a second portion of the hard mask fin structure that is to be etched, etching the second portion of the hard mask fin structure to form a modified hard mask fin structure, and etching portions of the stack of semiconductor layers to form a fin structure.

The invention belongs to the field of micro-nano manufacturing, and particularly relates to a preparation method of a high-precision large-area ultrathin hollowed-out hard mask. The invention provides a preparation method of a high-precision large-area ultrathin hollowed-out hard mask, and the method comprises the steps: carrying out the multi-step etching of a thin film layer deposited on the front surface of a silicon substrate, keeping a part of thickness of the thin film layer in the first etching process, and completely etching the thin film layer after the wet etching of the silicon substrate is completed. When the pattern size is smaller or the thin film layer is thinner, the thin film layer can be prevented from being broken in the wet etching process.

A trench in a semiconductor substrate is lined with a first insulation layer. A hard mask layer deposited on the first insulation layer is used to control performance of an etch that selectively removes a first portion of the first insulating layer from an upper trench portion while leaving a second portion of first insulating layer in a lower trench portion. After removing the hard mask layer, an upper portion of the trench is lined with a second insulation layer. An opening in the trench that includes a lower open portion delimited by the second portion of first insulating layer in the lower trench portion and an upper open portion delimited by the second insulation layer at the upper trench portion, is then filled by a single deposition of polysilicon material forming a unitary gate / field plate conductor of a field effect rectifier diode.

The invention provides a low-specific-on-resistivity GaN HEMT device and a preparation method thereof. The preparation method comprises the following steps: obtaining a thick-barrier GaN epitaxial structure; manufacturing a low-loss etched hard mask medium on a thick-barrier GaN epitaxial structure of the GaN HEMT device with low specific on-resistivity to form a passivation medium film; defining a gate region of the medium by utilizing a photoetching process, and defining a hard mask medium pattern by adopting a medium etching process; carrying out barrier layer groove etching by adopting a GaN low-loss etching process; etching is accurately stopped; adopting a molecular beam epitaxy process to perform secondary epitaxy on a p-GaN layer in a selected area so as to realize complete depletion of two-dimensional electron gas in a grid area; removing the polycrystalline GaN on the hard mask medium; and after horizontal GaN HEMT tape-out, metal deposition of a source electrode, a drain electrode and a grid electrode of the GaN HEMT is carried out. According to the method, a thick barrier layer structure is adopted, the specific on-resistivity limitation of the device is reduced, the device has low specific on-resistivity, the reliability of the grid electrode is improved, and the stability of the device is improved.

The invention relates to a semiconductor manufacturing method and a semiconductor structure, and belongs to the technical field of semiconductors. The semiconductor manufacturing method comprises the following steps: providing a first semiconductor substrate; forming a first dielectric layer over the first semiconductor substrate; patterning the first dielectric layer to form a first groove; depositing metal on the first dielectric layer to form a metal filling part filled in the first groove and a metal covering layer higher than the plane where the top of the first dielectric layer is located; executing a planarization process to remove the metal covering layer, and enabling the top of the metal filling part to be flush with the top of the first dielectric layer; and forming a first hard mask layer covering the first dielectric layer and the metal filling part. By optimizing the manufacturing process, the defects such as surface depression are avoided, meanwhile, the risk of cracking caused by mismatching of thermal expansion is reduced, and the reliability of the semiconductor device is improved.

A semiconductor device is provided. The semiconductor device includes a first region having a first gate structure disposed on a substrate and a second region having a second gate structure disposed on the substrate, a hard mask formed on the substrate, the first gate structure, and the second gate structure, a deep trench formed in the substrate between the first region and the second region, and formed to penetrate the hard mask to reach an inside of the substrate, and a planarized gap-fill insulating layer formed on the second gate structure and formed inside the deep trench. A topmost surface of the planarized gap-fill insulating layer and a topmost surface of the hard mask are coplanar.

Semiconductor structures and methods of forming the same are provided. An exemplary method incudes forming a first dielectric layer over a first conductive feature, forming a conductive via extending through the first dielectric layer and coupled to the first conductive feature, forming a hard mask layer over the conductive via, patterning the hard mask layer to form a first opening exposing the first dielectric layer; forming a sacrificial layer to partially fill the first opening, forming a porous dielectric layer on the sacrificial layer, after the forming of the porous dielectric layer, selectively removing the sacrificial layer to form an air gap, forming a second dielectric layer over the porous dielectric layer, and replacing a portion of the patterned hard mask layer disposed directly over the conductive via with a second conductive feature.

The invention provides a manufacturing method of a type-II superlattice medium-wave infrared focal plane array chip and an infrared detector, and belongs to the field of infrared focal plane array chips. The problem that in the prior art, the surface leakage current of an infrared focal plane array chip is large due to the fact that the mesa etching depth is large is solved. The method comprises the following steps: growing and cleaning an epitaxial material; hard mask deposition, mesa photoetching and etching: obtaining a required mesa pattern on the hard mask through a photoetching technology, then etching an epitaxial material, etching the epitaxial material to form the mesa pattern, the mesa pattern comprising an upper electrode region and a lower electrode region, etching the upper electrode region to the boundary of the barrier layer and the absorption region, and etching the lower electrode region to the boundary of the barrier layer and the absorption region; etching a lower electrode region to the lower ohmic contact layer; manufacturing a metal electrode; a connecting piece is manufactured on the metal electrode to be connected with a reading circuit, and manufacturing of the infrared focal plane array chip is completed; the invention is applied to the II-type superlattice medium-wave infrared detector.

The invention discloses a manufacturing method of a trench gate semiconductor power device. The manufacturing method comprises the following steps: forming a first hard mask layer on a first epitaxial layer; and performing graphical etching on the first hard mask layer to open the forming region of the gate trench. And etching the first epitaxial layer to form a gate trench. And after the first hard mask layer is removed, performing a first thermal oxidation process to form a first field oxide layer on the inner side surface of the gate trench and the outer surface of the gate trench. And performing a first CVD growth process to form a second field oxide layer, and overlapping the first field oxide layer and the second field oxide layer to form a third field oxide layer. And performing a first CMP process to remove the third field oxide layer outside the gate trench. And forming a first polycrystalline silicon layer to completely fill the gate trench and extend out of the gate trench. And performing a second CMP process to flatten the first polycrystalline silicon layer. The structure consistency of the gate trench region and the platform region can be improved at the same time, and the performance and the yield of the device can be comprehensively improved.

A method includes forming a fin protruding from a substrate, the fin including an epitaxial stack over a fin base and a hard mask layer over the epitaxial stack, the epitaxial stack including first and second semiconductor layers of different material compositions, performing a first etching process to etch the hard mask layer, the first etching process including applying a first combination of etchants, performing a second etching process to etch the epitaxial stack, the second etching process including applying a second combination of etchants, and performing a third etching process to etch the fin base, the third etching process including applying a third combination of etchants. The first, second, and third combinations of etchants are different from each other.

The invention relates to an epitaxial structure of a low-specific on-resistivity GaN HEMT and a preparation method thereof, and the preparation method comprises the steps: S1, sequentially growing an initial layer, a buffer layer, a channel layer, a first insertion layer, a first barrier layer, a second insertion layer and a second barrier layer on a substrate from bottom to top, and obtaining a thick barrier epitaxial wafer; s2, preparing a hard mask layer, patterning and etching the hard mask layer, then transferring the hard mask layer to the upper surface of the thick barrier epitaxial wafer, and etching the thick barrier epitaxial wafer to the upper surface of the second insertion layer; s3, secondarily growing a p-GaN layer on the upper surface of the second insertion layer in the gate region; and S4, removing the polycrystalline GaN in a non-gate region, depositing metal on the p-GaN layer to manufacture a gate, and depositing metal on two sides of the structure to manufacture a source and a drain respectively. By selectively growing the p-GaN layer in the grid region, two-dimensional electron gas in a channel is effectively exhausted, and the carrier concentration of the region below the grid is remarkably reduced.

The invention discloses a contact hole forming method and an image sensor, and the method comprises the steps: forming a contact hole etching stop layer on a device structure of a logic region and a pixel region of the image sensor; filling a thickened interlayer dielectric layer on the contact hole etching stop layer, wherein the increased thickness is equal to the thickness of the protective layer; forming a first hard mask layer and a second hard mask layer on the interlayer dielectric layer; etching a contact hole in the logic region by taking the first hard mask layer as a mask, and only forming a mask pattern on the pixel region under the protection of the second hard mask layer; forming a sacrificial layer for protecting the logic region contact hole; etching a contact hole of a pixel region until the contact hole is above the protective layer; the protection layer below the pixel area contact hole is etched downwards continuously, and the interlayer dielectric layer with the same thickness is etched at the same time; and removing the sacrificial layer of the logic region and filling all the contact holes. The contact holes of the logic region and the pixel region can be etched separately, over etching of the substrate in the logic region due to height difference is avoided, and electrical stability can be maintained.

A method of forming an electronic device includes forming a patterned stack including a first electrode layer deposited over a substrate, a ferroelectric material layer disposed over the first electrode layer, and a hard mask layer disposed over the ferroelectric material layer; forming a sidewall spacer along a sidewall of the patterned stack, the sidewall spacer including a metal oxide; etching the sidewall spacer selectively relative to the hard mask layer to expose a portion of a sidewall of the ferroelectric material layer; and depositing a second electrode layer over the ferroelectric material layer after removing the hard mask layer.

The invention provides a mask and a preparation method thereof, and relates to the technical field of semiconductor manufacturing and the technical field of photoetching, and the preparation method comprises the following steps: forming a mask absorption layer, a hard masking layer and a photoresist layer which are sequentially stacked on a substrate; performing exposure and development on the photoresist layer based on the mask pattern, and forming a target pattern in the photoresist layer; etching the hard masking layer by taking the photoresist layer on which the target pattern is formed as a masking layer, and transferring the target pattern to the hard masking layer; etching the mask absorption layer by taking the photoresist layer with the target pattern and the hard mask layer as a mask layer together, adjusting the flow ratio of different gases in the first etching gases in different etching stages, and etching and transferring the target pattern to the mask absorption layer; and removing residues on the mask absorption layer, and carrying out post-treatment to obtain the mask plate.

The invention provides a method for forming a semiconductor structure, which comprises the following steps of: providing a semiconductor substrate which comprises a first dielectric layer and a metal plug positioned in the first dielectric layer; sequentially forming a first isolation layer, a second dielectric layer, a second isolation layer and a hard mask layer on the top surface of the first dielectric layer; etching and removing the hard mask layer, the second isolation layer and a part of the second dielectric layer in a region corresponding to the metal plug to form an opening; the hard mask layer is removed; and etching is continued along the opening so as to expose the metal plug. The invention also provides a semiconductor structure. According to the semiconductor structure and the forming method provided by the invention, hole defects can be prevented from being formed in the metal layer when the opening is filled with the metal layer.

The invention discloses a semiconductor structure manufacturing method and a semiconductor structure, and the method comprises the steps: providing a silicon carbide substrate of which one side is provided with a plurality of first mask structures, forming second mask structures on the exposed surfaces of the first mask structures, taking the second mask structures and the first mask structures as masks, and carrying out the etching of the silicon carbide substrate, forming a high aspect ratio etching structure with a certain etching depth in the silicon carbide substrate; the material of the second mask structure and the material of the first mask structure are the same hard mask material, the second mask structure is completely etched and removed at the etching end point, and the surface of the remaining first mask structure is exposed. According to the method, the thickness insufficiency of an original mask can be compensated, damage is reduced, the protection effect on the surface of the silicon carbide substrate is improved, the defects caused by the original mask can be overcome, it is ensured that an ideal final etching morphology is obtained, and meanwhile a larger etching depth-to-width ratio can be achieved.

The invention discloses a semiconductor deep silicon etching method and application thereof. The semiconductor deep silicon etching method comprises the following steps: providing a structure to be etched, wherein the structure comprises a silicon structure and a silicon oxide layer; patterning etching is carried out; growing silicon oxide as a filling layer which comprises a side surface part and a bottom surface part, filling the first inner wall to form a second inner wall, and enabling the second inner wall and the bottom surface to be closer to 90 degrees; performing secondary etching to expose the silicon structure again; and forming a deep silicon etching structure by adopting a deep silicon etching process. According to the method, the opening width and the opening side wall morphology of the hard mask are adjusted by utilizing a transverse growth method, on one hand, the width of the mask opening can be accurately adjusted by controlling the transverse growth condition, and high-precision photoetching equipment is not needed; and on the other hand, the deep silicon etching quality can be remarkably improved by adjusting the shape of the side wall of the opening, and various abnormities of the deep silicon etching groove can be avoided without complex procedures and expensive equipment.