260results about How to "Easy to etch" patented technology

A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.

A method of making a transparent conductive film includes the steps of: providing a carbon nanotube array. At least one carbon nanotube film extracted from the carbon nanotube array. The carbon nanotube films are stacked on the substrate to form a carbon nanotube film structure. The carbon nanotube film structure is irradiated by a laser beam along a predetermined path to obtain a predetermined pattern. The predetermined pattern is separated from the other portion of the carbon nanotube film, thereby forming the transparent conductive film from the predetermined pattern of the carbon nanotube film.

A bonded assembly is provided. The bonded assembly comprises: (a) a first substrate having a plurality of etched trenches defined in a first bonding surface; and (b) a second substrate having a second bonding surface. The second bonding surface is bonded to the first bonding surface with an adhesive and the adhesive is received, at least partially, in the plurality of etched trenches. Semiconductors chips bonded to a second substrate exemplify the advantages of the invention. The etched trenches allow the adhesive bond to be strengthened whilst avoiding increased surface roughening.

The invention relates to a process for manufacturing smooth surface roughened electrolytic copper foil, which comprises a step of pickling, a step of primary smooth surface roughening, a step of secondary smooth surface roughening, a step of primary smooth surface curing, a step of secondary smooth surface curing, a step of double-size anti-oxidization treatment, a step of double side passivation and a step of smooth surface coupling agent treatment, which are accomplished continuously on the same production line. Compared with the prior art, the smooth surface roughened electric copper foil manufactured by the process for manufacturing the smooth surface roughened electrolytic copper foil has the advantages of short copper teeth, easy etching, and high impedance controllability. When the copper foil is used in production of downstream products, the needs of blackening micro corrosion and toughening treatment are obviated, so the manufacturing process is shortened, and the short circuit rate and open circuit rate are lowered; meanwhile, the copper foil manufactured by the process has the same quality as the conventional high-precision or double-side toughened electrolytic copper foil, is produced at low cost and is more suitable for manufacturing the inner layers of high-precision multilayer plates and high-density fine line printed circuit boards (PCBs).

Embodiments of the invention generally provide methods for forming a multilayer rear surface passivation layer on a solar cell substrate. The method includes forming a silicon oxide sub-layer having a net charge density of less than or equal to 2.1×10¹¹ Coulombs/cm² on a rear surface of a p-type doped region formed in a substrate comprising semiconductor material, the rear surface opposite a light receiving surface of the substrate and forming a silicon nitride sub-layer on the silicon oxide sub-layer. Embodiments of the invention also include a solar cell device that may be manufactured according methods disclosed herein.

To produce an ultra-thin copper foil with a carrier foil that microscopic crystal grains can be deposited without being affected by the surface roughness of a carrier foil, etching can be performed until an ultra-fine width such that line/space is 15 μm or less, and the microscopic line and a wiring board have large peel strength even after line of 15 μm is etched. An ultra-thin copper foil wherein a carrier foil, a peeling layer, an ultra-thin copper foil are laminated in this order, the ultra-thin copper foil (before roughening treatment is performed) is an electrolytic copper foil that surface roughness of 2.5 μm as ten point height of roughness profile, and the minimum distance between peaks of salients of a based material is 5 μm or more. Moreover, the surface of the ultra-thin copper foil is performed roughening treatment.

In the bevel etching apparatus relating to the present invention, a substrate is inserted between electrically connected electrodes. A high-frequency power source is connected to the electrodes, and ground potential is applied to a support unit that supports the substrate. Gas (atmosphere) is supplied to the gap between the electrodes and the application of the high-frequency electric power to the electrodes causes the generation of atmospheric-pressure glow discharge between the electrode and the substrate. Bevel etching is performed by rotating the substrate along the circumferential direction in this condition. According to this construction, the bevel etching can be simultaneously performed to the front surface, the rear surface and the side of the substrate without causing any configuration change in the substrate.

The invention provides a preparation method of a nanometer metal grating and a nanometer metal grating. The method includes providing a substrate on which a metal layer is arranged; forming an impression glue layer on the metal layer; impressing the impression glue layer with an impression template with a grating period pattern; solidifying a impression glue layer, removing the impression template after the solidification, forming the impression glue with the grating period pattern, and remaining the impression glue at the bottom of the grating period pattern; removing the residual impression glue by means of oxygen ashing, exposing the metal layer at the bottom of the grating period pattern, and forming a metal oxide film on the surface of the exposed metal layer; removing the impression glue with the grating period pattern; and taking the metal oxide film as a mask layer, and patterning the metal layer to form a nanometer metal grating. The method is advantageous in that the problem that the metal layer in the prior art cannot be etched after the oxidation is solved; and the metal oxide film is taken as the mark layer for the subsequent technology, and can be used as a nanometer metal grating protective layer.

A semiconductor memory device in which a plurality of capacitors each including a columnar lower electrode, a capacitor insulation film and an upper electrode are stacked with interlayer films therebetween, a contact plug connects an upper face of each lower electrode of a lower layer with a bottom face of each lower electrode of an upper layer, and another contact plug connects upper electrodes of the capacitors in respective layers with each other.

A novel flexible printed circuit substrate can be processed into a flexible printed circuit board having a high-accuracy connecting part which does not cause a connection failure when it is connected to a connector even if a pitch between two adjacent terminals is further reduced. The flexible printed circuit substrate has dummy patterns which are formed, simultaneously with the terminals, on the sides of the connecting part, in a shape corresponding to the outline of both sides of connecting part which are used for positioning the terminals when the connecting part is attached to the connector. The dummy patterns are used as masks when a base film is subjected to a laser process.

A first metal layer of tungsten is formed on a substrate in a scale. A second metal layer of chromium is formed on the first metal layer. The second metal layer is selectively removed with a mask of resist and an etching stopper of the first metal layer to form an optical grating.

The invention discloses a composite color organic electroluminescent display panel, comprising a base panel and several pixel elements arranged in matrix-type on the base panel to form the display panel, while each pixel element comprises a plurality of pixel sub-elements which can emit monochromatic light as red, green or blue. Then, the invention arranges the pixel sub-element near to the adjacent pixel sub-elements which has same monochromatic light side by side via the geometrical arrangement design of pixel sub-elements, to apply the process of manufacturing red, green, blue pixel sub-elements of low molecule organic luminescent diode metallic shield film or the high polymer organic luminescent diode ink-jet of high-definition panel.

A nonvolatile memory cell employing a plurality of dielectric nanoclusters and a method of fabricating the same are disclosed. In one embodiment, the nonvolatile memory cell comprises a semiconductor substrate having a channel region. A control gate is disposed above the channel region. A control gate dielectric layer is disposed between the channel region and the control gate. A plurality of dielectric nanoclusters are disposed between the channel region and the control gate dielectric layer. Each nanocluster may be separated from adjacent nanoclusters by the control gate dielectric layer. A tunnel oxide layer is disposed between the plurality of dielectric nanoclusters and the channel region. Further, a source and a drain are formed in the semiconductor substrate.

A GaN based substrate is obtained with a simple etching. The GaN based substrate is separate from another base substrate with the etching. The whole process is easy and costs low. The substrate is made of a material having a matching lattice length for a lattice structure so that the substrate has good characteristics. And the GaN based substrate has good heat dissipation so that the stability and life-time of GaN based devices on the GaN based substrate are enhanced even when they are constantly operated under a high power.

A semiconductor device and a method for making a semiconductor device having a pillar-shaped capacitor storage node compatible with a high dielectric film, wherein the pillar-shaped capacitor storage node includes a thick conductive metal layer that is easily etched and a thin conductive layer completely coating the thick conductive metal layer. The thin conductive layer protects the thick conductive metal layer during subsequent high dielectric deposition and annealing and various oxidation process.

A method embodiment for patterning a semiconductor device includes forming a plurality of mandrels over a substrate, and forming a multilayer spacer layer over the plurality of mandrels. The multilayer spacer layer is formed by conformably depositing a spacer layer over the plurality of mandrels and treating the spacer layer with plasma. The plurality of mandrels is exposed by etching a top portion of the multilayer spacer layer, thereby forming a multilayer spacer.

In a variable resistance nonvolatile storage element, an electrode suitable for a variable resistance operation and formed of a metallic nitride layer containing Ti and N is provided. In a nonvolatile storage device including: a first electrode; a second electrode; and a variable resistance layer which is sandwiched between the first electrode and the second electrode and in which a resistance value changes to two different resistance states, at least one of the first electrode and the second electrode is an electrode including a metallic nitride layer containing at least Ti and N, and a mole ratio (N/Ti ratio) between Ti and N in at least a part of the metallic nitride layer, the part being in contact with the variable resistance layer is 1.15 or more and a film density is 4.7 g/cc or more.

Aspects disclosed in the detailed description include nanowire channel structures of continuously stacked heterogeneous nanowires for complementary metal oxide semiconductor (CMOS) devices. Each of the nanowires has a top end portion and a bottom end portion that are narrower than a central portion. Furthermore, vertically adjacent nanowires are interconnected at the narrower top end portions and bottom end portions. This allows for connectivity between stacked nanowires and for having separation areas between vertically adjacent heterogeneous nanowires. Having the separation areas allows for gate material to be disposed over a large area of the heterogeneous nanowires and, therefore, provides strong gate control, a shorter nanowire channel structure, low parallel plate parasitic capacitance, and low parasitic channel capacitance. Having the nanowires be heterogeneous, i.e., fabricated using materials of different etching sensitivity, facilitates forming the particular cross section of the nanowires, thus eliminating the use of sacrificial masks/layers to form the heterogeneous nanowires.