699results about How to "Reduce aspect ratio" patented technology

Disclosed herein are a semiconductor device and a method of manufacturing the same that increases the reliability of these devices as size design limitations decrease. Generally, a first insulating film, and wiring, including conductive film patterns and second insulating film patterns are formed on a substrate. Third insulating film patterns including a silicon-oxide-based material are formed on sidewalls of the wiring, and contact patterns and spacers on the sidewalls thereof for defining contact hole regions are formed on the wiring. The contact holes contact surfaces of the third insulating film patterns and pass through the first insulating film. Thus, the thickness of a second insulating film pattern used in the wiring can be minimized, thereby increasing a gap-fill margin between the wiring. A parasitic capacitance between the wiring can be reduced because silicon oxide spacers with a low dielectric constant are formed on sidewalls of the wiring.

In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps without damaging underlying features and little or no incidence of voids or weak spots is provided. A protective layer is deposited to protect underlying features in regions of the substrate having lower feature density so that unwanted material may be removed from regions of the substrate having higher feature density. This protective layer may deposits thicker on a low density feature than on a high density feature and may be deposited using a PECVD process or low sputter / deposition ratio HDP CVD process. This protective layer may also be a metallic oxide layer that is resistant to fluorine etching, such as zirconium oxide (ZrO2) or aluminum oxide (Al2O3).

A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.

Methods and apparatus for vapor deposition of an organic film are configured to vaporize an organic reactant at a first temperature, transport the vapor to a reaction chamber housing a substrate, and maintain the substrate at a lower temperature than the vaporization temperature. Alternating contact of the substrate with the organic reactant and a second reactant in a sequential deposition sequence can result in bottom-up filling of voids and trenches with organic film in a manner otherwise difficult to achieve. Deposition reactors conducive to depositing organic films are provided.

An improved system based on the Czochralski process for continuous growth of a single crystal ingot comprises a low aspect ratio, large diameter, and substantially flat crucible, including an optional weir surrounding the crystal. The low aspect ratio crucible substantially eliminates convection currents and reduces oxygen content in a finished single crystal silicon ingot. A separate level controlled silicon pre-melting chamber provides a continuous source of molten silicon to the growth crucible advantageously eliminating the need for vertical travel and a crucible raising system during the crystal pulling process. A plurality of heaters beneath the crucible establish corresponding thermal zones across the melt. Thermal output of the heaters is individually controlled for providing an optimal thermal distribution across the melt and at the crystal / melt interface for improved crystal growth. Multiple crystal pulling chambers are provided for continuous processing and high throughput.