71 results about "Common source line" patented technology

The present disclosure relates to a semiconductor device, a memory and a preparation method thereof, and an electronic device, and relates to the technical field of storage, so as to improve the performance and reliability of the semiconductor device and the memory. The semiconductor device comprises a first gate, a second gate, a third gate, a first semiconductor layer, a second semiconductor layer and a common source line. The first semiconductor layer is insulatively surrounded around the side wall of the first gate. The second gate is located on the side of the first semiconductor layer away from the first gate, and comprises a first part electrically connected with the first semiconductor layer, and a second part located on the side of the first part away from the first semiconductor layer and electrically connected with the first part. The second semiconductor layer is insulatively surrounded around the side wall of the second part and the bottom wall of the second part away from the first part. The third gate and the common source line are insulatively spaced around the side of the second semiconductor layer away from the side wall of the second part.

A semiconductor device includes a peripheral circuit structure including circuits, wiring layers, and via contacts, a plate common source line covering the peripheral circuit structure, an insulating plug passing through the plate common source line, a lateral insulating spacer between the peripheral circuit structure and the plate common source line, a memory stack structure including gate lines on the plate common source line, a through contact passing through at least one of the gate lines and the insulating plug, the through contact being connected to a first via contact of the via contacts, and a source line contact passing through the lateral insulating spacer, the source line contact being between a second via contact of the via contacts and the plate common source line, wherein a width of the first via contact is greater than a width of the insulating plug in a lateral direction.

A memory device is a three-dimensional NAND flash memory device with high-performance and high-capacity. The memory device includes a common source line, at least one bit line and at least one memory string. During an erasing operation, an erasing voltage is applied to at least one of the common source line and the at least one bit line. In a first period of the erasing operation, a voltage value of the erasing voltage is raised, and a voltage value of a word line voltage is a first voltage value. In a second period after the first period of the erasing operation, the voltage value of the erasing voltage is a target voltage value, and the voltage value of the word line voltage is raised from the first voltage value to a second voltage value.

A method of operating a non-volatile memory device, wherein the non-volatile memory device includes a cell string, wherein the cell string includes a plurality of cell transistors stacked in a direction perpendicular to a substrate in series between a bit line and a common source line, the method comprising: programming an erase control transistor in the plurality of cell transistors; and after the erase control transistor is programmed, applying an erase voltage to the common source line or the bit line and applying an erase control voltage to an erase control line connected to the erase control transistor, wherein the erase control voltage is less than the erase voltage and greater than a ground voltage, and wherein the erase control transistor is between a ground select transistor in the plurality of cell transistors and the common source line or between a string select transistor in the plurality of cell transistors and the bit line.

A semiconductor memory device is provided. The semiconductor memory device includes a common source line, a substrate on the common source line, a plurality of gate electrodes arranged on the substrate and spaced apart from each other in a first direction perpendicular to a top surface of the common source line, a plurality of insulating films arranged between the plurality of gate electrodes, a plurality of channel structures penetrating through the plurality of gate electrodes and the plurality of insulating films in the first direction, and a plurality of remaining sacrificial films arranged on the substrate and spaced apart from each other in the first direction, wherein the plurality of gate electrodes are disposed on opposite sides of the plurality of remaining sacrificial films.

A non-volatile memory device includes: N planes, each plane including a plurality of memory blocks; N discharge control circuits, each adjacent to the N planes and configured to connect a common source line of each of the N planes to a ground voltage terminal in response to each of the N discharge control signals; a plane selection circuit configured to select K planes among the N planes; and an operation control circuit configured to adjust the voltage level of the K discharge control signals according to the distance difference between the ground voltage terminal and each of the K discharge control circuits corresponding to the K planes.

The memory device an array of memory cells arranged in a word lines and a one common source line (CELSRC) driver. Control circuitry is configured to program the memory cells of a selected word line in a plurality of program loops. During the program loops, the control circuitry sets a voltage of the CELSRC driver to approximately zero Volts, applies a verify voltage to the selected word line, applies a pass voltage to unselected word lines, and applies a bit line voltage to a bit line that is coupled to a memory cell to be sensed. During at least one early program loop for a given data state, the control circuitry increases the bit line voltage or increases the pass voltage. The control circuitry is further configured to reduce the bit line voltage or the pass voltage for the verify operations in at least one subsequent program loop.

The invention relates to a semiconductor structure, a preparation method thereof and electronic equipment. The semiconductor structure comprises a bit line, a common source line and a storage unit. The bit lines and the common source lines are arranged along a first direction and extend along a second direction. The memory cell includes a first transistor and a second transistor. The first transistor is located between the bit line and the common source line in the first direction, and the first channel layer is connected with the bit line in the first direction. The second transistor comprises a second grid electrode, a second gate dielectric layer and a second channel layer. The second grid electrode is located between the first transistor and the common source line and comprises a storage grid, a dielectric layer and a control grid. The dielectric layer surrounds the control gate. The storage gate surrounds the dielectric layer and is connected with the first channel layer in the first direction. The second gate dielectric layer is located between the storage gate and the second channel layer in the second direction. The two sides of the second channel layer in the first direction are connected with the bit line and the common source line respectively. The storage density can be effectively improved.

The present disclosure provides a three-dimensional memory device, such as a three-dimensional AND flash memory device. The three-dimensional memory device includes a plurality of memory cell arrays, a plurality of bit line switches, and a plurality of source line switches. The memory cell arrays have a plurality of memory cell rows coupled to a plurality of source lines and a plurality of bit lines, respectively. The bit line switches and the source line switches are formed by a plurality of first transistors and a plurality of second transistors, respectively. The first transistors are coupled to a common bit line and a bit line. The second transistors are coupled to a common source line and a source line. The first transistors are P-type transistors or N-type transistors having a triple-well region base, and the second transistors are P-type transistors or N-type transistors having a triple-well region base.

An exemplary apparatus comprises: a first input circuit coupled between a common source line and a first circuit node, wherein the first input circuit is configured to be controlled by a first signal; a second input circuit coupled between the common source line and a second circuit node, wherein the second input circuit is configured to be controlled by a second signal; an amplifier circuit configured to amplify a potential difference between the first and second circuit nodes; and an auxiliary current path configured to allow current to flow from the common source line to the first and second circuit nodes independently of the first and second signals.

The invention provides a low power supply write-in erase type non-volatile memory, which belongs to the field of memories and comprises a common source line, a word line, a bit line, a memory array, a first electronic switch, a second electronic switch, a decoding device, a first storage capacitor, a second storage capacitor and a booster circuit. Each memory array is coupled to a common source line, a word line and four bit lines. The decoding device is coupled with a common source line, a word line and a bit line, and is coupled with a high voltage, a medium voltage, a low voltage and a grounding voltage. One end of the first storage capacitor is coupled with reference voltage, and the other end is coupled with the decoding device through the first electronic switch. One end of the second storage capacitor is coupled with the reference voltage, and the other end is coupled with the decoding device through the second electronic switch. The boost circuit is coupled to the first storage capacitor. The boost circuit can charge the first storage capacitor to complete a programming action or an erasing action. The power consumption can be reduced, and the stability of stored data can be improved.

A nonvolatile memory device includes N planes each comprising a plurality of memory blocks, N discharge control circuits adjacent to the N planes, respectively, and configured to connect each common source line of the N planes and a ground voltage terminal in response to each one of N discharge control signals, a plane selection circuit configured to select K planes of the N planes, and an operation control circuit configured to adjust voltage levels of K discharge control signals according to a distance difference between the ground voltage terminal and each of K discharge control circuits corresponding to the K planes, among the N discharge control circuits.

A nonvolatile memory device includes a plurality of metal lines extending in a first direction and stacked in a second direction crossing the first direction, a plurality of cell structures passing through the plurality of metal lines and extending in the second direction, a plurality of extension regions, a plate common source line contact connected with a common source line, extending in the first direction, and formed in least two of the plurality of extension regions that are not formed with the plurality of cell structures, and input / output metal contacts connected with an external connection pad, extending in the first direction, and formed with at least two of the plurality of extension regions that are not formed with the plate common source line contact.

Embodiments of the present disclosure relate to a memory device and an operating method thereof. A memory device includes a common source line, a memory cell array, a bit line, and a conductive layer. The common source line is formed on a substrate. The memory cell array is formed on the common source line. The bit line is connected to the memory cell array. The conductive layer is formed over the bit line. In an erase operation, the memory device increases a voltage of the bit line to an erase voltage by capacitive coupling by increasing a voltage applied to the conductive layer.

To provide a semiconductor device with improved reliability, and a data storage system including the same.SOLUTION: According to example embodiments, a semiconductor device and a data storage system including the same may include a channel structure including a plurality of channel holes and a channel pattern connecting the plurality of channel holes using a stopper. Accordingly, embodiments of the inventive concept provide a semiconductor device and a data storage system including the same having improved reliability by minimizing and / or improving contact failure due to mis-alignment with a conductive pattern functioning as a common source line in contact with a channel structure.SELECTED DRAWING: Figure 3

A memory device capable of reducing peak current includes a plurality of strings of memory cells each including a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells. A method for operating a memory device includes pre-charging channel regions of the plurality of strings of memory cells through the common source line and setting a bit line voltage applied to the bit line while the channel regions of the plurality of strings of memory cells are being pre-charged after starting pre-charging the channel regions of the plurality of strings of memory cells.

A MRAM circuit is provided in the present invention, wherein each memory cell has three transistors, including a first transistor, a third transistor and a second transistor connected in order and series connection, a first node is connected between the first transistor and the third transistor, a second node is connected between the second transistor and the third transistor, and a common source line is connected with one terminal of the first transistor and the second transistor. A first MTJ set includes at least two MTJs in series connection and with one terminal connected to the first node, and a second MTJ set includes at least two MTJs in series connection and with one terminal connected to the second node.

Semiconductor devices and methods of operating semiconductor devices are provided. The semiconductor device includes a source layer, a plurality of channel structures, a plurality of gate electrodes, and a common source line. At least one gate electrode of the plurality of gate electrodes provides a GIDL line. During an erase operation, an erase voltage applied to the common source line reaches a target voltage, and after the erase voltage reaches the target voltage, a step increment voltage is added to the erase voltage such that a voltage level of the erase voltage is higher than a voltage level of the target voltage. After the step increment voltage has been added for a desired period of time, during a remaining operation of the erase operation, the voltage level of the erase voltage is decreased to the voltage level of the target voltage.

Disclosed is a nonvolatile memory device including a memory cell array including memory cells, bit lines and word lines connected with the memory cells, a common source line connected with the memory cells, a control logic circuit including a common source line noise control logic circuit and configured to generate voltages including a first voltage and a second voltage, a voltage selector configured to receive the voltages and configured to select at least one of the voltages, and a common source line driver configured to receive the at least one selected voltage and configured to control a voltage of the common source line, and the common source line noise control logic circuit is configured to control the voltage selector based on program information so as to select the at least one of the voltages.

An example memory device includes a substrate; and a first cell string and a second cell string on the substrate and between the first bit line and the common source line. The first cell string includes a first string selection transistor connected to the first string selection line, and first and third ground selection transistors connected to the first and second ground selection lines, respectively. The second cell string includes a second string selection transistor connected to the second string selection line, and second and fourth ground selection transistors connected to the first and second ground selection lines, respectively. When the first cell string is a selected cell string, in the second cell string, the second ground selection transistor and the fourth ground selection transistor are turned off, and at least one ground selection transistor between the second ground selection transistor and the fourth ground selection transistor is turned on.

A memory device includes a memory cell array having a plurality of memory blocks therein, including a target memory block. A voltage generator is provided, which is configured to generate an erase voltage and row line voltages, which are provided to the target memory block upon which an erase operation is to be performed. Control logic is provided, which is configured to control the memory cell array and the voltage generator. In addition, during operation, the erase voltage is provided to at least one of a bitline or a common source line associated with the target memory block, and a gate line of a transistor provided with the erase voltage is precharged before the erase voltage is provided to the at least one of the bitline or the common source line of the target memory block.

A semiconductor memory device and a method of operating the semiconductor memory device include an array of memory cells, a peripheral circuit, and control logic. The array of memory cells includes a plurality of memory blocks coupled to a common source line. The peripheral circuit performs a program operation on a memory block selected from among the memory blocks. The control logic controls the program operation of the peripheral circuit. The memory blocks are respectively coupled to corresponding source select lines. The program operation includes a plurality of program loops, each program loop including a pass precharge operation. During the pass precharge operation, the control logic controls the peripheral circuit such that: the common source line is floated, and a voltage of a source select line coupled to an unselected memory block among the memory blocks is increased.

A nonvolatile memory device includes first to n-th cell strings connected in parallel between a bit line and a common source line. Each of the first to n-th cell strings includes: a respective one of first to n-th ground selection transistors connected to first to n-th ground selection lines, respectively; and first to m-th string selection transistors connected to the first to m-th string selection lines, respectively. On the basis that the first cell string is a selected cell string: first to m-th string selection transistors of the first cell string are turned on, and at least one string selection transistor of the first to m-th string selection transistors of each of the second to n-th cell strings is turned off, where m and n are natural numbers, and n is a natural number. And m is less than or equal to n.

A MRAM circuit is provided in the present invention, wherein each memory cell has three transistors, including a first transistor, a third transistor and a second transistor connected in order and series connection, a first node is connected between the first transistor and the third transistor, a second node is connected between the second transistor and the third transistor, and a common source line is connected with one terminal of the first transistor and the second transistor. A first MTJ set includes at least two MTJs in series connection and with one terminal connected to the first node, and a second MTJ set includes at least two MTJs in series connection and with one terminal connected to the second node.

An example non-volatile memory device includes a memory cell array including a plurality of memory blocks, a voltage generator configured to generate an erase voltage provided to at least one of a bit line or a common source line connected to a selected block targeted by an erase operation among the plurality of memory blocks, and a first negative bias voltage provided to a gate induced drain leakage (GIDL) line connected to the selected block, and a control logic circuit configured to control the voltage generator, wherein the erase voltage is increased and maintained constant during an erase operation on the selected block, and wherein a GIDL voltage provided to the GIDL line connected to the selected block is maintained at the first negative bias voltage and increased in response to the erase voltage increasing.

A memory device includes a word line area that is between a bit line and a common source line. The word line area includes a plurality of stacks. A first area includes first stacks with a first resistance value in the word line area, a second area includes second stacks with a second resistance value in the word line area, wherein the second resistance value is different from the first resistance value, a third area includes third stacks with a third resistance value that different from the first resistance value, and a processor is configured to control a recovery sequence of the first area, the second area, and the third area.

There is provided a method of operating a nonvolatile memory device that includes a plurality of memory blocks, each of the plurality of memory blocks including a plurality of cell strings where each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells, and a ground selection transistor which are connected in series and arranged in a vertical direction between each of a plurality of bit-lines and a common source line on and / or in a substrate, the method comprising: receiving an erase command and a block address designating a target memory block among the plurality of memory blocks; sensing an operating temperature of the nonvolatile memory device; and adjusting an erase execution time interval of each of word-lines of the target memory block, respectively, based on the sensed operating temperature, wherein the vertical direction is perpendicular to an upper surface of the substrate.

A non-volatile memory device includes a substrate; an insulating layer on the substrate; a bit line isolation layer on the insulating layer; a common source line conductive layer on the bit line isolation layer; a ferroelectric memory cell on the bit line isolation layer; a bit line connected to a top of the ferroelectric memory cell; and a common source line connected to the common source line conductive layer and electrically connected to the ferroelectric memory cell, wherein the ferroelectric memory cell includes a ferroelectric layer, a channel layer, a first conductive filler connected to the ferroelectric layer and the channel layer and extending in a vertical direction, and a second conductive filler connected to the ferroelectric layer and the channel layer and extending in the vertical direction, the first conductive filler is connected to the bit line, and the second conductive filler is connected to the common source line.

A nonvolatile memory device includes a first cell string to an n-th cell string connected in parallel between a bit line and a common source line. Each of the first to n-th cell strings includes: a corresponding one of a first ground selection transistor to an n-th ground selection transistor respectively connected to a first ground selection line to an n-th ground selection line; and a first string selection transistor to an m-th string selection transistor respectively connected to a first string selection line to an m-th string selection line. Based on the first cell string being a selected cell string: the first to m-th string selection transistors of the first cell string are turned on, and at least one of the first to m-th string selection transistors of each of the second to n-th cell strings is turned off, where m and n are natural numbers, and m is less than or equal to n.

A three-dimensional semiconductor device includes a plate common source line, first and second word lines spaced apart from each other to at least partially define a vertical space therebetween, a channel pattern in the vertical space, a ferroelectric layer including a first portion between the channel pattern and the first word line, a second portion between the channel pattern and the second word line, and a third portion contacting the plate common source line, a bit line in the vertical space to contact the channel pattern and having a first width in a first horizontal direction, and a source line spaced apart from the bit line in the vertical space to contact the channel pattern, having a second width greater than the first width in the first horizontal direction, and having a source line contact portion inside the plate common source line.