40 results about "Common source line" patented technology

A semiconductor device includes a peripheral circuit structure including circuits, wiring layers, and via contacts, a plate common source line covering the peripheral circuit structure, an insulating plug passing through the plate common source line, a lateral insulating spacer between the peripheral circuit structure and the plate common source line, a memory stack structure including gate lines on the plate common source line, a through contact passing through at least one of the gate lines and the insulating plug, the through contact being connected to a first via contact of the via contacts, and a source line contact passing through the lateral insulating spacer, the source line contact being between a second via contact of the via contacts and the plate common source line, wherein a width of the first via contact is greater than a width of the insulating plug in a lateral direction.

A memory device is a three-dimensional NAND flash memory device with high-performance and high-capacity. The memory device includes a common source line, at least one bit line and at least one memory string. During an erasing operation, an erasing voltage is applied to at least one of the common source line and the at least one bit line. In a first period of the erasing operation, a voltage value of the erasing voltage is raised, and a voltage value of a word line voltage is a first voltage value. In a second period after the first period of the erasing operation, the voltage value of the erasing voltage is a target voltage value, and the voltage value of the word line voltage is raised from the first voltage value to a second voltage value.

A method of operating a non-volatile memory device, wherein the non-volatile memory device includes a cell string, wherein the cell string includes a plurality of cell transistors stacked in a direction perpendicular to a substrate in series between a bit line and a common source line, the method comprising: programming an erase control transistor in the plurality of cell transistors; and after the erase control transistor is programmed, applying an erase voltage to the common source line or the bit line and applying an erase control voltage to an erase control line connected to the erase control transistor, wherein the erase control voltage is less than the erase voltage and greater than a ground voltage, and wherein the erase control transistor is between a ground select transistor in the plurality of cell transistors and the common source line or between a string select transistor in the plurality of cell transistors and the bit line.

A non-volatile memory device includes: N planes, each plane including a plurality of memory blocks; N discharge control circuits, each adjacent to the N planes and configured to connect a common source line of each of the N planes to a ground voltage terminal in response to each of the N discharge control signals; a plane selection circuit configured to select K planes among the N planes; and an operation control circuit configured to adjust the voltage level of the K discharge control signals according to the distance difference between the ground voltage terminal and each of the K discharge control circuits corresponding to the K planes.

The present disclosure provides a three-dimensional memory device, such as a three-dimensional AND flash memory device. The three-dimensional memory device includes a plurality of memory cell arrays, a plurality of bit line switches, and a plurality of source line switches. The memory cell arrays have a plurality of memory cell rows coupled to a plurality of source lines and a plurality of bit lines, respectively. The bit line switches and the source line switches are formed by a plurality of first transistors and a plurality of second transistors, respectively. The first transistors are coupled to a common bit line and a bit line. The second transistors are coupled to a common source line and a source line. The first transistors are P-type transistors or N-type transistors having a triple-well region base, and the second transistors are P-type transistors or N-type transistors having a triple-well region base.

An exemplary apparatus comprises: a first input circuit coupled between a common source line and a first circuit node, wherein the first input circuit is configured to be controlled by a first signal; a second input circuit coupled between the common source line and a second circuit node, wherein the second input circuit is configured to be controlled by a second signal; an amplifier circuit configured to amplify a potential difference between the first and second circuit nodes; and an auxiliary current path configured to allow current to flow from the common source line to the first and second circuit nodes independently of the first and second signals.

The invention provides a low power supply write-in erase type non-volatile memory, which belongs to the field of memories and comprises a common source line, a word line, a bit line, a memory array, a first electronic switch, a second electronic switch, a decoding device, a first storage capacitor, a second storage capacitor and a booster circuit. Each memory array is coupled to a common source line, a word line and four bit lines. The decoding device is coupled with a common source line, a word line and a bit line, and is coupled with a high voltage, a medium voltage, a low voltage and a grounding voltage. One end of the first storage capacitor is coupled with reference voltage, and the other end is coupled with the decoding device through the first electronic switch. One end of the second storage capacitor is coupled with the reference voltage, and the other end is coupled with the decoding device through the second electronic switch. The boost circuit is coupled to the first storage capacitor. The boost circuit can charge the first storage capacitor to complete a programming action or an erasing action. The power consumption can be reduced, and the stability of stored data can be improved.

A nonvolatile memory device includes N planes each comprising a plurality of memory blocks, N discharge control circuits adjacent to the N planes, respectively, and configured to connect each common source line of the N planes and a ground voltage terminal in response to each one of N discharge control signals, a plane selection circuit configured to select K planes of the N planes, and an operation control circuit configured to adjust voltage levels of K discharge control signals according to a distance difference between the ground voltage terminal and each of K discharge control circuits corresponding to the K planes, among the N discharge control circuits.

Embodiments of the present disclosure relate to a memory device and an operating method thereof. A memory device includes a common source line, a memory cell array, a bit line, and a conductive layer. The common source line is formed on a substrate. The memory cell array is formed on the common source line. The bit line is connected to the memory cell array. The conductive layer is formed over the bit line. In an erase operation, the memory device increases a voltage of the bit line to an erase voltage by capacitive coupling by increasing a voltage applied to the conductive layer.

To provide a semiconductor device with improved reliability, and a data storage system including the same.SOLUTION: According to example embodiments, a semiconductor device and a data storage system including the same may include a channel structure including a plurality of channel holes and a channel pattern connecting the plurality of channel holes using a stopper. Accordingly, embodiments of the inventive concept provide a semiconductor device and a data storage system including the same having improved reliability by minimizing and / or improving contact failure due to mis-alignment with a conductive pattern functioning as a common source line in contact with a channel structure.SELECTED DRAWING: Figure 3

A memory device capable of reducing peak current includes a plurality of strings of memory cells each including a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells. A method for operating a memory device includes pre-charging channel regions of the plurality of strings of memory cells through the common source line and setting a bit line voltage applied to the bit line while the channel regions of the plurality of strings of memory cells are being pre-charged after starting pre-charging the channel regions of the plurality of strings of memory cells.

Semiconductor devices and methods of operating semiconductor devices are provided. The semiconductor device includes a source layer, a plurality of channel structures, a plurality of gate electrodes, and a common source line. At least one gate electrode of the plurality of gate electrodes provides a GIDL line. During an erase operation, an erase voltage applied to the common source line reaches a target voltage, and after the erase voltage reaches the target voltage, a step increment voltage is added to the erase voltage such that a voltage level of the erase voltage is higher than a voltage level of the target voltage. After the step increment voltage has been added for a desired period of time, during a remaining operation of the erase operation, the voltage level of the erase voltage is decreased to the voltage level of the target voltage.

A memory device includes a memory cell array having a plurality of memory blocks therein, including a target memory block. A voltage generator is provided, which is configured to generate an erase voltage and row line voltages, which are provided to the target memory block upon which an erase operation is to be performed. Control logic is provided, which is configured to control the memory cell array and the voltage generator. In addition, during operation, the erase voltage is provided to at least one of a bitline or a common source line associated with the target memory block, and a gate line of a transistor provided with the erase voltage is precharged before the erase voltage is provided to the at least one of the bitline or the common source line of the target memory block.

A semiconductor memory device and a method of operating the semiconductor memory device include an array of memory cells, a peripheral circuit, and control logic. The array of memory cells includes a plurality of memory blocks coupled to a common source line. The peripheral circuit performs a program operation on a memory block selected from among the memory blocks. The control logic controls the program operation of the peripheral circuit. The memory blocks are respectively coupled to corresponding source select lines. The program operation includes a plurality of program loops, each program loop including a pass precharge operation. During the pass precharge operation, the control logic controls the peripheral circuit such that: the common source line is floated, and a voltage of a source select line coupled to an unselected memory block among the memory blocks is increased.

A nonvolatile memory device includes first to n-th cell strings connected in parallel between a bit line and a common source line. Each of the first to n-th cell strings includes: a respective one of first to n-th ground selection transistors connected to first to n-th ground selection lines, respectively; and first to m-th string selection transistors connected to the first to m-th string selection lines, respectively. On the basis that the first cell string is a selected cell string: first to m-th string selection transistors of the first cell string are turned on, and at least one string selection transistor of the first to m-th string selection transistors of each of the second to n-th cell strings is turned off, where m and n are natural numbers, and n is a natural number. And m is less than or equal to n.

A MRAM circuit is provided in the present invention, wherein each memory cell has three transistors, including a first transistor, a third transistor and a second transistor connected in order and series connection, a first node is connected between the first transistor and the third transistor, a second node is connected between the second transistor and the third transistor, and a common source line is connected with one terminal of the first transistor and the second transistor. A first MTJ set includes at least two MTJs in series connection and with one terminal connected to the first node, and a second MTJ set includes at least two MTJs in series connection and with one terminal connected to the second node.

An example non-volatile memory device includes a memory cell array including a plurality of memory blocks, a voltage generator configured to generate an erase voltage provided to at least one of a bit line or a common source line connected to a selected block targeted by an erase operation among the plurality of memory blocks, and a first negative bias voltage provided to a gate induced drain leakage (GIDL) line connected to the selected block, and a control logic circuit configured to control the voltage generator, wherein the erase voltage is increased and maintained constant during an erase operation on the selected block, and wherein a GIDL voltage provided to the GIDL line connected to the selected block is maintained at the first negative bias voltage and increased in response to the erase voltage increasing.

A non-volatile memory device includes a substrate; an insulating layer on the substrate; a bit line isolation layer on the insulating layer; a common source line conductive layer on the bit line isolation layer; a ferroelectric memory cell on the bit line isolation layer; a bit line connected to a top of the ferroelectric memory cell; and a common source line connected to the common source line conductive layer and electrically connected to the ferroelectric memory cell, wherein the ferroelectric memory cell includes a ferroelectric layer, a channel layer, a first conductive filler connected to the ferroelectric layer and the channel layer and extending in a vertical direction, and a second conductive filler connected to the ferroelectric layer and the channel layer and extending in the vertical direction, the first conductive filler is connected to the bit line, and the second conductive filler is connected to the common source line.

A nonvolatile memory device includes a first cell string to an n-th cell string connected in parallel between a bit line and a common source line. Each of the first to n-th cell strings includes: a corresponding one of a first ground selection transistor to an n-th ground selection transistor respectively connected to a first ground selection line to an n-th ground selection line; and a first string selection transistor to an m-th string selection transistor respectively connected to a first string selection line to an m-th string selection line. Based on the first cell string being a selected cell string: the first to m-th string selection transistors of the first cell string are turned on, and at least one of the first to m-th string selection transistors of each of the second to n-th cell strings is turned off, where m and n are natural numbers, and m is less than or equal to n.

A memory device is provided, the memory device comprising: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of word lines extending along a first direction and stacked along a second direction substantially perpendicular to the first direction; and a plurality of transfer transistors disposed in the first semiconductor layer, wherein a first transfer transistor of the plurality of transfer transistors is disposed between a first signal line of the plurality of signal lines and a first word line of the plurality of word lines, and wherein the plurality of signal lines and a common source line are arranged at the same horizontal level.

A memory and reading, writing and erasing methods thereof. The memory includes: H memory planes arranged in parallel along a first direction, where each memory plane extends in a second direction, and includes M columns of memory strings; each column of memory string extends in a third direction; the first direction, the second direction and the third direction are all different, and H and M are integers greater than zero; each column of memory string includes N rows of memristive memory cells. The memory is also provided with word lines, gating transistors, gating lines, bit lines and a common source line, where memristive memory cells in last rows of all memory strings are connected to the common source line, and the common source line is connected to a reference potential through a reference resistor. Use performance of the memory can be improved.

The present disclosure relates to a memory device including a plurality of memory cells arranged in an array with word and bit lines. Each cell includes a memory element made of a phase-change material and two transistors connected by their first conduction nodes, themselves connected to a first terminal of the element. The elements of a bit line are connected by their second terminals. Both transistors of a word line are connected by their gates. Each cell is connected to two source lines, respectively, connected to the two second nodes of the transistors. The cells of a word line are connected to the two source lines and the cells of two consecutive word lines being connected to a common source line. Each transistor is disposed in and on a pair of two fins disposed in a semiconductor substrate.

A memory device includes a substrate and first to fourth tiers. The first tier is located on the substrate and includes first transistors and second transistors. The first transistors includes multiple groups. The second tier includes a composite stack structure. The third tier includes local bit lines and local source lines. Each of the local bit lines is connected to a first terminal of one of the first transistors. Each of the local source lines is connected to a first terminal of one of the second transistors. The fourth tier includes multiple global bit lines and a common source line. Each of the global bit lines is connected to second terminals of the first transistors in one of the groups. The common source line is connected to a second terminal of each of the second transistors. Embodiments of the present disclosure may be applied to a 3D AND flash memory.

A non-volatile memory device including a peripheral circuit structure and a cell array structure may be provided. The cell array structure may include a common source line layer, a bit line, a bit line wiring insulation layer, a cell stack provided between the common source line layer and the bit line and including a plurality of gate electrodes and a plurality of interlayer insulation layers, and a plurality of channel structures extending through the cell stack into the bit line wiring insulation layer. Each of the plurality of channel structures includes a channel layer electrically connected to the common source line layer, a bit line pad electrically connecting the channel layer to the bit line and being adjacent to one end of the channel layer facing the bit line, and a gate insulation layer covering the channel layer and the bit line pad.

The semiconductor device includes a substrate, a stack disposed on the substrate, a first common source line and a second common source line disposed in the stack and connected to the substrate. The stack includes insulating layers and conductive layers alternately arranged. The first common source line and the second common source line are extended along a first direction and are arranged in a second direction that is perpendicular to the first direction. The first common source line includes a first segment and a second segment spaced apart by a first common source line cut. The second common source line includes a third segment and a fourth segment spaced apart by a second common source line cut. The first common source line cut is shifted relative to the second common source line cut in the first direction. A method of forming the semiconductor device is also disclosed.

The present disclosure provides a memory device and an operating method thereof. The memory device includes a P-type well region, a common source line, a ground select line, at least one dummy ground select line, a plurality of word lines, at least one dummy string select line, a string select line, at least one bit line, and at least one memory string. The word line is disposed between the dummy ground select line and the dummy string select line, and a plurality of memory cells of the memory string are connected to the word line. The operating method includes the following steps: for a selected word line, applying a read voltage to the selected word line, and applying a pass voltage to the unselected other word lines and the ground select line. Before the read operation ends, the voltage of the string select line and the dummy string select line is first lowered in advance, and then the voltage of the bit line is raised.

A memory device, comprising: a memory cell array including a plurality of memory cell strings, and coupled between a plurality of bit lines and a plurality of word lines, the bit lines commonly coupled to a common source line, and a control portion suitable for: precharging the bit lines to a first level during a read operation for selected memory cells coupled to a selected word line of the word lines, and precharging the bit lines to a second level during a verify operation of a program operation for the selected memory cells, wherein the second level is lower than the first level by a set level.

The present invention relates to a three-dimension flash memory to which an efficient word line connection structure is applied, and a method for manufacturing same, wherein a plurality of word lines are connected to a low decoder respectively through contacts of the plurality of word lines, a plurality of connection wires, and plug vias of the plurality of word lines. The row decoder and a column decoder are arranged to divide a plurality of peripheral circuit blocks such that the plurality of peripheral circuit blocks are symmetrical to each other in the plane of the three-dimensional flash memory. The three-dimension flash memory is configured in a buried type in which a common source line is buried in a substrate, in order to improve integration density.

A memory device includes a common source line, a first cell region that controls a connection between the common source line and string selection lines, and a dummy cell region including one or more dummy word lines to which dummy elements are connected. The dummy cell region is disposed in the first cell region or between the common source line and the first cell region.

A memory structure includes storage transistors organized as horizontal NOR memory strings where the storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent a semiconductor channel. In some embodiments, the semiconductor channel is formed by an oxide semiconductor material and the ferroelectric storage transistors are junctionless transistors with no p / n junction in the channel. In some embodiments, the ferroelectric storage transistors in each NOR memory string share a first conductive layer as a common source line and a second conductive layer as a common bit line, the first and second conductive layers being in electrical contact with the semiconductor channel. The ferroelectric storage transistors in a multiplicity of NOR memory strings are arranged to form semi-autonomous three-dimensional memory arrays (tiles) with each tile individually addressed and controlled by circuitry in the semiconductor substrate underneath each tile in cooperation with a memory controller.