100 results about "Common source line" patented technology

A semiconductor memory device and an electronic system including the same are provided. The semiconductor memory device includes a first cell array structure including a plurality of first cell strings, a plurality of first bonding pads, a first bit line, a first common source line, and a plurality of first word lines; and a second cell array structure including a plurality of second cell strings, a plurality of second bonding pads, a second bit line, a second common source line, and a plurality of second word lines, in which the plurality of first bonding pads are bonded to the plurality of second bonding pads, in which the plurality of first word lines are electrically connected to the plurality of second word lines, in which the plurality of first word lines are electrically connected to the plurality of second word lines. The first bit line is spaced apart from the second bit line, and wherein the first common source line is electrically separated from the second common source line.

The present disclosure provides a vertical memory device and an operation method thereof. An operation method of a memory device is provided, the memory device including a plurality of strings on a substrate, where the plurality of strings include a main string connected to a bit line and a dummy string spaced apart from the bit line, the operation method including: pre-programming the dummy string; and erasing the main string and the dummy string, where pre-programming includes: applying a pre-programming voltage to a word line connected to the dummy string; applying a pass voltage to a ground selection line of a ground selection transistor connected to the dummy string; and applying a common source line voltage to a common source line connected to the dummy string.

A vertical-type nonvolatile memory device is provided in which differences between the sizes of channel holes in which channel structures are formed are reduced. The vertical-type nonvolatile memory device includes a substrate having channel hole recess regions in a surface thereof. Channel structures vertically protrude from the surface of the substrate on ones of the channel hole recess regions, and memory cell stacks including insulating and conductive layers are alternately stacked along sidewalls of the channel structures. A common source line extends along the surface of the substrate on other ones of the channel hole recess regions in a word line recess region, which separates adjacent memory cell stacks. Related fabrication methods are also discussed.

The present disclosure relates to a semiconductor device, a memory and a preparation method thereof, and an electronic device, and relates to the technical field of storage, so as to improve the performance and reliability of the semiconductor device and the memory. The semiconductor device comprises a first gate, a second gate, a third gate, a first semiconductor layer, a second semiconductor layer and a common source line. The first semiconductor layer is insulatively surrounded around the side wall of the first gate. The second gate is located on the side of the first semiconductor layer away from the first gate, and comprises a first part electrically connected with the first semiconductor layer, and a second part located on the side of the first part away from the first semiconductor layer and electrically connected with the first part. The second semiconductor layer is insulatively surrounded around the side wall of the second part and the bottom wall of the second part away from the first part. The third gate and the common source line are insulatively spaced around the side of the second semiconductor layer away from the side wall of the second part.

A semiconductor memory device includes a memory block including plurality of string groups, a peripheral circuit, and control logic. The peripheral circuit performs a program operation on source select transistors included in the memory block. The control logic controls the program operation of the peripheral circuit. Each of the plurality of string groups includes at least one cell string, and the at least one cell string includes inner source select transistors located adjacent to memory cells and outer source select transistors located adjacent to a common source line. The control logic controls the peripheral circuit to perform program operations on the outer source select transistors and the inner source select transistors by an ISPP method. The control logic controls the peripheral circuit to perform a verify operation by dividing the inner source select transistors into at least two groups during the program operation of the inner source select transistors.

A semiconductor device includes a peripheral circuit structure including circuits, wiring layers, and via contacts, a plate common source line covering the peripheral circuit structure, an insulating plug passing through the plate common source line, a lateral insulating spacer between the peripheral circuit structure and the plate common source line, a memory stack structure including gate lines on the plate common source line, a through contact passing through at least one of the gate lines and the insulating plug, the through contact being connected to a first via contact of the via contacts, and a source line contact passing through the lateral insulating spacer, the source line contact being between a second via contact of the via contacts and the plate common source line, wherein a width of the first via contact is greater than a width of the insulating plug in a lateral direction.

A memory device is a three-dimensional NAND flash memory device with high-performance and high-capacity. The memory device includes a common source line, at least one bit line and at least one memory string. During an erasing operation, an erasing voltage is applied to at least one of the common source line and the at least one bit line. In a first period of the erasing operation, a voltage value of the erasing voltage is raised, and a voltage value of a word line voltage is a first voltage value. In a second period after the first period of the erasing operation, the voltage value of the erasing voltage is a target voltage value, and the voltage value of the word line voltage is raised from the first voltage value to a second voltage value.

A method of operating a non-volatile memory device, wherein the non-volatile memory device includes a cell string, wherein the cell string includes a plurality of cell transistors stacked in a direction perpendicular to a substrate in series between a bit line and a common source line, the method comprising: programming an erase control transistor in the plurality of cell transistors; and after the erase control transistor is programmed, applying an erase voltage to the common source line or the bit line and applying an erase control voltage to an erase control line connected to the erase control transistor, wherein the erase control voltage is less than the erase voltage and greater than a ground voltage, and wherein the erase control transistor is between a ground select transistor in the plurality of cell transistors and the common source line or between a string select transistor in the plurality of cell transistors and the bit line.

A semiconductor memory device is provided. The semiconductor memory device includes a common source line, a substrate on the common source line, a plurality of gate electrodes arranged on the substrate and spaced apart from each other in a first direction perpendicular to a top surface of the common source line, a plurality of insulating films arranged between the plurality of gate electrodes, a plurality of channel structures penetrating through the plurality of gate electrodes and the plurality of insulating films in the first direction, and a plurality of remaining sacrificial films arranged on the substrate and spaced apart from each other in the first direction, wherein the plurality of gate electrodes are disposed on opposite sides of the plurality of remaining sacrificial films.

A non-volatile memory device includes: N planes, each plane including a plurality of memory blocks; N discharge control circuits, each adjacent to the N planes and configured to connect a common source line of each of the N planes to a ground voltage terminal in response to each of the N discharge control signals; a plane selection circuit configured to select K planes among the N planes; and an operation control circuit configured to adjust the voltage level of the K discharge control signals according to the distance difference between the ground voltage terminal and each of the K discharge control circuits corresponding to the K planes.

Systems, methods, circuits, and apparatus for managing multi-block operations in memory devices are provided. In one aspect, a memory device includes a memory cell array including at least two blocks, a bit line coupled to a string of memory cells in each of the at least two blocks respectively, a common source line (CSL) coupled to strings coupled to the bit line in the at least two blocks, and a circuitry configured to perform a multi-block operation in the memory cell array by at least one of: forming a first current path from the bit line through the strings to the CSL coupled to a ground to discharge a capacitor associated with the bit line that is pre-charged, or forming a second current path from the CSL coupled to a supply voltage through the strings to the bit line to charge the capacitor that is pre-discharged.

A memory device includes a first cell string that is provided between a first bit line and a common source line and a second cell string that is provided between the first bit line and the common source line. At least two first ground selection transistors among first ground selection transistors of the first cell string have a first program state and remaining first ground selection transistors have an erase state. At least two second ground selection transistors among the second ground selection transistors of the second cell string have the first program state and remaining second ground selection transistors have the erase state.

The memory device an array of memory cells arranged in a word lines and a one common source line (CELSRC) driver. Control circuitry is configured to program the memory cells of a selected word line in a plurality of program loops. During the program loops, the control circuitry sets a voltage of the CELSRC driver to approximately zero Volts, applies a verify voltage to the selected word line, applies a pass voltage to unselected word lines, and applies a bit line voltage to a bit line that is coupled to a memory cell to be sensed. During at least one early program loop for a given data state, the control circuitry increases the bit line voltage or increases the pass voltage. The control circuitry is further configured to reduce the bit line voltage or the pass voltage for the verify operations in at least one subsequent program loop.

The invention relates to a semiconductor structure, a preparation method thereof and electronic equipment. The semiconductor structure comprises a bit line, a common source line and a storage unit. The bit lines and the common source lines are arranged along a first direction and extend along a second direction. The memory cell includes a first transistor and a second transistor. The first transistor is located between the bit line and the common source line in the first direction, and the first channel layer is connected with the bit line in the first direction. The second transistor comprises a second grid electrode, a second gate dielectric layer and a second channel layer. The second grid electrode is located between the first transistor and the common source line and comprises a storage grid, a dielectric layer and a control grid. The dielectric layer surrounds the control gate. The storage gate surrounds the dielectric layer and is connected with the first channel layer in the first direction. The second gate dielectric layer is located between the storage gate and the second channel layer in the second direction. The two sides of the second channel layer in the first direction are connected with the bit line and the common source line respectively. The storage density can be effectively improved.

The present disclosure provides a three-dimensional memory device, such as a three-dimensional AND flash memory device. The three-dimensional memory device includes a plurality of memory cell arrays, a plurality of bit line switches, and a plurality of source line switches. The memory cell arrays have a plurality of memory cell rows coupled to a plurality of source lines and a plurality of bit lines, respectively. The bit line switches and the source line switches are formed by a plurality of first transistors and a plurality of second transistors, respectively. The first transistors are coupled to a common bit line and a bit line. The second transistors are coupled to a common source line and a source line. The first transistors are P-type transistors or N-type transistors having a triple-well region base, and the second transistors are P-type transistors or N-type transistors having a triple-well region base.

An exemplary apparatus comprises: a first input circuit coupled between a common source line and a first circuit node, wherein the first input circuit is configured to be controlled by a first signal; a second input circuit coupled between the common source line and a second circuit node, wherein the second input circuit is configured to be controlled by a second signal; an amplifier circuit configured to amplify a potential difference between the first and second circuit nodes; and an auxiliary current path configured to allow current to flow from the common source line to the first and second circuit nodes independently of the first and second signals.

The invention provides a low power supply write-in erase type non-volatile memory, which belongs to the field of memories and comprises a common source line, a word line, a bit line, a memory array, a first electronic switch, a second electronic switch, a decoding device, a first storage capacitor, a second storage capacitor and a booster circuit. Each memory array is coupled to a common source line, a word line and four bit lines. The decoding device is coupled with a common source line, a word line and a bit line, and is coupled with a high voltage, a medium voltage, a low voltage and a grounding voltage. One end of the first storage capacitor is coupled with reference voltage, and the other end is coupled with the decoding device through the first electronic switch. One end of the second storage capacitor is coupled with the reference voltage, and the other end is coupled with the decoding device through the second electronic switch. The boost circuit is coupled to the first storage capacitor. The boost circuit can charge the first storage capacitor to complete a programming action or an erasing action. The power consumption can be reduced, and the stability of stored data can be improved.

A nonvolatile memory device includes N planes each comprising a plurality of memory blocks, N discharge control circuits adjacent to the N planes, respectively, and configured to connect each common source line of the N planes and a ground voltage terminal in response to each one of N discharge control signals, a plane selection circuit configured to select K planes of the N planes, and an operation control circuit configured to adjust voltage levels of K discharge control signals according to a distance difference between the ground voltage terminal and each of K discharge control circuits corresponding to the K planes, among the N discharge control circuits.

A nonvolatile memory device includes a plurality of metal lines extending in a first direction and stacked in a second direction crossing the first direction, a plurality of cell structures passing through the plurality of metal lines and extending in the second direction, a plurality of extension regions, a plate common source line contact connected with a common source line, extending in the first direction, and formed in least two of the plurality of extension regions that are not formed with the plurality of cell structures, and input / output metal contacts connected with an external connection pad, extending in the first direction, and formed with at least two of the plurality of extension regions that are not formed with the plate common source line contact.

Embodiments of the present disclosure relate to a memory device and an operating method thereof. A memory device includes a common source line, a memory cell array, a bit line, and a conductive layer. The common source line is formed on a substrate. The memory cell array is formed on the common source line. The bit line is connected to the memory cell array. The conductive layer is formed over the bit line. In an erase operation, the memory device increases a voltage of the bit line to an erase voltage by capacitive coupling by increasing a voltage applied to the conductive layer.

An integrated circuit device includes a substrate having a peripheral circuit structure thereon, and a cell array structure extending on the peripheral circuit structure. The cell array structure includes: a gate stack including a plurality of insulation layers and a plurality of gate lines alternately arranged on the substrate, a plurality of channel structures each penetrating through the gate stack in a vertical direction perpendicular to a top surface of the substrate and comprising a monocrystalline channel layer, and a common source line, which extends on the gate stack, is in contact with the channel layer of the channel structure, and includes a semiconductor layer and a cover layer provided between the semiconductor layer and the channel layer.

A memory device may include a memory block and a control circuit. The memory block may include a first sub-block and a second sub-block that are connected between a common source line and a plurality of bit lines and may be vertically stacked. The control circuit may be configured to select any one of the common source line and the plurality of bit lines as a transmission path of an erase voltage based on positions of the first sub-block and the second sub-block, and perform erase operations on the first sub-block and the second sub-block in units of sub-blocks.

To provide a semiconductor device with improved reliability, and a data storage system including the same.SOLUTION: According to example embodiments, a semiconductor device and a data storage system including the same may include a channel structure including a plurality of channel holes and a channel pattern connecting the plurality of channel holes using a stopper. Accordingly, embodiments of the inventive concept provide a semiconductor device and a data storage system including the same having improved reliability by minimizing and / or improving contact failure due to mis-alignment with a conductive pattern functioning as a common source line in contact with a channel structure.SELECTED DRAWING: Figure 3

There are provided a semiconductor memory device and a manufacturing method thereof. The manufacturing method of the semiconductor memory device includes: forming a preliminary memory cell array that includes a gate stack structure and a channel structure, wherein the gate stack structure includes interlayer insulating layers and conductive patterns, alternately stacked on a first substrate, and wherein the channel structure has a first end portion that penetrates the gate stack structure and extends into the first substrate; forming a common source line to be in contact with a second end portion of the channel structure, the common source line formed on a first surface of the gate stack structure; removing the first substrate; and forming a bit line connected to the first end portion of the channel structure on a second surface of the gate stack structure that is opposite of the first surface of the gate stack structure.

A memory device capable of reducing peak current includes a plurality of strings of memory cells each including a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells. A method for operating a memory device includes pre-charging channel regions of the plurality of strings of memory cells through the common source line and setting a bit line voltage applied to the bit line while the channel regions of the plurality of strings of memory cells are being pre-charged after starting pre-charging the channel regions of the plurality of strings of memory cells.

A MRAM circuit is provided in the present invention, wherein each memory cell has three transistors, including a first transistor, a third transistor and a second transistor connected in order and series connection, a first node is connected between the first transistor and the third transistor, a second node is connected between the second transistor and the third transistor, and a common source line is connected with one terminal of the first transistor and the second transistor. A first MTJ set includes at least two MTJs in series connection and with one terminal connected to the first node, and a second MTJ set includes at least two MTJs in series connection and with one terminal connected to the second node.

Semiconductor devices and methods of operating semiconductor devices are provided. The semiconductor device includes a source layer, a plurality of channel structures, a plurality of gate electrodes, and a common source line. At least one gate electrode of the plurality of gate electrodes provides a GIDL line. During an erase operation, an erase voltage applied to the common source line reaches a target voltage, and after the erase voltage reaches the target voltage, a step increment voltage is added to the erase voltage such that a voltage level of the erase voltage is higher than a voltage level of the target voltage. After the step increment voltage has been added for a desired period of time, during a remaining operation of the erase operation, the voltage level of the erase voltage is decreased to the voltage level of the target voltage.

Disclosed is a nonvolatile memory device including a memory cell array including memory cells, bit lines and word lines connected with the memory cells, a common source line connected with the memory cells, a control logic circuit including a common source line noise control logic circuit and configured to generate voltages including a first voltage and a second voltage, a voltage selector configured to receive the voltages and configured to select at least one of the voltages, and a common source line driver configured to receive the at least one selected voltage and configured to control a voltage of the common source line, and the common source line noise control logic circuit is configured to control the voltage selector based on program information so as to select the at least one of the voltages.

An example memory device includes a substrate; and a first cell string and a second cell string on the substrate and between the first bit line and the common source line. The first cell string includes a first string selection transistor connected to the first string selection line, and first and third ground selection transistors connected to the first and second ground selection lines, respectively. The second cell string includes a second string selection transistor connected to the second string selection line, and second and fourth ground selection transistors connected to the first and second ground selection lines, respectively. When the first cell string is a selected cell string, in the second cell string, the second ground selection transistor and the fourth ground selection transistor are turned off, and at least one ground selection transistor between the second ground selection transistor and the fourth ground selection transistor is turned on.

A memory device includes a memory cell array having a plurality of memory blocks therein, including a target memory block. A voltage generator is provided, which is configured to generate an erase voltage and row line voltages, which are provided to the target memory block upon which an erase operation is to be performed. Control logic is provided, which is configured to control the memory cell array and the voltage generator. In addition, during operation, the erase voltage is provided to at least one of a bitline or a common source line associated with the target memory block, and a gate line of a transistor provided with the erase voltage is precharged before the erase voltage is provided to the at least one of the bitline or the common source line of the target memory block.