122results about How to "Lower channel resistance" patented technology

A DC-to-DC converter comprises an error amplifier, a comparator, a PWM controller, a power switch unit, and a control signal monitoring circuit. The PWM controller receives a comparison signal from the comparator and generates a digital control signal that controls the power switch unit such that the DC-to-DC converter supplies a regulated voltage onto a load. The control signal monitoring circuit monitors the digital control signal and detects either a heavy load or a light load condition based on characteristics of the digital control signal. Under the light load condition, the monitoring circuit generates a first enabling signal such that the DC-to-DC controller operates in a power-save mode. Under the heavy load condition, the monitoring circuit generates a second enabling signal such that the DC-to-DC controller operates in a normal operation mode. The DC-to-DC converter consumes substantially less power in the power-save mode than in the normal operation mode.

A source-drain buried graphene transistor device on a diamond-like carbon substrate and a manufacture method are applicable to radio frequency communication. The manufacture method includes: firstly, depositing a layer of diamond-like carbon amorphous carbon smooth in surface and stable in chemical property on the substrate by the aid of a magnetic filtered cathode vacuum arc system; secondly, etching a source trench and a drain trench on the diamond-like carbon amorphous carbon insulating layer and filling electrode metal into the trenches; thirdly, planarizing and cleaning the surface of the substrate prior to transferring graphene grown by a chemical vapor deposition method to the cleaned substrate; fourthly, growing gate insulating dielectric by an atomic layer deposition method and sputtering gate electrode metal; and finally, forming a metal gate by means of reactive ion etching and depositing low-K insulating dielectric to protect the device. Carrier mobility of a graphene transistor is high, and the source-drain buried structure is capable of decreasing the graphene length of a region uncovered by the gate, so that gate-source capacitance, gate-drain capacitance and channel resistance are reduced, and high-frequency performance and efficiency of the graphene transistor are improved. The source-drain buried graphene transistor device can be widely applied to small-sized high-frequency graphene integrated circuits.

The invention discloses a GaN-based enhanced power electronic device and a preparation method thereof. The GaN-based enhanced power electronic device comprises a substrate, a thin barrier Al (In, Ga)N/GaN heterostructure formed on the substrate, and a grid electrode, a source electrode and a drain electrode formed on the thin barrier Al (In, Ga)N/GaN heterostructure, wherein AlN passivation layers are formed in access areas between the grid electrode and the source electrode and between the grid electrode and the drain electrode. The AlN passivation layers with a polarization characteristic are utilized to restore two0-dimension electronic gas in channels of the thin barrier Al (In, Ga)N/GaN heterostructure under the AlN passivation layers, so that the conducting resistance of the device is lowered, and high-voltage current collapse of the device is inhibited. According to the invention, the controllability and the consistency of a threshold voltage of the GaN-based enhanced device are improved, the technology repeatability of the GaN-based enhanced device is eliminated, the yield rate of the GaN-based enhanced electronic device is improved, and the industrialization process of the GaN-based enhanced device is promoted.

The invention discloses a preparation method of a bottom n-type doped SiC-based UMOSFET with a p-type buried layer and a groove. The method is characterized in that the p-type buried layer (4) is formed through epitaxial growth on an n- drift layer (3); an n- drift layer (30) is formed through epitaxial growth on the p-type buried layer (4); a p-type base region layer (5) is formed through epitaxial growth on the n- drift layer (30); and an n-type doped layer (900) is formed at the bottom of a main groove (7). The electric field of a gate oxide layer (10) is effectively reduced in a reverse blocking state. Due to the shielding effects of the p-type buried layer (4) and the n-type doped layer (900), the thickness of the p-type base region layer (5) is greatly reduced, the groove is reduced to below 0.5[mu]m and the on-state performance is improved. The SiC-based UMOSFET has a relatively high Baliga optimum value and a relatively low switching loss. The invention further provides a structure of the SiC-based UMOSFET.

A non-volatile memory device may include a plurality of memory blocks including memory cells connected in series to bit lines, respectively. Each of the plurality of memory blocks may include a first sub memory block having a first group of memory cells, which are respectively connected in series between first select transistors connected to the bit lines, respectively, and second select transistors connected to a common source line, and a second sub memory block having a second group of memory cells, which are respectively connected in series between third select transistors connected to the bit lines, respectively, and fourth select transistors connected to the common source line.

The invention belongs to the technical field of semiconductor power devices, and relates to a transverse SOI power LDMOS. Compared with the existing structure, the power LDMOS provided by the invention has a three-dimensional gate structure, and an oxide layer thickness between the part extending to a trench gate field plate of a drift region from a gate and the drift region gradually changes from the gate to a drain end. In a forward conducting state, the trench gate forms a side channel to greatly reduce the channel resistance of the device; an electron accumulation layer is formed in the drift region to constitute a low resistance current channel, so as to greatly reduce the resistance in the drift region of the device; and the conducting resistance of the device is reduced by the two aspects. In a forward blocking state, the trench gate field plate extending to the drift region has a depletion effect on the drift region, thereby improving the concentration in the drift region and reducing the resistance in the drift region. Since most open state current flows by a charge accumulation layer, the specific on-state resistance of the transverse SOI power LDMOS provided by the invention is nearly not affected by the concentration in the drift region, so that the 2.5 power contradictory relationship of the specific on-state resistance Ron, sp of the device and the withstand voltage BV.

The invention discloses a 4H-silicon carbide based N-channel accumulating high-voltage insulated gate bipolar transistor. The 4H-silicon carbide based N-channel accumulating high-voltage insulated gate bipolar transistor is characterized in that the traditional inversion channel is replaced by an accumulation channel and an N type base region is adopted between a P type shielding layer and a gate oxide layer. The thickness and the dosage concentration of the N type base region are selected to guarantee that the region is completely deleted when the gate voltage is zero, and therefore, the bipolar transistor is closed in a normal state. When the gate voltage is high enough, the accumulation channel is formed at the interface of SiO2/SiC so that the bipolar transistor can be switched on. Current carriers in an accumulation layer are distributed farther away from the surface than current carriers in an inversion layer and a higher effective migration rate of the accumulation channel can be expected, and therefore, the differential on resistance of the 4H-SiC based high-voltage N-channel IGBT and the on voltage drop under specific on current density and gate voltage can be effectively reduced by replacing the traditional inversion channel with the accumulation channel, and consequently, the energy loss of the bipolar transistor in the on state can be effectively reduced.

The invention discloses a 4H-SiC metal semiconductor field effect transistor with a slope-shaped grid. The 4H-SiC metal semiconductor field effect transistor comprises a 4H-SiC semi-insulating substrate, a P-type buffer layer and an N-type channel layer from bottom to top, a source electrode cap layer and a drain electrode cap layer are arranged on the surface of the N-type channel layer, a source electrode and a drain electrode are arranged on the surface of the source electrode cap layer and the surface of the drain electrode cap layer respectively, a slope-shaped groove inclined towards one side of the source electrode cap layer is formed in the upper end face of the N-type channel layer, the slope-shaped grid is arranged is arranged in the slope-shaped groove, the lower end face of the slope-shaped grid is matched with the slope-shaped groove, the upper end face of the slope-shaped grid is parallel to the upper end face of the N-type channel layer, and the distance between the slope-shaped grid and the source electrode cap layer is smaller than that between the slope-shaped grid and the drain electrode cap layer. The field effect transistor has the advantages of being high in drain electrode output current and excellent in frequency property.

In the memory device, a lower memory cell string including a first channel structure, a plurality of first word line layers, and a first insulating layer is formed over a substrate. The first channelstructure extends from the substrate and passes through the first word line layer and the first insulating layer. Inter-stack contacts are formed over the lower memory cell string and coupled to the first channel structure. An upper memory cell string is formed over the inter-stack contacts. The upper memory cell string includes a second channel structure, a plurality of second word lines, and a second insulating layer. The second channel structure passes through the second word line and the second insulating layer and extends into the inter-stack contacts and further laterally into the secondinsulating layer. A channel dielectric region of the second channel structure is above the inter-stack contacts.

The invention discloses a material structure of a GaN-base enhancement-mode electronic device, and relates to the technical field of application of GaN-base power electronics and microwave power amplifiers. The material structure comprises a substrate, a GaN buffer layer and an Al(In,Ga)N barrier layer which are sequentially formed on the substrate, and a passivation layer, wherein the Al(In,Ga)N barrier layer forms a thin barrier Al(In,Ga)N/GaN heterostructure; and the passivation layer is formed on the thin barrier Al(In,Ga)N layer, and prepared from n-GaN, SiO2 or SiNx. Therefore, an enhancement-mode gate structure can be formed without etching the Al(In,Ga)N barrier layer; the density of two-dimensional electron gas in a thin barrier Al(In,Ga)N/GaN heterojunction channel outside a gate is significantly improved by utilizing polarization of the passivation layer or an n-type doping effect; the GaN-base enhancement-mode power electronic device with good threshold uniformity and low dynamic on resistance can be prepared; a yield of the device is increased; and an industrialization progress of the GaN-base power electronic device is pushed.

Devices, methods, and processes that improve immunity to transient voltages and reduce parasitic impedances. Immunity to unclamped inductive switching events is improved. For example, a trench-gated power MOSFET device having a SiGe source is provided, where the SiGe source reduces parasitic npn transistor gain by reducing hole current in the body or well region, thereby decreasing the likelihood of a latch-up condition. A trench-gated power MOSFET device having a SiGe body or well region is also provided. A SiGe body reduces hole current when the body diode is turned on, thereby reducing reverse recovery power losses. Other device characteristics are also improved. For example, parasitic gate impedance can reduced through the use of a poly SiGe gate. Also, channel resistance can be reduced through the use of a SiGe layer near the device's gate and a thick oxide region can be formed under the trench gate to reduce gate-to-drain capacitance.

The invention provides a VDMOS device and a manufacturing method thereof. The manufacturing method comprises the following steps that: a gate oxide layer is formed in gate trenches of a silicon substrate, and the gate trenches of the silicon substrate are filled with polycrystalline silicon; a body region is formed; first ions and second ions are sequentially injected into the silicon substrate, and the silicon substrate is subjected to annealing treatment, and therefore, source contact regions can be formed at two sides of each gate trench, and the first ions and the second ions have the same type, and the energy of the first ions is larger than that of the second ions, and the dosage of the first ions is smaller than that of the second ions; a dielectric layer is formed; after a source trench mask is formed on the dielectric layer, and the silicon substrate is etched, and therefore, source trenches can be formed between the source contact regions; and the source trench mask is removed, and a metal layer is formed on the silicon substrate. With the manufacturing method provided by the invention adopted, the contact resistance of the VDMOS device can be decreased without changing the structure of the device, increasing the manufacturing process difficulty of the device and increasing the manufacturing cost of the device, and therefore, the performance of the device can be improved.

The invention provides a semiconductor variable capacitor which comprises a semiconductor substrate, an ion trap, a gate dielectric layer, a gate and an insulation layer, wherein the ion trap is arranged on the semiconductor substrate, a plurality of ion doping areas are arranged in the ion trap, and each area is respectively used as a source or a drain; the gate dielectric layer is arranged on the ion trap; the gate is arranged between the source and the drain and is stacked on the gate dielectric layer; the insulation layers are arranged on the upper surface of the ion trap, the side wall stacked by the gate dielectric layer and the gate, and the upper surface of the gate and the sides of the insulation layers are provided with side walls. Compared with the traditional semiconductor variable capacitor, as the semiconductor variable capacitor is arranged on the overlapping part of the gate and the drain, and the overlapping part of the gate and the source, the doping concentration ratio of the invention is lighter than that of the semiconductor variable capacitor containing LDD/Pck, the width of the consumed layer is increased, the capacitor Cf values between the gate and the source and between the gate and the drain are decreased, and thus, the frequency modulating range of the capacitor is enhanced.

An ink reservoir (166) has a plurality of thin bodies (164) provided in a housing (161) at gaps from each other. Ink in the housing (161) is held by a capillary force generated by the thin bodies (164). An ink guide portion (167) which is set at a gap between one end of the liquid ink (166) and an inner wall of the housing (161) is provided so that a capillary force in the vicinity of an ink supply port (165) is larger than that of the liquid reservoir (166).

The present invention relates to a laterally diffused metal oxide semiconductor field effect transistor with an RESURF (reduced surface field) structure. The laterally diffused metal oxide semiconductor field effect transistor includes a substrate, a gate, a source, a drain, a body region, a field oxide region which is located between the source and the drain, as well as a first well region and a second well region which are located on the substrate; a plurality of gate doped regions are arranged in the second well region below the gate; the polysilicon gate of the gate is of a multi-section structure; the sections of the polysilicon gate are separated from one another; the gate doped regions are arranged below gaps between the sections of the polysilicon gate; and each gate doped region is electrically connected with one of two sections of the polysilicon gate which are located at two sides of the gate doped region, wherein the one section of the polysilicon gate electrically connected with the gate doped region is adjacent to the source. According to the laterally diffused metal oxide semiconductor field effect transistor with the RESURF structure of the invention, the number of trench electrons is increased, and the electrons are accelerated a plurality of times during a process of flowing from the source to the drain, equivalently, and a trench electric field and trench current can be improved, and therefore, trench resistance is reduced, and on-resistance can be reduced.