256 results about "Wide-bandgap semiconductor" patented technology

The invention provides a wide bandgap semiconductor heteroepitaxial layer growth process parameter adjustment method and system, and relates to the technical field of semiconductors, and the method comprises the steps: obtaining substrate parameters, constructing a digital twin model, predicting an initial strain evolution trend, and determining an optimal initial process parameter; acquiring multi-source data through an in-situ ellipsometer, a reflective high-energy electron diffraction sensor and an acoustic emission sensor in the growth process, and calculating a strain tensor field and defect density distribution by adopting a deep neural network; layered progressive process parameter optimization is executed; and adjusting the growth process according to an optimization result. According to the method, accurate regulation and control of process parameters can be realized, the defect density is reduced, and the quality of the wide bandgap semiconductor heteroepitaxial layer is improved.

The invention relates to a heterojunction composite material and a preparation method and application thereof, and belongs to the technical field of catalysts. The preparation method of the heterojunction composite material comprises the following steps: dispersing nano cadmium sulfide in water to obtain a nano cadmium sulfide dispersion liquid, then adding a triazinyl covalent organic framework, fully reacting at 75-85 DEG C, centrifuging, precipitating, washing and drying to obtain the heterojunction composite material. The narrow-band-gap semiconductor cadmium sulfide and the wide-band-gap semiconductor triazinyl covalent organic framework are compounded to form the heterojunction structure composite material photocatalyst, and the narrow-band-gap semiconductor cadmium sulfide and the wide-band-gap semiconductor triazinyl covalent organic framework interact with each other, so that the response range of sunlight is widened, separation and transfer of photo-induced electrons and holes are promoted, and the photoelectric conversion efficiency is improved. Therefore, the photocatalytic oxidation-reduction capacity of the catalyst is improved, and the photocatalytic performance of the catalyst is finally improved. The heterojunction composite material can be applied to the field of cleaning and environmental protection as a photocatalyst, and has excellent hydrogen production efficiency.

To provide a semiconductor device capable of achieving reduction in recovery loss.SOLUTION: A vertical semiconductor device comprising a wide gap semiconductor includes an n-type first layer. The semiconductor device includes an n-type second layer that is in contact with an upper surface of the first layer, the second layer having an n-type impurity concentration lower than that of the first layer. The semiconductor device includes a p-type body layer in contact with an upper surface of the second layer. The semiconductor device includes an n-type source region disposed on an upper part of the body layer. The semiconductor device includes a gate electrode structure disposed in contact with the body layer. A p-type first specific region is disposed in the first layer. The first specific region is disposed in a part of the first layer as viewed in a direction vertical to the upper surface of the first layer.SELECTED DRAWING: Figure 1

A power conversion system is provided, which system includes a first power converter including power electronic switches of a first type that are switchable to provide electric power conversion; and a second power converter connected in parallel to the first power converter. The second power converter includes power electronic switches of a second type that are switchable to provide electric power conversion. The second type is different from the first type. The second type of power electronic switches includes wide bandgap semiconductor switches. The system further includes a controller configured to operate the power conversion system in a first operating mode in which the second power converter is operated at a first switching frequency, and in a second operating mode in which the second power converter is operated at a second switching frequency of the power electronic switches and the first power converter is operated to provide power conversion.

According to the field effect transistor, a first JFET is formed in a first epitaxial layer, and a second MOSFET is formed in a second epitaxial layer. The forbidden band width of the material of the first epitaxial layer is greater than that of the material of the second epitaxial layer; the second epitaxial layer is formed on the top surface of the first epitaxial layer, and the contact surface of the first epitaxial layer and the second epitaxial layer is heterojunction; a first source region of the first JFET and a second drain region of the second MOSFET are connected through a first floating metal contact hole penetrating through the heterojunction. A first gate region of the first JFET is connected to a source consisting of a front metal layer through a deep contact hole penetrating through the heterojunction; the second source region is connected with the source electrode. The back face of the first drain region is connected to a drain electrode composed of a back face metal layer. The invention further discloses a manufacturing method of the field effect transistor. The invention has the advantages of a wide bandgap semiconductor material device, and can overcome the problems of high channel carrier mobility, high driving voltage and poor reliability of the gate dielectric layer of the wide bandgap semiconductor material device.

Systems and methods for laser-based surface processing operations on a wide bandgap semiconductor wafer, such as a silicon carbide semiconductor wafer, are provided. In one example, a method includes removing a wide bandgap semiconductor wafer from a boule using a removal process. The method includes ablating, with one or more lasers, an exposed surface resulting from the removal process to remove material from the exposed surface, wherein ablating, with one or more lasers, the exposed surface reduces a thickness of semiconductor material (e.g., by about 25 microns or greater).

A power tool includes a working component configured with the maximum output rotational speed; an electric motor configured with the maximum rotational speed; a transmission assembly configured with a transmission ratio; a driver circuit including one or more drive switches; and a controller for outputting a control signal to control the one or more drive switches of the driver circuit. At least one drive switch in the driver circuit includes a wide bandgap semiconductor switch, and the ratio of the required maximum rotational speed of the electric motor to the maximum rotational speed of the electric motor is less than or equal to 0.9. The electric motor system of the power tool has good electrical performance.

A thin and light optical waveguide lens, which can be applied to a display device. The optical waveguide lens comprises waveguide plates (1) made of a wide bandgap semiconductor material and protective films (2) made of an optical resin material; at least one surface of the waveguide plates (1) is provided with a grating structure (11); the protective films (2) are arranged on the surfaces of the waveguide plates (1), and are embedded in grating gaps of the grating structure (11); and the outer side surfaces of the corresponding protective film (2) and the grating structure (11) are approximately located on the same plane, and / or said protective film (2) covers the outer side surface of the grating structure (11). According to the optical waveguide lens, high-refractive-index glass waveguide plates (1) having a refractive index of 1.7-1.9 are replaced with the waveguide plates (1) made of the wide bandgap semiconductor material, and cover glass is replaced with the protective films (2) made of the optical resin material, such that hardening, scratch resistance, anti-fog, anti-slip, anti-smudge, high light transmittance and other functions are integrated while the waveguide plates (1) are protected on both sides, the overall thickness of the optical waveguide lens is reduced and the optical properties are improved.

An example method includes providing a wide bandgap semiconductor workpiece. The example method includes exposing the wide bandgap semiconductor workpiece to one or more electrical discharges from an electrical discharge machining (EDM) system to reduce a surface roughness of the wide bandgap semiconductor workpiece. Exposing the wide bandgap semiconductor workpiece to the one or more electrical discharges may include submerging a surface of the wide bandgap semiconductor workpiece in a dielectric fluid; positioning an electrode head relative to the surface such that a gap is defined between an end of the electrode head and the surface; and generating an electrical discharge across the gap to create a plasma zone within the gap such that a material is removed from the surface.

A power supply system including a housing, an internal non-removable battery, an output, a power converter, and an electronic processor. The internal non-removable battery received in the housing and having a nominal voltage of at least 12 Volts. The output provided on the housing. The power converter coupled between the internal non-removable battery and the output. The power converter including a first switch. The power converter also converts power received from the internal non-removable battery. The electronic processor coupled to the power converter and controls operation of the power converter by controlling the first switch at a switching frequency of at least 100 kHz.

The invention belongs to the field of high-power electric vacuum devices, relates to heat transport performance of an interface ceramic material in a high-power electric vacuum device, and particularly provides a deep learning potential-based wide bandgap semiconductor heat transport performance calculation method, which is used for solving various problems of existing methods. According to the method, firstly, the deep learning potential is constructed by adopting a first principle, then the deep learning potential is used as an empirical potential function, and the heat transport performance of the wide bandgap semiconductor is calculated through a molecular dynamics method, so that large-scale molecular dynamics simulation is realized, and a temperature conduction process and a heat transfer process of a long-time dimension can be accurately predicted; errors caused by empirical potential simulation calculation are avoided, and the time and operation cost of first principle calculation are greatly reduced.

The invention relates to the technical field of wide bandgap semiconductor materials, in particular to a rapid detection method for a fatal defect of a gallium oxide epitaxial wafer. The method comprises the following steps: S1, preparing a gallium oxide epitaxial wafer; s2, performing a nanoindentation test on the surface of the epitaxial wafer to obtain a local mechanical property data load-displacement curve and an electrical response data current-time curve; s3, based on correlation analysis of the mechanical property data and the electrical response data, positioning and classifying fatal defects in the epitaxial wafer; the fatal defects comprise dislocation and cracks, and are judged by the following modes: an area in which the elastic modulus is reduced by more than 10% and the current is suddenly increased is a dislocation enrichment area; the area where the load-displacement curve has the onrushing phenomenon is a crack defect. The method is based on the nanoindentation technology, rapid positioning and classification of defects are achieved through mechanical-electrical coupling response, the limitation of a traditional method is broken through, and core technical support is provided for quality control and process upgrading of the gallium oxide epitaxial wafer.

To provide a wide band gap power device comprising a JBS diode having improved electrical characteristics, and a manufacturing method thereof.SOLUTION: In a Junction Barrier Schottky diode 50, a body 55 of silicon carbide having a first conductivity type and a surface 55A is formed by: a drift region 59 and a plurality of first portions 59A delimited by the surface 55A; a second portion 59B; a plurality of first implanted regions 62 of a second conductivity type, extending into the drift region 59 from the surface 55A; and a plurality of metal portions (a first portion 65A, a second portion 66A) arranged on the surface 55A. Each metal portion is in Schottky contact with a respective surface portion of the plurality of surface portions so as to form a first-type Schottky diode 51 and a second-type Schottky diode 52. The first-type Schottky diode and the second-type Schottky diode each have, at equilibrium, a Schottky barrier having a height different from each other.SELECTED DRAWING: Figure 2

The present invention specifically relates to an accumulation-type wide bandgap semiconductor trench MOSFET device structure and a method for preparing the same. The structure comprises at least a substrate, an epitaxial layer, a source P+ region, and a gate electrode; an N+ current channel is provided below the gate electrode trench, and N-accumulation-type channels and / or P-inversion channels are provided on both sides of the gate electrode trench. The N+ current channel is prepared by ion implantation and is located in the epitaxial layer. The N-accumulation-type channels and / or P-inversion channels are formed by the lateral diffusion effect during ion implantation of the N+ current channel. The present invention forms the N+ current channel through a trench bottom ion implantation process, and utilizes the lateral diffusion effect of this process during ion implantation to naturally form the N-accumulation-type channel and / or P-inversion channel. Furthermore, the channel doping concentration and thickness can be carefully controlled by controlling the mask thickness of the trench sidewalls during ion implantation of the N+ current channel, thereby achieving the purpose of enhancing channel mobility and reducing device on-resistance without the need for additional processes.

A method for preparing an interconnection line of a diamond device belongs to the field of processing and preparation of ultra-wide bandgap semiconductor electronic devices. It is characterized in that: designing a circuit layout and cleaning a diamond substrate (110); then performing a photolithography process to prepare device units (120) and an interconnection region (130); plating a metal catalyst (131) on the interconnection region of the diamond surface; and in-situ growing a conductive carbon nanomaterial (132) on the diamond surface as the interconnection line. The present invention obtains a low-resistance and stable ohmic contact interconnection line on the diamond substrate, effectively avoiding the limitation of device failure caused by the breakage of the interconnection line formed by an ultra-thin metal film at present; the carbon nanomaterial interconnection line can work normally under high-temperature and high-pressure conditions and can meet the requirements of the future working environment of diamond devices. The obtained interconnection line has a low contact resistance with the diamond substrate, strong bonding force, and can withstand high-temperature and high-pressure working environments, laying a good foundation for the back-end process of future diamond-based integrated circuit preparation.

A method for forming semiconductor devices includes: attaching a glass structure to a wide band-gap semiconductor wafer having a plurality of semiconductor devices; forming at least one pad structure electrically connected to at least one doping region of a semiconductor substrate of the wide band-gap semiconductor wafer, by forming electrically conductive material within at least one opening extending through the glass structure; and reducing a thickness of the wide band-gap semiconductor wafer after attaching the glass structure. Additional methods for forming semiconductor devices are described.

The invention relates to the technical field of semiconductor luminescent materials, in particular to a wide-band-gap semiconductor crystal luminescent material and a preparation method and application thereof. The chemical composition of the CdLCl < 2 >. H2O or the Cd2L2 (Ac) (H2O) is [CdLCl] < 2 >. H2O]. L represents a quinoline carboxylic acid ligand; ac represents an acetate ion; the crystal structure of the wide-band-gap semiconductor crystal luminescent material is a one-dimensional chain structure. The crystal complex is mainly formed by bridging cadmium ions with carboxyl of a quinoline carboxylic ligand, and the formed crystal complex emits light in a red region, is suitable for various light-emitting application scenes, and solves the problems that an existing wide-band-gap semiconductor light-emitting material is relatively low in light-emitting efficiency, light stability and heat stability, and the light-emitting efficiency is low. And the light-emitting wavelength is difficult to regulate and control.

An example method includes providing a wide bandgap semiconductor workpiece. The example method includes exposing the wide bandgap semiconductor workpiece to one or more electrical discharges from an electrical discharge machining (EDM) system to reduce a surface roughness of the wide bandgap semiconductor workpiece. Exposing the wide bandgap semiconductor workpiece to the one or more electrical discharges may include submerging a surface of the wide bandgap semiconductor workpiece in a dielectric fluid; positioning an electrode head relative to the surface such that a gap is defined between an end of the electrode head and the surface; and generating an electrical discharge across the gap to create a plasma zone within the gap such that a material is removed from the surface.

The present application relates to a kind of hydrogen terminal diamond / gallium oxide hetero lateral diode and preparation method, lateral diode includes: diamond substrate layer, n type Ga2O3 layer, hydrogen terminal diamond surface layer, cathode and anode, wherein, the n type Ga2O3 layer is located on one side of the diamond substrate layer, the hydrogen terminal diamond surface layer is located on the other side of the diamond substrate layer, the cathode is located on the n type Ga2O3 layer, the anode is located on the hydrogen terminal diamond surface layer.This lateral diode is combined together by the method of hetero integration p type electrically conductive diamond and n type electrically conductive Ga2O3, preparation ultra-wide bandgap semiconductor hetero integrated quasi-vertical diode device, effectively solve the problem that diamond is difficult to realize n type doping, gallium oxide is difficult to realize p type doping, improve the breakdown voltage of diode, realize ultra-wide bandgap semiconductor complementary conduction device.

The present disclosure relates to a 2T memory cell, and more particularly to a technology including a first transistor that performs data write and erase operations and a second transistor that performs a data read operation. The first transistor is formed vertically above the second transistor, and the first drain of the first transistor serves as the second gate of the second transistor. The channel of the first transistor has a longer effective channel length than the channel of the second transistor. High-density integration is possible by forming the first transistor through a self-aligned process, and data retention characteristics are improved by forming the channel of the first transistor with a semiconductor material having a wide bandgap such as polysilicon or IGZO. The 2T memory cell according to the present disclosure can simultaneously achieve high-speed operation and high integration density.

The invention belongs to the field of preparation of wide bandgap semiconductor materials, and particularly discloses a preparation method of a low-stress large-size polycrystalline diamond wafer, which comprises the following steps: by taking a substrate as a growth foundation of diamond, sequentially carrying out diamond inoculation treatment and MPCVD process treatment on the substrate so as to grow and form an initial growth layer on the substrate; the primary growth layer serves as a growth foundation of diamond, diamond inoculation treatment and MPCVD process treatment are sequentially conducted on the primary growth layer, a secondary growth layer is formed on the primary growth layer in a growing mode, and an elastic buffer interface is formed between the primary growth layer and the secondary growth layer. By means of the method, the problems of wafer warping, film layer microcracks and film layer stripping caused by the residual stress of the large-size wafer can be solved, active reconstruction and release of the residual stress are facilitated through the successive multiple inoculation and growth processes, and then preparation of the polycrystalline diamond wafer with low stress, large size and high crystallization quality is achieved.

A semiconductor device comprises a semiconductor layer structure that comprises at least one wide bandgap semiconductor layer; a gate pad on the semiconductor layer structure; and a gate runner that is electrically connected to the gate pad, the gate runner comprising a polysilicon gate runner and a metal gate runner on the polysilicon gate runner opposite the semiconductor layer structure. A gap is provided in the metal gate runner above a first portion of the polysilicon gate runner, where the gap separates the metal gate runner into a first metal gate runner segment and a second metal gate runner segment or separates the first metal gate runner segment from the gate pad.

In one aspect, a field-effect transistor device includes: a semiconductor layer of a wide-bandgap semiconductor layer, the semiconductor layer comprising a source region, a drain region and a floating body region between the source region and the drain region; a first gate and a second gate arranged along the floating body region of the semiconductor layer, wherein the first gate is arranged at a first side of the semiconductor layer and the second gate is arranged at a second side of the semiconductor layer, opposite the first side; and a charge storage island arranged along the floating body region in contact with the second side of the semiconductor layer such that the charge storage island is arranged between the floating body region and the second gate. The charge storage island is configured to define a potential well for charge carriers attracted from a channel.

The utility model relates to a deep ultraviolet photoelectric detector with an ultra-wide bandgap semiconductor heterojunction structure. The deep ultraviolet photoelectric detector comprises a substrate, a DBR layer, a Zn-doped beta-Ga2O3 layer, a barrier layer, a Ga-doped gamma-GeO2 layer and a current collection layer, the DBR layer is configured on the substrate, the Zn-doped beta-Ga2O3 layer is configured on the DBR layer, the barrier layer is configured on the Zn-doped beta-Ga2O3 layer, the Ga-doped gamma-GeO2 layer is configured on the barrier layer, and the current collection layer is configured on the Ga-doped gamma-GeO2 layer; the Zn-doped beta-Ga2O3 layer is an N-type semiconductor, the Ga-doped gamma-GeO2 layer is a P-type semiconductor, and the Zn-doped beta-Ga2O3 layer and the Ga-doped gamma-GeO2 layer form a P-N heterojunction; by arranging the Zn-doped beta-Ga2O3 layer and the Ga-doped gamma-GeO2 layer, the photoelectric conversion efficiency is good; the beta-Ga2O3 is favorable for enhancing the response to an ultraviolet wave band; gamma-GeO2 has a wide light absorption range, and the combination of gamma-GeO2 and gamma-GeO2 can improve the sensitivity and photoelectric conversion efficiency of the deep ultraviolet photoelectric detector; by arranging the P-N heterojunction, the photoelectric conversion efficiency is improved, the dark current is effectively reduced, the detection noise is reduced, and the signal-to-noise ratio is improved.

A semiconductor structure can comprise a plurality of first semiconductor layers comprising wide bandgap semiconductor layers, a narrow bandgap semiconductor layer, and a chirp layer between the plurality of first semiconductor layers and the narrow bandgap semiconductor layer. The values of overlap integrals between different electron wavefunctions in a conduction band of the chirp layer can be less than 0.1 for intersubband transition energies greater than 1.0 eV, and / or the values of overlaps between electron wavefunctions and barrier centers in a conduction band of the chirp layer can be less than 0.4 nm−1, when the structure is biased at an operating potential. The chirp layer can comprise a short-period superlattice with alternating wide bandgap barrier layers and narrow bandgap well layers, wherein the thickness of the barrier layers, or the well layers, or the thickness of both the barrier and well layers changes throughout the chirp layer.

The semiconductor transistor device includes a gate trench structure extending in a vertical direction from a wide bandgap semiconductor body first surface into the wide bandgap semiconductor body, the gate trench structure including a gate trench dielectric and a gate trench electrode. The semiconductor transistor device includes a first conductivity type body region adjoining a first sidewall of the gate trench structure. The first lateral direction is perpendicular to the second lateral direction. The semiconductor transistor device includes a first conductivity type auxiliary structure adjoining a bottom side of the gate trench structure and a second conductivity type drift structure adjoining a bottom side of the body region. The drift structure includes a drift layer arranged in a vertical direction between the bottom side of the auxiliary structure and the second surface of the wide bandgap semiconductor body. In a first location in a second lateral direction, a first sub-region of the drift structure extends from a bottom side of the body region to the drift layer. At a second location in a second lateral direction, the drift structure second sub-region extends from the bottom side of the body region to the top side of the auxiliary structure lateral sub-region.

A semiconductor device includes: a plurality of semiconductor chips spaced apart from one another; and a conductive part. The plurality of semiconductor chips include respective semiconductor switching elements. The conductive part connects the plurality of semiconductor chips in parallel. A material of the semiconductor switching elements of the plurality of semiconductor chips includes a wide bandgap semiconductor. At least one of the semiconductor switching elements has a channel length of 1.5 μm or less.

The invention discloses a wide bandgap semiconductor device, which can be used in the field of semiconductors, and comprises a P-type column region, an N-type column region, a P-type buried layer, a P-type connecting layer, a grid electrode and a source electrode, wherein the P-type column regions and the N-type column regions are alternately arranged along a first direction; the P-type column region, the P-type buried layer, the P-type connecting layer and the source electrode are arranged along a second direction, and the P-type connecting layer is in contact with the source electrode; the first direction is perpendicular to the second direction; the N-type column region, the grid electrode and the source electrode are arranged along a second direction; the P-type buried layers and the P-type connecting layers are discontinuously distributed in a third direction, any P-type buried layer is electrically connected with at least one P-type connecting layer in a three-dimensional space, and any P-type column region is electrically connected with at least one P-type buried layer in the three-dimensional space; the third direction is perpendicular to the first direction and the second direction. Therefore, an electrical connection path of the P-type column region, the P-type buried layer, the P-type connection layer and the source electrode is constructed, and the dynamic resistance loss of the device is effectively reduced.