177 results about "Wide-bandgap semiconductor" patented technology

A power tool includes a working component configured with the maximum output rotational speed; an electric motor configured with the maximum rotational speed; a transmission assembly configured with a transmission ratio; a driver circuit including one or more drive switches; and a controller for outputting a control signal to control the one or more drive switches of the driver circuit. At least one drive switch in the driver circuit includes a wide bandgap semiconductor switch, and the ratio of the required maximum rotational speed of the electric motor to the maximum rotational speed of the electric motor is less than or equal to 0.9. The electric motor system of the power tool has good electrical performance.

An example method includes providing a wide bandgap semiconductor workpiece. The example method includes exposing the wide bandgap semiconductor workpiece to one or more electrical discharges from an electrical discharge machining (EDM) system to reduce a surface roughness of the wide bandgap semiconductor workpiece. Exposing the wide bandgap semiconductor workpiece to the one or more electrical discharges may include submerging a surface of the wide bandgap semiconductor workpiece in a dielectric fluid; positioning an electrode head relative to the surface such that a gap is defined between an end of the electrode head and the surface; and generating an electrical discharge across the gap to create a plasma zone within the gap such that a material is removed from the surface.

To provide a wide band gap power device comprising a JBS diode having improved electrical characteristics, and a manufacturing method thereof.SOLUTION: In a Junction Barrier Schottky diode 50, a body 55 of silicon carbide having a first conductivity type and a surface 55A is formed by: a drift region 59 and a plurality of first portions 59A delimited by the surface 55A; a second portion 59B; a plurality of first implanted regions 62 of a second conductivity type, extending into the drift region 59 from the surface 55A; and a plurality of metal portions (a first portion 65A, a second portion 66A) arranged on the surface 55A. Each metal portion is in Schottky contact with a respective surface portion of the plurality of surface portions so as to form a first-type Schottky diode 51 and a second-type Schottky diode 52. The first-type Schottky diode and the second-type Schottky diode each have, at equilibrium, a Schottky barrier having a height different from each other.SELECTED DRAWING: Figure 2

A method for forming semiconductor devices includes: attaching a glass structure to a wide band-gap semiconductor wafer having a plurality of semiconductor devices; forming at least one pad structure electrically connected to at least one doping region of a semiconductor substrate of the wide band-gap semiconductor wafer, by forming electrically conductive material within at least one opening extending through the glass structure; and reducing a thickness of the wide band-gap semiconductor wafer after attaching the glass structure. Additional methods for forming semiconductor devices are described.

An example method includes providing a wide bandgap semiconductor workpiece. The example method includes exposing the wide bandgap semiconductor workpiece to one or more electrical discharges from an electrical discharge machining (EDM) system to reduce a surface roughness of the wide bandgap semiconductor workpiece. Exposing the wide bandgap semiconductor workpiece to the one or more electrical discharges may include submerging a surface of the wide bandgap semiconductor workpiece in a dielectric fluid; positioning an electrode head relative to the surface such that a gap is defined between an end of the electrode head and the surface; and generating an electrical discharge across the gap to create a plasma zone within the gap such that a material is removed from the surface.

The present application relates to a kind of hydrogen terminal diamond / gallium oxide hetero lateral diode and preparation method, lateral diode includes: diamond substrate layer, n type Ga2O3 layer, hydrogen terminal diamond surface layer, cathode and anode, wherein, the n type Ga2O3 layer is located on one side of the diamond substrate layer, the hydrogen terminal diamond surface layer is located on the other side of the diamond substrate layer, the cathode is located on the n type Ga2O3 layer, the anode is located on the hydrogen terminal diamond surface layer.This lateral diode is combined together by the method of hetero integration p type electrically conductive diamond and n type electrically conductive Ga2O3, preparation ultra-wide bandgap semiconductor hetero integrated quasi-vertical diode device, effectively solve the problem that diamond is difficult to realize n type doping, gallium oxide is difficult to realize p type doping, improve the breakdown voltage of diode, realize ultra-wide bandgap semiconductor complementary conduction device.

The present disclosure relates to a 2T memory cell, and more particularly to a technology including a first transistor that performs data write and erase operations and a second transistor that performs a data read operation. The first transistor is formed vertically above the second transistor, and the first drain of the first transistor serves as the second gate of the second transistor. The channel of the first transistor has a longer effective channel length than the channel of the second transistor. High-density integration is possible by forming the first transistor through a self-aligned process, and data retention characteristics are improved by forming the channel of the first transistor with a semiconductor material having a wide bandgap such as polysilicon or IGZO. The 2T memory cell according to the present disclosure can simultaneously achieve high-speed operation and high integration density.

The invention belongs to the field of preparation of wide bandgap semiconductor materials, and particularly discloses a preparation method of a low-stress large-size polycrystalline diamond wafer, which comprises the following steps: by taking a substrate as a growth foundation of diamond, sequentially carrying out diamond inoculation treatment and MPCVD process treatment on the substrate so as to grow and form an initial growth layer on the substrate; the primary growth layer serves as a growth foundation of diamond, diamond inoculation treatment and MPCVD process treatment are sequentially conducted on the primary growth layer, a secondary growth layer is formed on the primary growth layer in a growing mode, and an elastic buffer interface is formed between the primary growth layer and the secondary growth layer. By means of the method, the problems of wafer warping, film layer microcracks and film layer stripping caused by the residual stress of the large-size wafer can be solved, active reconstruction and release of the residual stress are facilitated through the successive multiple inoculation and growth processes, and then preparation of the polycrystalline diamond wafer with low stress, large size and high crystallization quality is achieved.

A semiconductor device comprises a semiconductor layer structure that comprises at least one wide bandgap semiconductor layer; a gate pad on the semiconductor layer structure; and a gate runner that is electrically connected to the gate pad, the gate runner comprising a polysilicon gate runner and a metal gate runner on the polysilicon gate runner opposite the semiconductor layer structure. A gap is provided in the metal gate runner above a first portion of the polysilicon gate runner, where the gap separates the metal gate runner into a first metal gate runner segment and a second metal gate runner segment or separates the first metal gate runner segment from the gate pad.

In one aspect, a field-effect transistor device includes: a semiconductor layer of a wide-bandgap semiconductor layer, the semiconductor layer comprising a source region, a drain region and a floating body region between the source region and the drain region; a first gate and a second gate arranged along the floating body region of the semiconductor layer, wherein the first gate is arranged at a first side of the semiconductor layer and the second gate is arranged at a second side of the semiconductor layer, opposite the first side; and a charge storage island arranged along the floating body region in contact with the second side of the semiconductor layer such that the charge storage island is arranged between the floating body region and the second gate. The charge storage island is configured to define a potential well for charge carriers attracted from a channel.

The utility model relates to a deep ultraviolet photoelectric detector with an ultra-wide bandgap semiconductor heterojunction structure. The deep ultraviolet photoelectric detector comprises a substrate, a DBR layer, a Zn-doped beta-Ga2O3 layer, a barrier layer, a Ga-doped gamma-GeO2 layer and a current collection layer, the DBR layer is configured on the substrate, the Zn-doped beta-Ga2O3 layer is configured on the DBR layer, the barrier layer is configured on the Zn-doped beta-Ga2O3 layer, the Ga-doped gamma-GeO2 layer is configured on the barrier layer, and the current collection layer is configured on the Ga-doped gamma-GeO2 layer; the Zn-doped beta-Ga2O3 layer is an N-type semiconductor, the Ga-doped gamma-GeO2 layer is a P-type semiconductor, and the Zn-doped beta-Ga2O3 layer and the Ga-doped gamma-GeO2 layer form a P-N heterojunction; by arranging the Zn-doped beta-Ga2O3 layer and the Ga-doped gamma-GeO2 layer, the photoelectric conversion efficiency is good; the beta-Ga2O3 is favorable for enhancing the response to an ultraviolet wave band; gamma-GeO2 has a wide light absorption range, and the combination of gamma-GeO2 and gamma-GeO2 can improve the sensitivity and photoelectric conversion efficiency of the deep ultraviolet photoelectric detector; by arranging the P-N heterojunction, the photoelectric conversion efficiency is improved, the dark current is effectively reduced, the detection noise is reduced, and the signal-to-noise ratio is improved.

A semiconductor structure can comprise a plurality of first semiconductor layers comprising wide bandgap semiconductor layers, a narrow bandgap semiconductor layer, and a chirp layer between the plurality of first semiconductor layers and the narrow bandgap semiconductor layer. The values of overlap integrals between different electron wavefunctions in a conduction band of the chirp layer can be less than 0.1 for intersubband transition energies greater than 1.0 eV, and / or the values of overlaps between electron wavefunctions and barrier centers in a conduction band of the chirp layer can be less than 0.4 nm−1, when the structure is biased at an operating potential. The chirp layer can comprise a short-period superlattice with alternating wide bandgap barrier layers and narrow bandgap well layers, wherein the thickness of the barrier layers, or the well layers, or the thickness of both the barrier and well layers changes throughout the chirp layer.

The semiconductor transistor device includes a gate trench structure extending in a vertical direction from a wide bandgap semiconductor body first surface into the wide bandgap semiconductor body, the gate trench structure including a gate trench dielectric and a gate trench electrode. The semiconductor transistor device includes a first conductivity type body region adjoining a first sidewall of the gate trench structure. The first lateral direction is perpendicular to the second lateral direction. The semiconductor transistor device includes a first conductivity type auxiliary structure adjoining a bottom side of the gate trench structure and a second conductivity type drift structure adjoining a bottom side of the body region. The drift structure includes a drift layer arranged in a vertical direction between the bottom side of the auxiliary structure and the second surface of the wide bandgap semiconductor body. In a first location in a second lateral direction, a first sub-region of the drift structure extends from a bottom side of the body region to the drift layer. At a second location in a second lateral direction, the drift structure second sub-region extends from the bottom side of the body region to the top side of the auxiliary structure lateral sub-region.

A semiconductor device includes: a plurality of semiconductor chips spaced apart from one another; and a conductive part. The plurality of semiconductor chips include respective semiconductor switching elements. The conductive part connects the plurality of semiconductor chips in parallel. A material of the semiconductor switching elements of the plurality of semiconductor chips includes a wide bandgap semiconductor. At least one of the semiconductor switching elements has a channel length of 1.5 μm or less.

The invention discloses a wide bandgap semiconductor device, which can be used in the field of semiconductors, and comprises a P-type column region, an N-type column region, a P-type buried layer, a P-type connecting layer, a grid electrode and a source electrode, wherein the P-type column regions and the N-type column regions are alternately arranged along a first direction; the P-type column region, the P-type buried layer, the P-type connecting layer and the source electrode are arranged along a second direction, and the P-type connecting layer is in contact with the source electrode; the first direction is perpendicular to the second direction; the N-type column region, the grid electrode and the source electrode are arranged along a second direction; the P-type buried layers and the P-type connecting layers are discontinuously distributed in a third direction, any P-type buried layer is electrically connected with at least one P-type connecting layer in a three-dimensional space, and any P-type column region is electrically connected with at least one P-type buried layer in the three-dimensional space; the third direction is perpendicular to the first direction and the second direction. Therefore, an electrical connection path of the P-type column region, the P-type buried layer, the P-type connection layer and the source electrode is constructed, and the dynamic resistance loss of the device is effectively reduced.

A high-density multi-level interconnect device for harsh environment applications combines thin-film and thick-film processing technologies to achieve superior performance in extreme conditions. The device comprises an alumina substrate with a thin-film metal layer deposited via electron beam evaporation, including a 20 nm titanium adhesion layer and a 400 nm gold layer, followed by a screen-printed thick-film gold layer. The layers are annealed at 850° C. for 10 minutes to promote strong adhesion. This hybrid approach provides improved die shear strength and enhanced thermal cycling resistance. The interconnects are suitable for wide bandgap semiconductor devices operating at temperatures up to 500° C. in harsh environments including elevated temperature, high pressure, and acidic conditions.

Methods for characterizing semiconductor doping in wide-bandgap semiconductor samples include: measuring an initial value V0 of the surface voltage at a region on the surface of the semiconductor sample in darkness; charging the region to deep depletion in darkness by depositing a specified corona charge at the region; measuring the surface voltage value at the region in darkness after charging; and using a specific photon flux f. eff The light irradiates the charging region, and a specific photon flux f eff A photon energy above the semiconductor bandgap is used, sufficient to generate free minority carriers in the semiconductor sample, thereby causing photoneutralization of the corona charge. The relationship between the photoneutralization-induced corona charge decay and the irradiation time t at the region is monitored using non-contact time-resolved measurements of the surface voltage V(t). The monitored time-resolved surface voltage decay data V(t) is analyzed to determine the photoneutralization time constant τ. ph ; and using a specific photon flux f eff Light neutralization time constant τ ph It serves as a semiconductor doping index, and its value characterizes the semiconductor doping concentration in that region.

A transistor includes a wide bandgap semiconductor layer, a gate electrode, a gate pad, and a gate runner. The gate electrode extends to a region where the gate pad is located and a region where the gate runner is located. The gate pad is connected to the gate electrode. The gate runner is connected to the gate electrode. The gate electrode includes a first region connected to the gate pad, a second region connected to the gate runner, and a third region and a fourth region arranged between the first and second regions in different positions in a first direction. In a cross section perpendicular to the first direction, the gate electrode in the fourth region has a cross-sectional area smaller than that of the gate electrode in the third region.

Systems and methods for laser-based surface processing operations on a wide bandgap semiconductor wafer, such as a silicon carbide semiconductor wafer, are provided. In one example, a method includes removing a wide bandgap semiconductor wafer from a boule using a removal process. The method includes ablating, with one or more lasers, an exposed surface resulting from the removal process to remove material from the exposed surface, wherein ablating, with one or more lasers, the exposed surface reduces a thickness of semiconductor material (e.g., by about 25 microns or greater).

Method for forming a wide bandgap semiconductor device (100), the method comprising: forming a mask pattern for a columnar region (116) over the first surface (1041) of the wide bandgap semiconductor body (104), the mask pattern having an opening that exposes part of a transistor cell area (TCA) of the wide bandgap semiconductor body (104); and forming the columnar region (116), comprising introducing dopants of the first conductivity type through the opening on the first surface (1041) into the transistor cell area (TCA) of the wide bandgap semiconductor body (104) by ion implantation;and then forming a trench-gate mask pattern (120) over a first surface (1041) of a wide-bandgap semiconductor body (104), wherein the trench-gate mask pattern (120) has an opening that exposes the trench-gate region of the transistor cell area (TCA) of the wide-bandgap semiconductor body (104); and etching a trench (102) into the wide-bandgap semiconductor body (104) over the opening in the trench-gate mask pattern (120), wherein the trench (102) extends deeper into the semiconductor body than the columnar region (116);Forming a shielding region (106), comprising introducing dopants of a first conductivity type into the wide bandgap semiconductor body (104) through a bottom and / or a side wall of the trench (102) by ion implantation, wherein the mask pattern (120) for a trench-gate region serves as an ion implantation mask for forming the shielding region (106) and subsequently expanding the trench (102), comprising an expansion process to form a sacrificial oxide (122) lining the side walls and a bottom of the trench (102) by thermal oxidation and removal of the sacrificial oxide (122).

The invention discloses a wide-range neutron measurement method, and belongs to the technical field of neutron detection and measurement, and the method comprises the steps: selecting a wide bandgap semiconductor material, an electrode metal material, a neutron conversion material and a neutron conversion material coating method, obtaining a wide bandgap semiconductor radiation detector coated with the neutron conversion material, and taking the wide bandgap semiconductor radiation detector as a neutron detector; a neutron detector is connected with a pre-amplifier, the pre-amplifier is connected with a rear-end digital sampling circuit, the rear-end digital sampling circuit processes pulse waveforms output by the pre-amplifier, and digital pulse signals are output; processing the digital pulse signal by using a pulse counting method and a Campbell method in upper computer software to obtain a pulse counting rate value and a Campbell value, and calculating neutron fluence rates obtained by the two methods; and obtaining the neutron fluence rate as an output result by adopting different methods according to the size of the neutron fluence rate. According to the invention, a neutron fluence rate measurement system with a small size, high temperature resistance, radiation resistance and a wide range can be obtained, and real-time accurate measurement under the condition of large-range change of the neutron fluence rate is realized.

A power tool includes a motor, a power source, and a printed circuit board ("PCB") electrically connected to the motor and the power source. The PCB is mounted to the motor. The PCB includes a plurality of wide band gap semiconductor switches configured as an inverter for controlling power supplied by the power source to the motor.

The invention relates to the technical field of memristors, in particular to a wide bandgap semiconductor perovskite heterojunction memristor and a preparation method thereof. The memristor comprises a substrate, a wide band gap thin film layer, a perovskite thin film layer and a metal thin film electrode which are sequentially and tightly stacked from bottom to top. The perovskite thin film layer and the wide bandgap thin film layer form a heterojunction; the perovskite thin film layer is made of quasi-two-dimensional metal halide perovskite. The wide bandgap thin film layer is subjected to plasma surface modification, so that the adhesive force and the crystallization quality of the perovskite thin film layer are improved; by adopting a sol-gel method and a thermal evaporation method, excellent crystallinity and gradient switching characteristics are realized, the current level in a high resistance state is reduced, the voltage-current characteristic of the device is improved, and the power consumption is reduced. The heterojunction memristor has the advantages that the heterojunction memristor has a large on-off ratio and has stable retention time and cycle performance.

A gate driver has a turn-on circuit and a turn-off circuit. The turn-on circuit pulls up a gate terminal of a wide bandgap (WBG) semiconductor transistor and turns on the WBG semiconductor transistor in response to a first status of an on-off control signal. The turn-off circuit pulls down the gate terminal of the WBG semiconductor transistor and turns off the WBG semiconductor transistor in response to a second status of the on-off control signal. When the on-off control signal transits to the first status, the turn-on circuit drives the gate terminal of the WBG semiconductor transistor at a first constant driving current, and later switches to a second constant driving current. The second constant driving current is lower than the first constant driving current.

The application discloses a kind of wide band gap semiconductor double-sided heat dissipation module packaging structures based on conductive metal strip, and the semiconductor power chip of different bridge arm is arranged on different power substrate, the volume of module is reduced, and the power density of module is greatly improved;Power gasket is arranged between top and bottom power substrate, and it plays a mechanical support and electrical connection role, provides additional heat dissipation path for each semiconductor power chip on the basis of double-sided heat dissipation, reduces the degree of thermal coupling between chips, achieves chip temperature uniformity effect, while improving chip heat dissipation environment;Driving circuit and commutation circuit are close to vertical in space, and the degree of electromagnetic coupling between circuits is greatly reduced, and the reliability of module is further improved;The conductive metal strip is used in commutation circuit to complete the electrical connection required by chip, and the numerical value of module parasitic inductance is greatly reduced, wherein the hole slot is opened in the connection of source conductive metal strip, which can improve the uniformity of parasitic inductance distribution, and achieve chip current sharing effect.

This invention discloses a method for achieving JTE junction termination in a GaN vertical structure pn diode, belonging to the field of wide bandgap semiconductor materials. The invention involves hydrogen plasma treatment near the etch boundary of the heavily doped p-type GaN layer, causing H ions to form Mg-H complexes with Mg acceptors in the heavily doped p-type GaN layer. Simultaneously, thermal annealing is used to diffuse H ions within the heavily doped p-type GaN, creating a gradually varying hole concentration gradient from the main junction region to the junction edge, thereby achieving JTE junction termination. Compared to existing junction termination technologies, this invention involves no etching, low damage, and effectively weakens the electric field accumulation effect, improving the device's breakdown voltage.

A system and method for determining a single event breakdown voltage for a wide bandgap semiconductor power device. The power device includes an epitaxial layer composed of a wide bandgap semiconductor material such as SiC having a critical energy density. A specific doping level is applied to the epitaxial layer based on a relationship between doping level and the critical energy density to produce a power device with a specific single event breakdown voltage.

The application discloses a wide-bandgap semiconductor module packaging structure based on a planar interconnection, which is electrically connected between wide-bandgap semiconductor chips in the same group in a planar interconnection structure mode and finally connected with a power substrate bottom metal layer, without using a bonding wire, so that the inductance is reduced, the parasitic inductance from the chip to the terminal is greatly balanced through the interconnection mode, and the current sharing capacity of the module is greatly improved; in addition, the metal layer of the power substrate, the power terminal driving terminal and the surface of the planar interconnection structure are all plated with silver, so that the anti-oxidation capacity of the metal in the module under high temperature can be effectively improved, the nano-silver sintering technology is more easily used in the silver-plated surface mode, and the high-temperature resistance of the module is further improved; the wide-bandgap semiconductor module packaging structure has the characteristics of high-temperature resistance, low parasitic inductance and low parasitic inductance imbalance, and is particularly suitable for current sharing of multi-chip in a half-bridge structure, high switching frequency and high working temperature.