330 results about "Avalanche breakdown" patented technology

Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programming, the antifuse transistor is turned on which melts the underlying silicon and causes a permanent reduction in the transistor's resistance. A sensing circuit monitors the resistance of the antifuse transistor and supplies a high or low output signal accordingly. The antifuse transistor may be turned on during programming by raising the voltage at its substrate relative to its source. The substrate may be connected to ground through a resistor. The substrate may be biased by causing current to flow through the resistor. Current may be made to flow through the resistor by inducing avalanche breakdown of the drain-substrate junction or by producing Zener breakdown of external Zener diode circuitry connected to the resistor.

A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region may be located beneath the trench and may be electrically connected to the source region. When the MOSFET is reverse-biased, depletion regions extend from the dielectric sidewall spacers into the “drift” region, shielding the gate oxide from high electric fields and increasing the avalanche breakdown voltage of the device. This permits the drift region to be more heavily doped and reduces the on-resistance of the device. It also allows the use of a thin, 20 Å gate oxide for a power MOSFET that is to be switched with a 1V signal applied to its gate while being able to block over 30V applied across its drain and source electrodes, for example.

A wide band gap semiconductor device is disclosed. A first trench in a gate electrode part and a second trench in a source electrode part (Schottky diode part) are disposed so that the first and second trenches are close to each other while and the second trench is deeper than the first trench. A metal electrode is formed in the second trench to form a Schottky junction on a surface of an n-type drift layer in the bottom of the second trench. Further, a p+-type region is provided in part of the built-in Schottky diode part being in contact with the surface of the n-type drift layer, preferably in the bottom of the second trench. The result is a wide band gap semiconductor device which is small in size and low in on-resistance and loss, and in which electric field concentration applied on a gate insulating film is relaxed to suppress lowering of withstand voltage to thereby increase avalanche breakdown tolerance at turning-off time.

A protection method may prevent a load-mismatch-induced failure in solid-state power amplifiers. In an RF power amplifier, the load voltage standing-wave ratio results in very high voltage peaks at the collector of the final stage and may eventually lead to permanent failure of the power transistor due to avalanche breakdown. The method avoids breakdown by attenuating the input power to the final stage during overvoltage conditions, thus limiting the output collector swing. This is accomplished by a feedback control system, which detects the peak voltage at the output collector node and clamps its value to a given threshold by varying the circuit gain. Indeed, the control loop is unlocked in the nominal condition and it acts when an output mismatching condition is detected. A control circuit also allows a supply-independent collector-clamping threshold to be accurately set.

An optoelectronic device (10) formed in a chip of an indirect bandgap semiconductor material such as silicon is disclosed and claimed. The device comprises a visibly exposed highly doped n+ region (16) embedded at the surface of an oppositely doped epitaxial layer (14), to form a first junction region (15) closed to the surface of the epitaxial layer. When the junction region is reverse biased to beyond avalanche breakdown, the device acts as a light emitting device to the external environment. When it is reversed biased to just below avalanche breakdown it acts as a light detector. The device may further include a further junction region for generating or providing additional carriers in the first junction region, thereby to improve the performance of the device. This further junction can be multiplied to facilitate multi-input processing functions where the light emission from the first junction is a function of the electrical signals applied to the further junctions.

Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programming, the antifuse transistor is turned on which melts the underlying silicon and causes a permanent reduction in the transistor's resistance. A sensing circuit monitors the resistance of the antifuse transistor and supplies a high or low output signal accordingly. The antifuse transistor may be turned on during programming by raising the voltage at its substrate relative to its source. The substrate may be connected to ground through a resistor. The substrate may be biased by causing current to flow through the resistor. Current may be made to flow through the resistor by inducing avalanche breakdown of the drain-substrate junction or by producing Zener breakdown of external Zener diode circuitry connected to the resistor.

The invention provides a direct-current power supply hot plug slow starting control circuit, which comprises a discrete component slow starting circuit, power resistance circuits and a metal oxide semiconductor (MOS) tube drain-source electrode detecting circuit. The power resistance circuits are connected in parallel between MOS tube drain-source electrodes and a drain electrode of the discrete component slow starting circuit. The MOS tube drain-source electrode detecting circuit is connected with the power resistance circuits and the discrete component slow starting circuit and used for detecting voltage values of the power resistance circuits. When the voltage values are in a range of set values, MOS tubes of the power resistance circuits are connected. When the voltage values are beyond the range of set values, the MOS tubes of the power resistance circuits are disconnected. The invention further provides a control method for direct-current power supply hot plug slow starting. The direct-current power supply hot plug slow starting control circuit and the control method can effectively avoid MOS breakdown due to avalanche, simultaneously can effectively reduce voltage stress of the MOS tube drain-source electrodes and facilitates economic selection.

A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region may be located beneath the trench and may be electrically connected to the source region. When the MOSFET is reverse-biased, depletion regions extend from the dielectric sidewall spacers into the “drift” region, shielding the gate oxide from high electric fields and increasing the avalanche breakdown voltage of the device. This permits the drift region to be more heavily doped and reduces the on-resistance of the device. It also allows the use of a thin, 20 Å gate oxide for a power MOSFET that is to be switched with a 1V signal applied to its gate while being able to block over 30V applied across its drain and source electrodes, for example.

A field effect transistor includes an active region and a termination region surrounding the active region. A resistive element is coupled to the termination region, wherein upon occurrence of avalanche breakdown in the termination region an avalanche current starts to flow in the termination region, and the resistive element is configured to induce a portion of the avalanche current to flow through the termination region and a remaining portion of the avalanche current to flow through the active region.

Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).

Provided is a technology, in a semiconductor device having a power MISFET and a Schottky barrier diode on one semiconductor substrate, capable of suppressing a drastic increase in the on-resistance of the power MISFET while making the avalanche breakdown voltage of the Schottky barrier diode greater than that of the power MISFET. In the present invention, two epitaxial layers, one having a high doping concentration and the other having a low doping concentration, are formed over a semiconductor substrate and the boundary between these two epitaxial layers is located in a region equal in depth to or shallower than the bottom portion of a trench.

The invention discloses a test circuit for automatically testing the avalanche voltage of avalanche photodiodes and a method. The test circuit comprises a boost power chip with a current detector and a boost controller for providing bias voltage and current for an avalanche photodiode; a microcontroller with three internal analogue converters for adjusting and sampling the bias voltage and current; four resistance capacitance networks for connecting the internal circuits between the microcontroller and the boost power chip. The three analogue converters of the microcontroller are respectively connected with the feedback input of the boost controller, the bias voltage input of the current detector and the monitor output of the current detector via three resistance capacitance networks. The invention is based on automatic control theory, can automatically adjust safe bias voltage, can judge the avalanche breakdown region by comparing the sampled current value and a preset respected value, and can display the result on a man-machine interface of a microcomputer system, having wide dynamic range, accurate and adjustable output, fast and accurate measurement.

A semiconductor device includes a semiconductor substrate having at least a pn-junction arranged in the semiconductor substrate. At least a field electrode is arranged at least next to a portion of the pn-junction, wherein the field electrode is insulated from the semiconductor substrate. A switching device is electrically connected to the field electrode and adapted to apply selectively and dynamically one of a first electrical potential and a second electrical potential, which is different to the first electrical potential, to the field electrode to alter the avalanche breakdown characteristics of the pn-junction.

Methods and devices are provided for avalanche breakdown in a thin-film solar cell. In one embodiment, a method of breakdown protection assembly comprises providing a single reel of material which is pre-cut in a pattern so that a first portion of the material can be overlapped to a second portion of material to sandwich a breakdown protection device therebetween

A high voltage diamond based switching device capable of sustaining high currents in the on state with a relatively low impedance and a relatively low optical switching flux, and capable of being switched off in the presence of the high voltage being switched. The device includes a diamond body having a Schottky barrier contact, held in reverse bias by the applied voltage to be switched, to an essentially intrinsic diamond layer or portion in the diamond body, a second metal contact, and an optical source or other illuminating or irradiating device such that when the depletion region formed by the Schottky contact to the intrinsic diamond layer is exposed to its radiation charge carriers are generated. Cain in the total number of charge carriers then occurs as a result of these charge carriers accelerating under the field within the intrinsic diamond layer and generating further carriers by assisted avalanche breakdown.

A semiconductor device having high durability against avalanche breakdown is provided. A method for manufacturing a semiconductor device is provided with an IGBT region, a diode region, and a peripheral region includes: forming crystal defects in an n-type region by implanting charged particles into an n-type region in the diode region and an n-type region in the peripheral region; and forming crystal defects in the n-type region by implanting charged particles into an n-type region in the IGBT region and the n-type region in the peripheral region.

The invention discloses a high-gain AlGaN ultraviolet avalanche photodetector which structurally and sequentially comprises components from bottom to up: an AlN template layer, an AlxGal-xN buffer layer, an n type AlxGal-xN layer, an i type AlyGal-yN absorbing layer, an n type AlyGal-yN separating layer, an i type AlyGal-yN multiplication layer, a p type AlzGal-zN layer and a p type GaN layer, wherein an n type ohmic electrode is led out from the n type AlxGal-xN layer, a p type ohmic electrode is led out from the p type GaN layer, x is larger than y, y is larger than z, and z is larger than 0. The invention further discloses a preparation method of the high-gain AlGaN ultraviolet avalanche photodetector. The high-gain AlGaN ultraviolet avalanche photodetector adopting an SAM (security account manager) structure can obviously reduce impressed voltage and dark current during APD (avalanche photodiode) avalanche breakdown, and facilitates the increase of APD avalanche multiplication factors.

A second trench in each source electrode portion (Schottky diode portion) is formed to have a depth equal to or larger than the depth of a first trench in each gate electrode portion. The distance between the first and second trenches is set to be not longer than 10 μm. A source electrode is formed in the second trench and a Schottky junction is formed in the bottom portion of the second trench. In this manner, it is possible to provide a wide band gap semiconductor device which is small-sized, which has low on-resistance and low loss characteristic, in which electric field concentration into a gate insulating film is relaxed to suppress reduction of a withstand voltage, and which has high avalanche breakdown tolerance at turn-off time.

In an LDMOS-SCR ESD protection structure gate voltage of an ESD protection LDSCR is defined by connecting the gate to the source of a reference LDSCR. The reference LDSCR is implemented as a self-triggering device in which the snapback drain-source voltage (avalanche breakdown voltage) is controlled to be lower than that for the major LDSCR by adjusting the RESURF layer-composite overlap for the reference LDSCR to be different to that of the major LDSCR.

Provided is a technology, in a semiconductor device having a power MISFET and a Schottky barrier diode on one semiconductor substrate, capable of suppressing a drastic increase in the on-resistance of the power MISFET while making the avalanche breakdown voltage of the Schottky barrier diode greater than that of the power MISFET. In the present invention, two epitaxial layers, one having a high doping concentration and the other having a low doping concentration, are formed over a semiconductor substrate and the boundary between these two epitaxial layers is located in a region equal in depth to or shallower than the bottom portion of a trench.

A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region may be located beneath the trench and may be electrically connected to the source region. When the MOSFET is reverse-biased, depletion regions extend from the dielectric sidewall spacers into the “drift” region, shielding the gate oxide from high electric fields and increasing the avalanche breakdown voltage of the device. This permits the drift region to be more heavily doped and reduces the on-resistance of the device. It also allows the use of a thin, 20 Å gate oxide for a power MOSFET that is to be switched with a 1V signal applied to its gate while being able to block over 30V applied across its drain and source electrodes, for example.

A double quench circuit for an avalanche current device is provided in which the circuit includes an avalanche current device having a first terminal responsive to a bias voltage to reverse bias the avalanche current device above its avalanche breakdown voltage. A first quench circuit is responsive to the bias voltage and coupled to the first terminal of the avalanche device for reducing the amount of the avalanche current passing through the avalanche device. A second quench circuit is coupled to a second terminal of the avalanche device for reducing the amount of the avalanche current passing through the avalanche device.

A protection method may prevent a load-mismatch-induced failure in solid-state power amplifiers. In an RF power amplifier, the load voltage standing-wave ratio results in very high voltage peaks at the collector of the final stage and may eventually lead to permanent failure of the power transistor due to avalanche breakdown. The method avoids breakdown by attenuating the input power to the final stage during overvoltage conditions, thus limiting the output collector swing. This is accomplished by a feedback control system, which detects the peak voltage at the output collector node and clamps its value to a given threshold by varying the circuit gain. Indeed, the control loop is unlocked in the nominal condition and it acts when an output mismatching condition is detected. A control circuit also allows a supply-independent collector-clamping threshold to be accurately set.

A double quench circuit for an avalanche current device is provided in which the circuit includes an avalanche current device having a first terminal responsive to a bias voltage to reverse bias the avalanche current device above its avalanche breakdown voltage. A first quench circuit is responsive to the bias voltage and coupled to the first terminal of the avalanche device for reducing the amount of the avalanche current passing through the avalanche device. A second quench circuit is coupled to a second terminal of the avalanche device for reducing the amount of the avalanche current passing through the avalanche device.

In order to obtain an on resistance that is as low as possible, it is proposed, in the case of a MOS transistor device, to form the avalanche breakdown region in an end region of a trench structure. As an alternative or in addition, it is proposed to form a region of local maximum dopant concentration of a first conductivity type in the region between a source and a drain in proximity to the gate insulation in a manner remote from the gate electrode.

A semiconductor device includes a semiconductor substrate having at least a pn-junction arranged in the semiconductor substrate. At least a field electrode is arranged at least next to a portion of the pn-junction, wherein the field electrode is insulated from the semiconductor substrate. A switching device is electrically connected to the field electrode and adapted to apply selectively and dynamically one of a first electrical potential and a second electrical potential, which is different to the first electrical potential, to the field electrode to alter the avalanche breakdown characteristics of the pn-junction.

The vertical silicon photomultiplier according to the present invention includes a trench electrode and a PN-junction layer perpendicular to the trench electrode forms and can maximize the quantum efficiency at optical wavelengths, 200˜900 nm in such a way that: it generates electric fields horizontal thereto, by applying a reverse bias voltage to between the trench electrode and the PN junction layer, so that, although ultraviolet light does not reach the PN-junction layer but is incident on the surface, electron-hole pairs can be produced by the horizontally generated electric fields although and an avalanche breakdown can be thus generated, and it allows ultraviolet light, capable of being transmitted to a relatively deep depth, to react with the PN-junction layer.

An integrated power semiconductor device has an isolation structure having two or more isolation trenches, and one or more regions in between the isolation trenches, and a bias arrangement coupled to the regions to divide a voltage across the isolation structure between the isolation trenches. By dividing the voltage, the reverse breakdown voltage characteristics such as voltage level, reliability and stability can be improved for a given area of device, or for a given complexity of device, and avalanche breakdown at weaknesses in isolation structures can be reduced or avoided.

The invention discloses an insulated gate bipolar transistor with a dielectric layer at a collector terminal, belonging to the technical field of power semiconductor devices and power integrated circuits. According to the invention, a continuous or discontinuous dielectric layer is introduced into a region of the terminal collector of a device on the basis of a traditional structure of the insulated gate bipolar transistor. According to the invention, the effective hole emission efficiency in the region of the terminal collector of the device can be significantly reduced due to the dielectric layer introduced, so that the hole injections at the terminal of the device can be reduced. When the device is cut off, the phenomenon of current concentration around an equipotential ring of the terminal of the device can be effectively inhibited due to the reduction of the hole injections in the region of the collector of the terminal, so that the thermal breakdown and the dynamic avalanche breakdown caused by the current concentration can be inhibited and eliminated, the cut-off ability of the insulated gate bipolar transistor can be effectively improved, and the reliability of the device can be improved.

An integrated power semiconductor device has an isolation structure having two or more isolation trenches, and one or more regions in between the isolation trenches, and a bias arrangement coupled to the regions to divide a voltage across the isolation structure between the isolation trenches. By dividing the voltage, the reverse breakdown voltage characteristics such as voltage level, reliability and stability can be improved for a given area of device, or for a given complexity of device, and avalanche breakdown at weaknesses in isolation structures can be reduced or avoided.