112 results about "Avalanche breakdown" patented technology

The invention discloses a super-junction MOSFET device and a preparation method thereof, and belongs to the technical field of semiconductors, and the super-junction MOSFET device comprises a first conduction type substrate and a first conduction type epitaxial layer located on the first conduction type substrate; a cellular region and a terminal region of the device are arranged in the first conductive type epitaxial layer; a plurality of second conductive type columns are longitudinally distributed in a cellular region and a terminal region in the first conductive type epitaxial layer; wherein the plurality of second conductive type columns distributed in the terminal area comprise a plurality of size types, and the second conductive type columns of different size types are alternately arranged. The structural design relieves the strength of a terminal electric field of the device in a reverse withstand voltage state, so that the electric field strength of a terminal region is lower than that of a cellular region, breakdown occurs in the cellular region, the situation that holes are injected into a silicon and silicon dioxide interface, and consequently charges on an oxide layer interface are increased is avoided, the reliability of the device is improved, and the performance of the device is improved. And meanwhile, the avalanche breakdown capability of the device is improved.

The invention discloses a semiconductor device critical breakdown characteristic simulation method based on a hybrid finite volume method. The method comprises the following steps: firstly, carrying out geometric modeling on a device, and carrying out mesh generation; then, the quality of the grids is judged, an FBM method is adopted for the grids with the good quality, and a CVFEM method is adopted for the grids with the poor quality to discretize a drift-diffusion equation set; and then, solving the discrete drift-diffusion equation set system by adopting a full-coupling Newton iteration method, and realizing the optimization of the boost numerical simulation process by adopting an automatic boost strategy and an initial value extrapolation method. And finally, obtaining physical field information of a power semiconductor device (LDMOS) under different external bias voltages, calculating terminal current through a post-processing method, and obtaining an I-V characteristic curve of the device after the avalanche breakdown effect is considered. The method has good numerical calculation precision, numerical stability and grid adaptability, and the complete benchmarking with the solution precision of an international advanced semiconductor simulation tool Sentaur TCAD is realized.

A directed energy firefighting device is disclosed to extinguish fires with light, comprising a structured light generator and a directed energy controller for detecting and extinguishing fires remotely and at the speed of light. The device employs structured directed light energy capable of inducing atmospheric avalanche breakdown, generating at least one of sound waves and shockwaves, and dynamically forming space-time acoustic arrays for precise fire suppression. The system may integrate one or more energy sources, including gyrotrons, traveling wave tubes, klystrons, free electron lasers, and others, to produce diffraction-resistant and dynamically structured beams that penetrate through the atmospheric and non-metalic solid physical obstructions. Key features also may include safety mechanisms and artificial intelligence for real-time optimization. Other applications include power beaming, environmental monitoring, medicine, disaster response, and orbital debris clearing are also discussed. A key feature is the ability for arbitrary manipulation of light over large areas.

The invention provides a trench type field effect transistor and a manufacturing method thereof, and the trench type field effect transistor is provided with a gate trench structure and a source trench structure at one side, deviating from a substrate, of a second conductive type drift region, and the source trench structure is introduced below a source metal layer. A high electric field peak value exists at the bottoms of the gate trench structure and the source trench structure at the same time, and an avalanche breakdown current generated at the bottom of the source trench structure directly flows to the first conduction type ohmic contact region along the source trench, so that the avalanche breakdown current can be reduced without changing the channel density and the voltage endurance capability of the field effect transistor. And the current proportion of the first conduction type body region below the second conduction type source region is reduced, so that the avalanche energy of the field effect transistor is improved.

An electrostatic discharge semiconductor device is disclosed and comprises: a first well region of a first doping type, extending from the surface of an epitaxial layer to the surface of the substrate; a second well region and a third well region of a second doping type; a fourth well region of the second doping type; a fifth well region and a sixth well region have a first doping type; a first injection region and a second injection region, spaced apart in each well region. The second injection region in the second and third well regions is connected to a cathode, and the first and second injection regions in the fourth well region are connected to an anode. The electrostatic discharge semiconductor device enhances its electrostatic protection capability by adjusting the avalanche breakdown voltage between the floating fifth and sixth well regions and the triggering voltage of the device.

The invention relates to an ESD protection device, an ESD protection circuit and a chip. The ESD protection device comprises a substrate; the N well is located in the substrate; the P well is located in the substrate; the first P-type region is positioned in the N well; the N-type region is positioned in the P well; the second P-type region is separated from the first P-type region by the N well; the grid electrode is positioned on the N well between the second P-type region and the first P-type region; wherein the first P-type region, the N well and the grid electrode are used for being connected with an anode, and the N-type region and the P well are used for being connected with a cathode. The trigger voltage of the whole ESD protection device is reduced through avalanche breakdown of the parasitic diode, the SCR and the GDPMOS are ingeniously combined, more discharge current channels are formed, the problem that a traditional GGNMOS multi-finger structure is burnt in advance due to uneven conduction is solved, the discharge current capacity of the device per unit area can be greatly improved, and robustness is high.

The invention belongs to the technical field of high-efficiency rectifier thermal management, and provides a SiC device-based high-efficiency rectifier thermal management method, which comprises the following steps of: acquiring temperature distribution of a SiC device in a high-efficiency rectifier under a full-load condition, and acquiring a transient temperature rise area and a steady temperature rise area by analyzing a temperature change range; the global voltage and the local voltage of the SiC device are collected, whether a global avalanche phenomenon occurs or not is judged by comparing the change rate of the global voltage with a typical value, if yes, a thermal-electric coupling coefficient is calculated through the local voltage and the temperature, an avalanche breakdown source candidate grid area is extracted, and a local avalanche origin point is positioned; determining the specific position of an avalanche breakdown origin point; and outputting a space overlapping degree according to the thermal-electric coupling coefficient and the space overlapping proportion, judging whether transient temperature rise is caused by an avalanche breakdown phenomenon, and if the transient temperature rise is caused by avalanche breakdown, triggering avalanche breakdown protection optimization.

Photoelectric conversion devices and apparatuses are disclosed. An apparatus in which a photoelectric conversion unit is disposed on a semiconductor substrate including a first surface and a second surface on an opposite side of the first surface. The photoelectric conversion unit includes: a first region of a first conductivity type, the first region constituting a part of the first surface and being connected to a detection circuit configured to detect an avalanche breakdown; a second region of the first conductivity type, the second region disposed away from the first region; a third region of a second conductivity type opposite to the first conductivity type, the third region being disposed at a position closer to the second surface than the first region and the second region; and a fourth region disposed between the first region and the second region. The second and third regions serve as avalanche photodiodes. The first region and the second region are configured to be conductive to each other via the fourth region.

This invention discloses a thermoelectric module with intrinsic open-circuit protection and its protection method. The thermoelectric module includes multiple thermoelectric units connected in series and at least one bidirectional protection device. The bidirectional protection device is connected in parallel with at least one of the thermoelectric units and is a semiconductor device with bidirectional avalanche breakdown characteristics. Its breakdown voltage satisfies: where is the normal operating terminal voltage of the thermoelectric unit, α is the absolute value of the Seebeck coefficient, is the maximum design temperature difference, and is the voltage across the faulty unit during an open-circuit fault. During normal operation, the protection device is high-resistance cutoff; during a fault, it avalanche conduction forms a bypass. This invention also provides an open-circuit protection method for the thermoelectric module, including a threshold determination step and a voltage triggering step. This invention achieves hardware-level passive fault tolerance, with fast response speed and high reliability.

The invention discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with asymmetric stepped field oxide. The field oxide structure of the LDMOS device is in an asymmetric step shape, asymmetric coordinated regulation and control of the STI thickness are achieved, the step side expands the field oxide boundary through the gradient, electric field concentration at the STI corner is weakened, breakdown voltage is improved, the inclination angle of the non-step side keeps a thick field oxide area, the electric field peak of the source side is restrained, avalanche breakdown is delayed, and the device performance is improved. And meanwhile, the hot carrier injection risk is reduced. The structure gives consideration to the collaborative optimization of the breakdown capability and the conduction efficiency, is especially suitable for a high-voltage BCD platform with low loss and high reliability requirements, and is a structural innovation scheme with high process compatibility and high design flexibility.

The invention discloses an SPAD photon detection efficiency simulation modeling method. The method comprises the following steps: establishing an SPAD structure model; setting an incident light source; quantum efficiency and avalanche breakdown probabilities under different reverse bias voltages in a depletion region of the SPAD structure model are obtained respectively, and SPAD photon detection efficiency is calculated; and comparing a simulation result with an experiment result, and performing electrical calibration on the SPAD photon detection efficiency parameter model. According to the modeling method disclosed by the invention, the photon detection efficiency of the SPAD under different bias voltages can be obtained, internal physical parameters of the device, such as electric field distribution, breakdown probability and the like, can be obtained along with the variation trend of the bias voltages, a microscopic physical model based on the evolution of the photon detection efficiency is established, and a theoretical support is provided for the design of the high-performance SPAD.

The invention relates to an ESD device with a self-aligned trigger region. A method of forming a semiconductor device includes forming rows of n-type wells and p-type wells in an upper surface of a semiconductor body, the p-type wells and the n-type wells being alternately arranged; a trigger region is formed between the n-type well and the p-type well, the trigger region including a lightly doped partition of the semiconductor body configured to induce a current between the p-type well and the n-type well via avalanche breakdown, where the p-type well and the n-type well are formed by implanting dopant atoms into an upper surface of the semiconductor body, and wherein the lowly doped partitions of the semiconductor body are formed by a hard mask that prevents dopant atoms from penetrating an upper surface of the semiconductor body during implantation of the dopant atoms.

The invention relates to the field of avalanche energy testers, in particular to a power device avalanche energy tester and a testing technology, and the power device avalanche energy tester comprises a supporting table and a case, and the case is arranged on the supporting table; the supporting table is formed by fixedly combining four supporting rods, an upper plate body and a lower plate body, and vertical grooves are formed in the outer sides of the supporting rods. The energy tester is arranged on the supporting table and used for evaluating the energy bearing capacity of the electronic component under the avalanche breakdown condition, and accurate detection of avalanche energy is achieved; the regulation and control part is arranged in the supporting table and is used for carrying out heat exchange treatment on the energy tester, controlling the working temperature of the energy tester and guaranteeing the detection precision and the equipment stability; according to the power device avalanche energy tester and the test process, a circulation heat exchange mechanism is triggered through multi-structure linkage, the equipment temperature is rapidly reduced, the high temperature is prevented from influencing the test precision or damaging the equipment, and stable operation of the equipment is guaranteed.

A vertical junction field effect (JFET) semiconductor device according to some embodiments includes a drift layer, a channel layer on the drift layer, and a plurality of alternating trenches and mesas in the channel layer, wherein a first plurality of the trenches includes gate contact regions. A source metallization is on the mesas. The device includes a second different than the first plurality of trenches, wherein the source metallization is electrically connected to the drift layer at a bottom of the second trench.

The invention provides a GGNMOS device, a manufacturing method and a chip, and belongs to the technical field of semiconductor integrated circuits. The GGNMOS device comprises a substrate, a body region and a substrate interface which are formed on the substrate, and a source region, a drain region and a grid which are formed on the surface of the body region, the substrate interface, the source region and the grid are all grounded, and the GGNMOS device further comprises a deep trench isolation region formed between the substrate interface and the source region; the deep trench isolation region extends towards the bottom of the substrate so as to increase the conduction path length of current from the source region to the substrate interface during avalanche breakdown of the drain region, so that the PN junction between the body region and the source region can reach the PN junction forward turn-on voltage more easily. The size of the turn-on voltage can be controlled by adjusting the depth of the deep trench isolation region, and the turn-on voltage of the GGNMOS device is adjusted under the conditions that the performance of other devices using the body region is not affected and the maintaining voltage of the GGNMOS device is not changed.

A solar power generation system includes photovoltaic (PV) material onto which optically concentrated incident sunlight is transmitted from an optical concentrator during a first series of time intervals, thereby inducing and maintaining a state of continuous electron avalanche in the PV material, the PV material continually generating an electrical current that exceeds an electrical current generated by the PV material in the absence of electron avalanche. The system includes a control means that reduces a temperature of the PV material during a second series of time intervals that alternate with the first series of time intervals to maintain integrity of the PV material while electron avalanche is maintained in the PV material, electron avalanche breakdown is avoided in the PV material, and the PV material continues to generate the electrical current. An electrical load receives the electrical current continually generated by the PV material.

An apparatus in which a photoelectric conversion unit is disposed on a semiconductor substrate including a first surface and a second surface on the opposite side of the first surface includes a first region of a first conductivity type constituting a part of the first surface and connected to a detection circuit configured to detect avalanche breakdown, a second region of the first conductivity type disposed away from the first region, a third region of a second conductivity type opposite to the first conductivity type, the third region disposed at a position closer to the second surface than the first and second regions, and a fourth region disposed between the first and second regions. The second and third regions function as an avalanche photodiode. The first and second regions are configured to be conductive with each other via the fourth region.

The invention provides a micro current and voltage measuring device, which belongs to the field of semiconductor devices, and comprises a collector region, a base region, a central emitter region, a protection ring surrounding the central emitter region, a high-resistance region positioned between the central emitter region and the protection ring, and a quenching resistor, the central emitter region and the collector region can be made of silicon materials, and the base region can be made of germanium-silicon materials; the central emitter region and the base region form an emitter junction, the protection ring and the base region form a protection ring junction, and the collector region and the base region form a collector junction; the center emitter region and the protection ring are heavily doped in the same type, the high-resistance region is a lightly doped region in the same type as the center emitter region, or the high-resistance region is a heavily doped region in the same type as the center emitter region, and the thickness is relatively thin; when the device works, the emitter junction is positively biased, the protection ring junction is reversely biased, and the base region under the protection ring is partially or completely exhausted; the collector junction is reverse biased, and the collector junction operating voltage is greater than its avalanche breakdown voltage. Compared with an existing device, the device can accurately measure smaller electric signals.

The invention provides a single-photon avalanche diode unit and a preparation method, and the single-photon avalanche diode unit comprises a photoelectric effect region which is a region for generating a photoelectric effect. Wherein the photoelectric effect region comprises a depletion region and an oxide filling region; the depletion region is used for absorbing photons and generating carriers, and the carriers in the depletion region are used for triggering avalanche breakdown; the oxide filling region is formed by filling an oxide, and the oxide filling region is a region exceeding the depletion region in the photoelectric effect region; a doped thin layer is arranged at the region junction of the depletion region and the oxide filling region, the polarity of the doped thin layer is the same as that of a target well region, and the target well region is a well region far away from an electrode in the depth direction in a main junction of the single photon avalanche diode unit. According to the technical scheme, the problems of time jitter and delay pulse of the SPAD can be solved.

According to the 4H-SiC MOSFET chip and the main junction region structure and the manufacturing method thereof, the main junction region structure of the 4H-SiC MOSFET chip is characterized in that an N-drift layer is formed on a substrate, a P well is embedded in the N-drift layer, a field oxide layer is arranged on the surface of the P well, the field oxide layer is divided into a plurality of field oxide blocks within the range of the P well, electric field distribution of a transition region is optimized, and the field effect of the N-drift layer is improved; electric field peak intensity is weakened, electric field concentration is avoided, dynamic avalanche breakdown probability is reduced, chip breakdown voltage performance is guaranteed, capacitance distribution of a transition area is adjusted, coupling effect of parasitic gate-drain capacitance is reduced, displacement current is reduced, gate misconduction is avoided, and local temperature rise and stress of the transition area are relieved. The stress transition layer is arranged between the field oxide layer and the P well, thermal expansion and cold contraction differences are reduced, the interface matching performance is improved, the stress transition layer is matched with the field oxide layer, thermal stress concentration can be reduced, the interface crack and stripping risk is remarkably reduced, and the structural stability of the main junction region is improved.

The invention discloses a groove type power device, which comprises a substrate, the substrate is provided with a first surface and a second surface, and the first surface is provided with an interlayer medium; the substrate comprises a terminal region and a cellular region, gate metal is arranged on an interlayer dielectric of the terminal region, and source metal is arranged on an interlayer dielectric of the cellular region; the first surface of the cellular region is provided with a cellular region groove, the first surface of the terminal region is provided with a terminal groove, a gate bus groove is arranged between the terminal groove and the cellular region groove, polycrystalline silicon is respectively arranged in the terminal groove, the cellular region groove and the gate bus groove, the polycrystalline silicon in the gate bus groove is led out and penetrates through the interlayer dielectric to be connected with the gate metal, and the terminal groove is connected with the terminal groove. The first surface of the cellular region is led out and penetrates through the interlayer dielectric to be connected with the source metal; the longitudinal sectional area of the middle of the grid bus groove is larger than that of the two ends of the grid bus groove. By changing the shape of the gate bus groove and optimizing the electric field of the terminal region, an avalanche breakdown point is transferred to the interior of the cellular region, so that the UIS capability of the power device is enhanced.

The utility model discloses a trench isolation structure and a semiconductor device, and relates to the technical field of semiconductors, the trench isolation structure comprises a substrate, the substrate at least comprises a first groove and a second groove, the depth of the first groove is greater than that of the second groove, the groove bottom of the first groove is provided with a first isolator, and the groove bottom of the second groove is provided with a second isolator. A second isolator is arranged at the bottom of the second groove, the distances between the upper surfaces of the first isolator and the second isolator and the upper surface of the base body are equal, and dielectric layers are further arranged on the side walls of the first groove and the second groove. According to the trench isolation structure and the semiconductor device provided by the invention, the avalanche breakdown voltage of the deep trench region can be improved.

A directed energy firefighting device is disclosed to extinguish fires with light, comprising a structured light generator and a directed energy controller for detecting and extinguishing fires remotely and at the speed of light. The device employs structured directed light energy capable of inducing atmospheric avalanche breakdown, generating at least one of sound waves and shockwaves, and dynamically forming space-time acoustic arrays for precise fire suppression. The system may integrate one or more energy sources, including gyrotrons, traveling wave tubes, klystrons, free electron lasers, and others, to produce diffraction-resistant and dynamically structured beams that penetrate through the atmospheric and non-metalic solid physical obstructions. Key features also may include safety mechanisms and artificial intelligence for real-time optimization. Other applications include power beaming, environmental monitoring, medicine, disaster response, and orbital debris clearing are also discussed. A key feature is the ability for arbitrary manipulation of light over large areas.

The application provides a low capacitance electrostatic protection device based on a novel structure and a manufacturing method thereof, which comprises a P-type heavily doped substrate and a P-type epitaxial layer, the P-type epitaxial layer is provided with a matching isolation deep groove, an N-type inversion layer and a P-type heavily doped buried layer, the P-type heavily doped buried layer is arranged around the isolation deep groove and is divided into two parts by the isolation deep groove, the inner part has a length of W3, W3>N-type inversion layer thickness, the lower surface of the P-type heavily doped substrate can be connected with an I / O port 1, the upper surface of the P-type epitaxial layer is provided with an N+ heavily doped active region which can be connected with an I / O port 2, the distance between the N+ heavily doped active region and the inner part of the P-type heavily doped buried layer is W5, the P-type heavily doped buried layer and the N+ heavily doped active region form a PN junction, and the avalanche breakdown voltage of the PN junction can be changed by adjusting W5. The application has the beneficial effect that the electrostatic protection device with super low parasitic capacitance and adjustable breakdown voltage can be realized.

A method, an electronic device, and a computer-readable storage medium are provided. The method includes: obtaining a calibration value of avalanche breakdown voltage of a single-photon avalanche diode array, calibration values of parameters of the single-photon avalanche diode array, and a temperature drift curve of the single-photon avalanche diode array; obtaining temperature of at least two positions of the single-photon avalanche diode array in a circumferential direction according to the calibration value; obtaining a temperature model of the single-photon avalanche diode array according to the temperature of at least two positions; and determining a calibration value of avalanche breakdown voltage of the single-photon avalanche diode array according to the temperature model, the temperature drift curve, and the calibration value of the parameter of the single-photon avalanche diode array and adjusting the input voltage of the single-photon avalanche diode array accordingly.

The invention discloses a thyristor type device junction temperature monitoring circuit and method and a power electronic device, and the circuit comprises a device turn-off module which is connected with a thyristor type device and forms a turn-off branch; the junction temperature monitoring module is used for acquiring an avalanche threshold voltage of the thyristor type device under the condition that the turn-off branch is switched on and the thyristor type device is subjected to avalanche breakdown; the control logic processing module is used for determining the junction temperature value of the thyristor type device based on the first corresponding relation and the avalanche threshold voltage; the first corresponding relation is the corresponding relation between the pre-generated avalanche threshold voltage and the junction temperature. According to the invention, high-precision on-line monitoring of the junction temperature of the thyristor device can be realized.

The application provides a semiconductor structure and a forming method thereof, and the forming method comprises the following steps: providing a substrate; forming a first shallow trench isolation structure in the substrate; forming a drift region in the substrate, the first shallow trench isolation structure is located in the drift region, the drift region comprises a first drift region and a second drift region adjacent to the first drift region, the ion concentration in the first drift region is greater than that in the second drift region, and one side and part of the bottom of the first shallow trench isolation structure are located in the second drift region; forming a gate structure on the surface of the substrate, the gate structure covers the surface of the second drift region and extends to the surface of the part of the first shallow trench isolation structure in the first drift region; the width of the depletion region is increased, the electric field is evenly distributed as much as possible, the difficulty of avalanche breakdown is improved, the breakdown voltage is greatly improved, the quality of the semiconductor structure is improved, and the application range is wide.

The application belongs to the field of photoelectric sensing and optical communication, and relates to a silicon-based light-emitting device, and particularly provides a current multiplication type polycrystalline silicon light-emitting device to solve the problem of low light-emitting efficiency of the existing silicon-based light-emitting device; the application comprises a substrate layer, a polycrystalline silicon layer, an encapsulation layer, a metal positive electrode and a metal negative electrode, the polycrystalline silicon layer is grown on the substrate layer, and is formed by doping to sequentially arrange a P1 region, an N1 region, an Nx region, a Px region, a P2 region and an N2 region from left to right; on the one hand, the structure of the light-emitting device is optimized, on the basis of the reverse-biased diode light-emitting, an additional multiplication current is introduced to accelerate the avalanche breakdown process of the light-emitting device; on the other hand, the doping concentration gradient of the PN junction space charge region is optimized, so that an electric field peak is formed in the space charge region, which is beneficial to the formation of high-energy carriers in the space charge region; the two mechanisms finally significantly improve the light-emitting efficiency of the device.

This application provides a method for fabricating a fast recovery diode, a fast recovery diode, and an electronic device, relating to the field of semiconductor technology. The method for fabricating a fast recovery diode includes: providing a substrate, the substrate including a first surface and a second surface disposed opposite to each other; performing ion doping treatment on the substrate to form ion-doped regions on the first surface and the second surface; etching the first surface based on a predetermined etching region to form a first groove; wherein the depth of the first groove is greater than the thickness of the ion-doped region; the predetermined etching region is located at the center of the first surface; forming a passivation layer in the first groove; and performing metal evaporation on the first surface to form a first metal layer. This method not only reduces the conduction loss of the fast recovery diode, improves energy conversion efficiency, effectively suppresses reverse current, and reduces electromagnetic interference, but also enhances its resistance to avalanche breakdown energy and surge capability.

The invention provides a method and a device for drawing a single avalanche derating characteristic curve of a transistor, and the method comprises the steps: obtaining a plurality of groups of test data, generating a driving parameter according to the test data, so as to drive a test circuit comprising a tested transistor, obtaining an avalanche period waveform of the tested transistor in an avalanche state, performing waveform equivalent processing on the avalanche period waveform to obtain the current avalanche time; determining a real-time junction temperature according to the current avalanche time and the transient thermal resistance curve, adjusting a driving parameter through the real-time junction temperature until the real-time junction temperature meets a preset junction temperature condition, and obtaining a target avalanche time and a target avalanche current, and fitting a single avalanche derating characteristic curve according to the target avalanche time and the target avalanche current corresponding to the multiple groups of test data. According to the drawing method provided by the invention, the junction temperature is calculated based on the transient thermal resistance curve, and the research and development cost is reduced; the circuit is simple, low in maintenance difficulty and less in manual operation; the processing flow is automatic, manual intervention is not needed, and the testing efficiency is improved.