62 results about "Avalanche breakdown" patented technology

An electrostatic discharge semiconductor device is disclosed and comprises: a first well region of a first doping type, extending from the surface of an epitaxial layer to the surface of the substrate; a second well region and a third well region of a second doping type; a fourth well region of the second doping type; a fifth well region and a sixth well region have a first doping type; a first injection region and a second injection region, spaced apart in each well region. The second injection region in the second and third well regions is connected to a cathode, and the first and second injection regions in the fourth well region are connected to an anode. The electrostatic discharge semiconductor device enhances its electrostatic protection capability by adjusting the avalanche breakdown voltage between the floating fifth and sixth well regions and the triggering voltage of the device.

The invention belongs to the technical field of high-efficiency rectifier thermal management, and provides a SiC device-based high-efficiency rectifier thermal management method, which comprises the following steps of: acquiring temperature distribution of a SiC device in a high-efficiency rectifier under a full-load condition, and acquiring a transient temperature rise area and a steady temperature rise area by analyzing a temperature change range; the global voltage and the local voltage of the SiC device are collected, whether a global avalanche phenomenon occurs or not is judged by comparing the change rate of the global voltage with a typical value, if yes, a thermal-electric coupling coefficient is calculated through the local voltage and the temperature, an avalanche breakdown source candidate grid area is extracted, and a local avalanche origin point is positioned; determining the specific position of an avalanche breakdown origin point; and outputting a space overlapping degree according to the thermal-electric coupling coefficient and the space overlapping proportion, judging whether transient temperature rise is caused by an avalanche breakdown phenomenon, and if the transient temperature rise is caused by avalanche breakdown, triggering avalanche breakdown protection optimization.

This invention discloses a thermoelectric module with intrinsic open-circuit protection and its protection method. The thermoelectric module includes multiple thermoelectric units connected in series and at least one bidirectional protection device. The bidirectional protection device is connected in parallel with at least one of the thermoelectric units and is a semiconductor device with bidirectional avalanche breakdown characteristics. Its breakdown voltage satisfies: where is the normal operating terminal voltage of the thermoelectric unit, α is the absolute value of the Seebeck coefficient, is the maximum design temperature difference, and is the voltage across the faulty unit during an open-circuit fault. During normal operation, the protection device is high-resistance cutoff; during a fault, it avalanche conduction forms a bypass. This invention also provides an open-circuit protection method for the thermoelectric module, including a threshold determination step and a voltage triggering step. This invention achieves hardware-level passive fault tolerance, with fast response speed and high reliability.

The invention relates to an ESD device with a self-aligned trigger region. A method of forming a semiconductor device includes forming rows of n-type wells and p-type wells in an upper surface of a semiconductor body, the p-type wells and the n-type wells being alternately arranged; a trigger region is formed between the n-type well and the p-type well, the trigger region including a lightly doped partition of the semiconductor body configured to induce a current between the p-type well and the n-type well via avalanche breakdown, where the p-type well and the n-type well are formed by implanting dopant atoms into an upper surface of the semiconductor body, and wherein the lowly doped partitions of the semiconductor body are formed by a hard mask that prevents dopant atoms from penetrating an upper surface of the semiconductor body during implantation of the dopant atoms.

The invention relates to the field of avalanche energy testers, in particular to a power device avalanche energy tester and a testing technology, and the power device avalanche energy tester comprises a supporting table and a case, and the case is arranged on the supporting table; the supporting table is formed by fixedly combining four supporting rods, an upper plate body and a lower plate body, and vertical grooves are formed in the outer sides of the supporting rods. The energy tester is arranged on the supporting table and used for evaluating the energy bearing capacity of the electronic component under the avalanche breakdown condition, and accurate detection of avalanche energy is achieved; the regulation and control part is arranged in the supporting table and is used for carrying out heat exchange treatment on the energy tester, controlling the working temperature of the energy tester and guaranteeing the detection precision and the equipment stability; according to the power device avalanche energy tester and the test process, a circulation heat exchange mechanism is triggered through multi-structure linkage, the equipment temperature is rapidly reduced, the high temperature is prevented from influencing the test precision or damaging the equipment, and stable operation of the equipment is guaranteed.

A vertical junction field effect (JFET) semiconductor device according to some embodiments includes a drift layer, a channel layer on the drift layer, and a plurality of alternating trenches and mesas in the channel layer, wherein a first plurality of the trenches includes gate contact regions. A source metallization is on the mesas. The device includes a second different than the first plurality of trenches, wherein the source metallization is electrically connected to the drift layer at a bottom of the second trench.

The invention provides a GGNMOS device, a manufacturing method and a chip, and belongs to the technical field of semiconductor integrated circuits. The GGNMOS device comprises a substrate, a body region and a substrate interface which are formed on the substrate, and a source region, a drain region and a grid which are formed on the surface of the body region, the substrate interface, the source region and the grid are all grounded, and the GGNMOS device further comprises a deep trench isolation region formed between the substrate interface and the source region; the deep trench isolation region extends towards the bottom of the substrate so as to increase the conduction path length of current from the source region to the substrate interface during avalanche breakdown of the drain region, so that the PN junction between the body region and the source region can reach the PN junction forward turn-on voltage more easily. The size of the turn-on voltage can be controlled by adjusting the depth of the deep trench isolation region, and the turn-on voltage of the GGNMOS device is adjusted under the conditions that the performance of other devices using the body region is not affected and the maintaining voltage of the GGNMOS device is not changed.

The invention provides a micro current and voltage measuring device, which belongs to the field of semiconductor devices, and comprises a collector region, a base region, a central emitter region, a protection ring surrounding the central emitter region, a high-resistance region positioned between the central emitter region and the protection ring, and a quenching resistor, the central emitter region and the collector region can be made of silicon materials, and the base region can be made of germanium-silicon materials; the central emitter region and the base region form an emitter junction, the protection ring and the base region form a protection ring junction, and the collector region and the base region form a collector junction; the center emitter region and the protection ring are heavily doped in the same type, the high-resistance region is a lightly doped region in the same type as the center emitter region, or the high-resistance region is a heavily doped region in the same type as the center emitter region, and the thickness is relatively thin; when the device works, the emitter junction is positively biased, the protection ring junction is reversely biased, and the base region under the protection ring is partially or completely exhausted; the collector junction is reverse biased, and the collector junction operating voltage is greater than its avalanche breakdown voltage. Compared with an existing device, the device can accurately measure smaller electric signals.

The invention provides a single-photon avalanche diode unit and a preparation method, and the single-photon avalanche diode unit comprises a photoelectric effect region which is a region for generating a photoelectric effect. Wherein the photoelectric effect region comprises a depletion region and an oxide filling region; the depletion region is used for absorbing photons and generating carriers, and the carriers in the depletion region are used for triggering avalanche breakdown; the oxide filling region is formed by filling an oxide, and the oxide filling region is a region exceeding the depletion region in the photoelectric effect region; a doped thin layer is arranged at the region junction of the depletion region and the oxide filling region, the polarity of the doped thin layer is the same as that of a target well region, and the target well region is a well region far away from an electrode in the depth direction in a main junction of the single photon avalanche diode unit. According to the technical scheme, the problems of time jitter and delay pulse of the SPAD can be solved.

According to the 4H-SiC MOSFET chip and the main junction region structure and the manufacturing method thereof, the main junction region structure of the 4H-SiC MOSFET chip is characterized in that an N-drift layer is formed on a substrate, a P well is embedded in the N-drift layer, a field oxide layer is arranged on the surface of the P well, the field oxide layer is divided into a plurality of field oxide blocks within the range of the P well, electric field distribution of a transition region is optimized, and the field effect of the N-drift layer is improved; electric field peak intensity is weakened, electric field concentration is avoided, dynamic avalanche breakdown probability is reduced, chip breakdown voltage performance is guaranteed, capacitance distribution of a transition area is adjusted, coupling effect of parasitic gate-drain capacitance is reduced, displacement current is reduced, gate misconduction is avoided, and local temperature rise and stress of the transition area are relieved. The stress transition layer is arranged between the field oxide layer and the P well, thermal expansion and cold contraction differences are reduced, the interface matching performance is improved, the stress transition layer is matched with the field oxide layer, thermal stress concentration can be reduced, the interface crack and stripping risk is remarkably reduced, and the structural stability of the main junction region is improved.

The application provides a low capacitance electrostatic protection device based on a novel structure and a manufacturing method thereof, which comprises a P-type heavily doped substrate and a P-type epitaxial layer, the P-type epitaxial layer is provided with a matching isolation deep groove, an N-type inversion layer and a P-type heavily doped buried layer, the P-type heavily doped buried layer is arranged around the isolation deep groove and is divided into two parts by the isolation deep groove, the inner part has a length of W3, W3>N-type inversion layer thickness, the lower surface of the P-type heavily doped substrate can be connected with an I / O port 1, the upper surface of the P-type epitaxial layer is provided with an N+ heavily doped active region which can be connected with an I / O port 2, the distance between the N+ heavily doped active region and the inner part of the P-type heavily doped buried layer is W5, the P-type heavily doped buried layer and the N+ heavily doped active region form a PN junction, and the avalanche breakdown voltage of the PN junction can be changed by adjusting W5. The application has the beneficial effect that the electrostatic protection device with super low parasitic capacitance and adjustable breakdown voltage can be realized.

A method, an electronic device, and a computer-readable storage medium are provided. The method includes: obtaining a calibration value of avalanche breakdown voltage of a single-photon avalanche diode array, calibration values of parameters of the single-photon avalanche diode array, and a temperature drift curve of the single-photon avalanche diode array; obtaining temperature of at least two positions of the single-photon avalanche diode array in a circumferential direction according to the calibration value; obtaining a temperature model of the single-photon avalanche diode array according to the temperature of at least two positions; and determining a calibration value of avalanche breakdown voltage of the single-photon avalanche diode array according to the temperature model, the temperature drift curve, and the calibration value of the parameter of the single-photon avalanche diode array and adjusting the input voltage of the single-photon avalanche diode array accordingly.

The invention discloses a thyristor type device junction temperature monitoring circuit and method and a power electronic device, and the circuit comprises a device turn-off module which is connected with a thyristor type device and forms a turn-off branch; the junction temperature monitoring module is used for acquiring an avalanche threshold voltage of the thyristor type device under the condition that the turn-off branch is switched on and the thyristor type device is subjected to avalanche breakdown; the control logic processing module is used for determining the junction temperature value of the thyristor type device based on the first corresponding relation and the avalanche threshold voltage; the first corresponding relation is the corresponding relation between the pre-generated avalanche threshold voltage and the junction temperature. According to the invention, high-precision on-line monitoring of the junction temperature of the thyristor device can be realized.

The application provides a semiconductor structure and a forming method thereof, and the forming method comprises the following steps: providing a substrate; forming a first shallow trench isolation structure in the substrate; forming a drift region in the substrate, the first shallow trench isolation structure is located in the drift region, the drift region comprises a first drift region and a second drift region adjacent to the first drift region, the ion concentration in the first drift region is greater than that in the second drift region, and one side and part of the bottom of the first shallow trench isolation structure are located in the second drift region; forming a gate structure on the surface of the substrate, the gate structure covers the surface of the second drift region and extends to the surface of the part of the first shallow trench isolation structure in the first drift region; the width of the depletion region is increased, the electric field is evenly distributed as much as possible, the difficulty of avalanche breakdown is improved, the breakdown voltage is greatly improved, the quality of the semiconductor structure is improved, and the application range is wide.

The application belongs to the field of photoelectric sensing and optical communication, and relates to a silicon-based light-emitting device, and particularly provides a current multiplication type polycrystalline silicon light-emitting device to solve the problem of low light-emitting efficiency of the existing silicon-based light-emitting device; the application comprises a substrate layer, a polycrystalline silicon layer, an encapsulation layer, a metal positive electrode and a metal negative electrode, the polycrystalline silicon layer is grown on the substrate layer, and is formed by doping to sequentially arrange a P1 region, an N1 region, an Nx region, a Px region, a P2 region and an N2 region from left to right; on the one hand, the structure of the light-emitting device is optimized, on the basis of the reverse-biased diode light-emitting, an additional multiplication current is introduced to accelerate the avalanche breakdown process of the light-emitting device; on the other hand, the doping concentration gradient of the PN junction space charge region is optimized, so that an electric field peak is formed in the space charge region, which is beneficial to the formation of high-energy carriers in the space charge region; the two mechanisms finally significantly improve the light-emitting efficiency of the device.

This application provides a method for fabricating a fast recovery diode, a fast recovery diode, and an electronic device, relating to the field of semiconductor technology. The method for fabricating a fast recovery diode includes: providing a substrate, the substrate including a first surface and a second surface disposed opposite to each other; performing ion doping treatment on the substrate to form ion-doped regions on the first surface and the second surface; etching the first surface based on a predetermined etching region to form a first groove; wherein the depth of the first groove is greater than the thickness of the ion-doped region; the predetermined etching region is located at the center of the first surface; forming a passivation layer in the first groove; and performing metal evaporation on the first surface to form a first metal layer. This method not only reduces the conduction loss of the fast recovery diode, improves energy conversion efficiency, effectively suppresses reverse current, and reduces electromagnetic interference, but also enhances its resistance to avalanche breakdown energy and surge capability.

The invention provides a method and a device for drawing a single avalanche derating characteristic curve of a transistor, and the method comprises the steps: obtaining a plurality of groups of test data, generating a driving parameter according to the test data, so as to drive a test circuit comprising a tested transistor, obtaining an avalanche period waveform of the tested transistor in an avalanche state, performing waveform equivalent processing on the avalanche period waveform to obtain the current avalanche time; determining a real-time junction temperature according to the current avalanche time and the transient thermal resistance curve, adjusting a driving parameter through the real-time junction temperature until the real-time junction temperature meets a preset junction temperature condition, and obtaining a target avalanche time and a target avalanche current, and fitting a single avalanche derating characteristic curve according to the target avalanche time and the target avalanche current corresponding to the multiple groups of test data. According to the drawing method provided by the invention, the junction temperature is calculated based on the transient thermal resistance curve, and the research and development cost is reduced; the circuit is simple, low in maintenance difficulty and less in manual operation; the processing flow is automatic, manual intervention is not needed, and the testing efficiency is improved.

The application provides a transient voltage suppressor based on path decoupling and electric field coupling triggering and a manufacturing method thereof. The transient voltage suppressor comprises at least one device unit. The device unit comprises a first electrode and a second electrode, a triggering unit, a main turn-on unit and a coupling unit. The triggering unit comprises a second-conductivity high-doped region and a first-conductivity high-doped region. A local PN junction region is formed between the second-conductivity high-doped region and a first-conductivity low-doped drift region, and the first-conductivity high-doped region is arranged on a coupling dielectric layer. When the local PN junction region is subjected to avalanche breakdown, displacement current is formed through the coupling dielectric layer and coupled to the main turn-on unit, thereby triggering the main turn-on unit to form a longitudinal low-resistance main turn-on path. The main turn-on unit is in a high-resistance state under a static bias condition, so that the static equivalent junction capacitance of the device is mainly determined by the local PN junction region, thereby balancing low junction capacitance, low dynamic resistance and high surge current bearing capacity.

To provide a semiconductor device in which avalanche breakdown is suppressed by suppressing increase in on-resistance.SOLUTION: The semiconductor device 100 according to the embodiment includes an N-type drift region 10, a P-type base region 41 on the N-type drift region 10, an N-type source region 42 on the P-type base region 41, a gate electrode 23 disposed on the P-type base region 41 via a gate insulating film 22, a source trench (ST) 31 provided on the P-type base region 41, and an N-type polysilicon electrode 33 electrically connected to the P-type base region 41 and the N-type source region 42 and provided in the source trench (ST) 31.SELECTED DRAWING: Figure 2

Provision of a semiconductor device (RC-IGBT) comprising an IGBT area and a diode area that prevents the element from being destroyed due to current concentration at the time of an avalanche breakdown under high voltage application.In a part of a region of a p-type (second conductivity type) anode layer (117) in a diode region (103) that is in contact with an n-type (first conductivity type) drift layer (101), a p-type high concentration region (129) (high concentration region of the second conductivity type) is formed with a higher concentration than the p-type (second conductivity type) anode layer (117), and in a section of the n-type (first conductivity type) drift layer (101) that is in contact with the p-type high concentration region (129) (high concentration region of the second conductivity type), an n-type high concentration region (130) (high concentration region of the first conductivity type) is formed with a higher concentration than the n-type (first conductivity type) drift layer (101).

A semiconductor device includes a semiconductor layer having an active region. The semiconductor layer has a first conductivity type. The semiconductor device further includes a plurality of alternating mesa stripes and trenches in the active region, a source metal layer electrically connected with the plurality of mesa stripes, an isolation ring adjacent the active region, the isolation ring having a second conductivity type opposite the first conductivity type, and a doped region in the semiconductor layer, wherein the isolation ring is between the active region and the doped region, the doped region having the second conductivity type and forming a P-N junction with the semiconductor layer. The source metal layer is electrically connected with the doped region.

The application discloses a low-noise and low-working-voltage microwave diode and a preparation method thereof, and the microwave diode is a vertical heterojunction structure composed of indium selenide (InSe) and black phosphorus (BP). The traditional material for preparing an impact ionization avalanche transit time (IMPATT) microwave diode is replaced by the two-dimensional material BP, and a ballistic avalanche mechanism unique to the BP, that is, a scattering-free quantum coherent transport avalanche mode, so that the IMPATT microwave diode in the application is obviously lower than a traditional avalanche device in terms of avalanche noise, and the avalanche threshold voltage is 2-3 orders of magnitude lower than that of the traditional device. In addition, the bipolarity of the BP makes it unnecessary to chemically dope the material when the IMPATT diode is prepared, thereby reducing the preparation difficulty of the device. Compared with the IMPATT diode prepared from the traditional material, the IMPATT diode in the application not only has lower avalanche noise and avalanche breakdown voltage, but also is simple to prepare, thereby greatly improving the working performance of the device.

The application discloses a semiconductor device and an electronic device. The semiconductor device comprises a first electrode, an active region and a second electrode which are sequentially stacked. The active region comprises a first doped structure, a second doped structure and a third doped structure which are stacked in a direction away from the first electrode. The first doped structure and the third doped structure are doped with a first conductive type, and the second doped structure is doped with a second conductive type. The second doped structure comprises a drift layer. At least one of the first electrode and the second electrode is provided with a relief window which is arranged through the thickness of the electrode. The active region can receive light through the relief window to form photo-generated carriers. According to the application, the semiconductor device can realize light-triggered avalanche breakdown. By adjusting the triggering relationship between the voltage and the external light, the semiconductor device can realize active degradation protection in the electronic device.

An electrostatic discharge semiconductor device and a manufacturing method thereof are disclosed. The electrostatic discharge semiconductor device includes: a substrate, an epitaxial layer and a first well region; a second well region and a third well region located on sides of the first well region respectively; a fourth well region extending in the first well region; fifth and sixth well regions on sides of the fourth well region; a first injection region and a second injection region. The second injection region in the second well region and third well region, and the first injection region in the fifth well region and sixth well region are connected to a cathode, and all injection regions in the fourth well region are connected to an anode, to form a lateral triode current discharge path, which increases the holding voltage and adjusts the avalanche breakdown voltage and trigger voltage, and enhances electrostatic protection capability.

A method of forming a semiconductor device includes forming a row of n-type wells and p-type wells in an upper surface of a semiconductor body, the p-type wells arranged alternatingly with the n-type wells, forming trigger regions in between the n-type wells and the p-type wells, the trigger regions including a low-doped section of the semiconductor body that is configured to induce current flow between the p-type wells and the n-type wells via avalanche breakdown, wherein the p-type wells and the n-type wells are formed by implanting dopant atoms into the upper surface of the semiconductor body, and wherein the low-doped section of the semiconductor body is formed by a hardmask that prevents the dopant atoms from penetrating the upper surface of the semiconductor body during the implanting of the dopant atoms.

The utility model relates to the technical field of driving circuits, and discloses a constant-voltage alternating-current signal source generating circuit and combustion equipment, and the circuit comprises a voltage conversion module, a filtering module, a rectification module, a voltage stabilization module and a feedback module. Therefore, the constant-voltage alternating-current signal source generating circuit is provided with the voltage stabilizing module, the first alternating-current voltage signal output by the voltage conversion module charges the charging capacitor of the voltage stabilizing module after being rectified by the rectifying module, and voltage division is realized through the first resistor and the second resistor of the voltage stabilizing module; and voltage feedback of the voltage conversion module is realized through a voltage stabilizing tube of the voltage stabilizing module and the feedback module. Specifically, in the charging process of the charging capacitor by the power supply conversion module, when the charging voltage of the charging capacitor reaches a set voltage value, the voltage-regulator tube is subjected to avalanche breakdown and is fed back to the voltage conversion module through the feedback module, the peak value of a first alternating current signal output by the voltage conversion module is limited, and stable constant-voltage alternating current signal output is realized.

The invention provides a super junction structure parameter optimization method and apparatus, a terminal device and a storage medium. The method comprises the steps of establishing a temperature dependence model of each physical parameter in a super junction structure; wherein the temperature dependence model is used for describing the change rule of the physical parameters along with the temperature; establishing constraint conditions according to a planar junction theory and an avalanche breakdown principle; wherein the constraint conditions comprise a collision ionization integral breakdown condition and a buffer layer boundary condition; obtaining target information based on the design target of the super junction structure; wherein the target information comprises breakdown voltage, depth-to-width ratio and temperature; solving a performance parameter optimization value of the super junction structure under the target information according to the temperature dependence model and the constraint condition; wherein the performance parameters comprise depletion layer thickness, doping concentration and specific on-resistance. According to the method, the optimization calculation of the performance parameters of the super junction structure can be realized in a larger temperature range.

A semiconductor device includes an active region comprising first and second mesa stripes and a trench between the mesa stripes. The trench has a first width between the first and second mesa stripes near a central portion of the first and second mesa stripes and a second width between the first and second mesa stripes near end portions of the first and second mesa stripes. The second width is less than the first width.

The present invention provides a semiconductor device (RC-IGBT) having an IGBT region and a diode region which prevent current concentration and element breakage when avalanche breakdown is applied under high voltage. A p-type high-concentration region (129) (second-conductivity-type high-concentration region) having a higher concentration than that of a p-type (second-conductivity-type) anode layer (117) is formed in a portion of a region of the p-type (second-conductivity-type) anode layer (117) in a diode region (103) that is in contact with an n-type (first-conductivity-type) drift layer (101). In a portion of an n-type (first conductivity type) drift layer (101) in contact with a p-type high-concentration region (129) (second conductivity type high-concentration region), an n-type high-concentration region (130) (first conductivity type high-concentration region) having a higher concentration than the n-type (first conductivity type) drift layer (101) is formed.

The application provides a micro-current and voltage measuring device, belonging to the field of semiconductor devices, comprising a collector region, a base region, a central emitter region, a guard ring surrounding the central emitter region, a high-resistance region between the central emitter region and the guard ring, and a quenching resistor; the central emitter region and the collector region can be silicon materials, and the base region can be a germanium-silicon material; the central emitter region and the base region form an emitter junction, the guard ring and the base region form a guard ring junction, and the collector region and the base region form a collector junction; the central emitter region and the guard ring are homotypically heavily doped, the high-resistance region is a homotypically lightly doped region of the central emitter region, or the high-resistance region is a homotypically heavily doped region of the central emitter region and is relatively thin; during operation of the device, the emitter junction is forward biased, the guard ring junction is reverse biased, and the base region under the guard ring is partially or completely depleted; the collector junction is reverse biased, and the working voltage of the collector junction is greater than the avalanche breakdown voltage thereof. Compared with existing devices, the device of the application can accurately measure smaller electrical signals.