31 results about "Avalanche breakdown" patented technology

This invention discloses a thermoelectric module with intrinsic open-circuit protection and its protection method. The thermoelectric module includes multiple thermoelectric units connected in series and at least one bidirectional protection device. The bidirectional protection device is connected in parallel with at least one of the thermoelectric units and is a semiconductor device with bidirectional avalanche breakdown characteristics. Its breakdown voltage satisfies: where is the normal operating terminal voltage of the thermoelectric unit, α is the absolute value of the Seebeck coefficient, is the maximum design temperature difference, and is the voltage across the faulty unit during an open-circuit fault. During normal operation, the protection device is high-resistance cutoff; during a fault, it avalanche conduction forms a bypass. This invention also provides an open-circuit protection method for the thermoelectric module, including a threshold determination step and a voltage triggering step. This invention achieves hardware-level passive fault tolerance, with fast response speed and high reliability.

The invention relates to an ESD device with a self-aligned trigger region. A method of forming a semiconductor device includes forming rows of n-type wells and p-type wells in an upper surface of a semiconductor body, the p-type wells and the n-type wells being alternately arranged; a trigger region is formed between the n-type well and the p-type well, the trigger region including a lightly doped partition of the semiconductor body configured to induce a current between the p-type well and the n-type well via avalanche breakdown, where the p-type well and the n-type well are formed by implanting dopant atoms into an upper surface of the semiconductor body, and wherein the lowly doped partitions of the semiconductor body are formed by a hard mask that prevents dopant atoms from penetrating an upper surface of the semiconductor body during implantation of the dopant atoms.

The invention relates to the field of avalanche energy testers, in particular to a power device avalanche energy tester and a testing technology, and the power device avalanche energy tester comprises a supporting table and a case, and the case is arranged on the supporting table; the supporting table is formed by fixedly combining four supporting rods, an upper plate body and a lower plate body, and vertical grooves are formed in the outer sides of the supporting rods. The energy tester is arranged on the supporting table and used for evaluating the energy bearing capacity of the electronic component under the avalanche breakdown condition, and accurate detection of avalanche energy is achieved; the regulation and control part is arranged in the supporting table and is used for carrying out heat exchange treatment on the energy tester, controlling the working temperature of the energy tester and guaranteeing the detection precision and the equipment stability; according to the power device avalanche energy tester and the test process, a circulation heat exchange mechanism is triggered through multi-structure linkage, the equipment temperature is rapidly reduced, the high temperature is prevented from influencing the test precision or damaging the equipment, and stable operation of the equipment is guaranteed.

A vertical junction field effect (JFET) semiconductor device according to some embodiments includes a drift layer, a channel layer on the drift layer, and a plurality of alternating trenches and mesas in the channel layer, wherein a first plurality of the trenches includes gate contact regions. A source metallization is on the mesas. The device includes a second different than the first plurality of trenches, wherein the source metallization is electrically connected to the drift layer at a bottom of the second trench.

The invention provides a micro current and voltage measuring device, which belongs to the field of semiconductor devices, and comprises a collector region, a base region, a central emitter region, a protection ring surrounding the central emitter region, a high-resistance region positioned between the central emitter region and the protection ring, and a quenching resistor, the central emitter region and the collector region can be made of silicon materials, and the base region can be made of germanium-silicon materials; the central emitter region and the base region form an emitter junction, the protection ring and the base region form a protection ring junction, and the collector region and the base region form a collector junction; the center emitter region and the protection ring are heavily doped in the same type, the high-resistance region is a lightly doped region in the same type as the center emitter region, or the high-resistance region is a heavily doped region in the same type as the center emitter region, and the thickness is relatively thin; when the device works, the emitter junction is positively biased, the protection ring junction is reversely biased, and the base region under the protection ring is partially or completely exhausted; the collector junction is reverse biased, and the collector junction operating voltage is greater than its avalanche breakdown voltage. Compared with an existing device, the device can accurately measure smaller electric signals.

The invention provides a single-photon avalanche diode unit and a preparation method, and the single-photon avalanche diode unit comprises a photoelectric effect region which is a region for generating a photoelectric effect. Wherein the photoelectric effect region comprises a depletion region and an oxide filling region; the depletion region is used for absorbing photons and generating carriers, and the carriers in the depletion region are used for triggering avalanche breakdown; the oxide filling region is formed by filling an oxide, and the oxide filling region is a region exceeding the depletion region in the photoelectric effect region; a doped thin layer is arranged at the region junction of the depletion region and the oxide filling region, the polarity of the doped thin layer is the same as that of a target well region, and the target well region is a well region far away from an electrode in the depth direction in a main junction of the single photon avalanche diode unit. According to the technical scheme, the problems of time jitter and delay pulse of the SPAD can be solved.

According to the 4H-SiC MOSFET chip and the main junction region structure and the manufacturing method thereof, the main junction region structure of the 4H-SiC MOSFET chip is characterized in that an N-drift layer is formed on a substrate, a P well is embedded in the N-drift layer, a field oxide layer is arranged on the surface of the P well, the field oxide layer is divided into a plurality of field oxide blocks within the range of the P well, electric field distribution of a transition region is optimized, and the field effect of the N-drift layer is improved; electric field peak intensity is weakened, electric field concentration is avoided, dynamic avalanche breakdown probability is reduced, chip breakdown voltage performance is guaranteed, capacitance distribution of a transition area is adjusted, coupling effect of parasitic gate-drain capacitance is reduced, displacement current is reduced, gate misconduction is avoided, and local temperature rise and stress of the transition area are relieved. The stress transition layer is arranged between the field oxide layer and the P well, thermal expansion and cold contraction differences are reduced, the interface matching performance is improved, the stress transition layer is matched with the field oxide layer, thermal stress concentration can be reduced, the interface crack and stripping risk is remarkably reduced, and the structural stability of the main junction region is improved.

The application provides a low capacitance electrostatic protection device based on a novel structure and a manufacturing method thereof, which comprises a P-type heavily doped substrate and a P-type epitaxial layer, the P-type epitaxial layer is provided with a matching isolation deep groove, an N-type inversion layer and a P-type heavily doped buried layer, the P-type heavily doped buried layer is arranged around the isolation deep groove and is divided into two parts by the isolation deep groove, the inner part has a length of W3, W3>N-type inversion layer thickness, the lower surface of the P-type heavily doped substrate can be connected with an I / O port 1, the upper surface of the P-type epitaxial layer is provided with an N+ heavily doped active region which can be connected with an I / O port 2, the distance between the N+ heavily doped active region and the inner part of the P-type heavily doped buried layer is W5, the P-type heavily doped buried layer and the N+ heavily doped active region form a PN junction, and the avalanche breakdown voltage of the PN junction can be changed by adjusting W5. The application has the beneficial effect that the electrostatic protection device with super low parasitic capacitance and adjustable breakdown voltage can be realized.

The application belongs to the field of photoelectric sensing and optical communication, and relates to a silicon-based light-emitting device, and particularly provides a current multiplication type polycrystalline silicon light-emitting device to solve the problem of low light-emitting efficiency of the existing silicon-based light-emitting device; the application comprises a substrate layer, a polycrystalline silicon layer, an encapsulation layer, a metal positive electrode and a metal negative electrode, the polycrystalline silicon layer is grown on the substrate layer, and is formed by doping to sequentially arrange a P1 region, an N1 region, an Nx region, a Px region, a P2 region and an N2 region from left to right; on the one hand, the structure of the light-emitting device is optimized, on the basis of the reverse-biased diode light-emitting, an additional multiplication current is introduced to accelerate the avalanche breakdown process of the light-emitting device; on the other hand, the doping concentration gradient of the PN junction space charge region is optimized, so that an electric field peak is formed in the space charge region, which is beneficial to the formation of high-energy carriers in the space charge region; the two mechanisms finally significantly improve the light-emitting efficiency of the device.

This application provides a method for fabricating a fast recovery diode, a fast recovery diode, and an electronic device, relating to the field of semiconductor technology. The method for fabricating a fast recovery diode includes: providing a substrate, the substrate including a first surface and a second surface disposed opposite to each other; performing ion doping treatment on the substrate to form ion-doped regions on the first surface and the second surface; etching the first surface based on a predetermined etching region to form a first groove; wherein the depth of the first groove is greater than the thickness of the ion-doped region; the predetermined etching region is located at the center of the first surface; forming a passivation layer in the first groove; and performing metal evaporation on the first surface to form a first metal layer. This method not only reduces the conduction loss of the fast recovery diode, improves energy conversion efficiency, effectively suppresses reverse current, and reduces electromagnetic interference, but also enhances its resistance to avalanche breakdown energy and surge capability.

The invention provides a method and a device for drawing a single avalanche derating characteristic curve of a transistor, and the method comprises the steps: obtaining a plurality of groups of test data, generating a driving parameter according to the test data, so as to drive a test circuit comprising a tested transistor, obtaining an avalanche period waveform of the tested transistor in an avalanche state, performing waveform equivalent processing on the avalanche period waveform to obtain the current avalanche time; determining a real-time junction temperature according to the current avalanche time and the transient thermal resistance curve, adjusting a driving parameter through the real-time junction temperature until the real-time junction temperature meets a preset junction temperature condition, and obtaining a target avalanche time and a target avalanche current, and fitting a single avalanche derating characteristic curve according to the target avalanche time and the target avalanche current corresponding to the multiple groups of test data. According to the drawing method provided by the invention, the junction temperature is calculated based on the transient thermal resistance curve, and the research and development cost is reduced; the circuit is simple, low in maintenance difficulty and less in manual operation; the processing flow is automatic, manual intervention is not needed, and the testing efficiency is improved.

The application provides a transient voltage suppressor based on path decoupling and electric field coupling triggering and a manufacturing method thereof. The transient voltage suppressor comprises at least one device unit. The device unit comprises a first electrode and a second electrode, a triggering unit, a main turn-on unit and a coupling unit. The triggering unit comprises a second-conductivity high-doped region and a first-conductivity high-doped region. A local PN junction region is formed between the second-conductivity high-doped region and a first-conductivity low-doped drift region, and the first-conductivity high-doped region is arranged on a coupling dielectric layer. When the local PN junction region is subjected to avalanche breakdown, displacement current is formed through the coupling dielectric layer and coupled to the main turn-on unit, thereby triggering the main turn-on unit to form a longitudinal low-resistance main turn-on path. The main turn-on unit is in a high-resistance state under a static bias condition, so that the static equivalent junction capacitance of the device is mainly determined by the local PN junction region, thereby balancing low junction capacitance, low dynamic resistance and high surge current bearing capacity.

Provision of a semiconductor device (RC-IGBT) comprising an IGBT area and a diode area that prevents the element from being destroyed due to current concentration at the time of an avalanche breakdown under high voltage application.In a part of a region of a p-type (second conductivity type) anode layer (117) in a diode region (103) that is in contact with an n-type (first conductivity type) drift layer (101), a p-type high concentration region (129) (high concentration region of the second conductivity type) is formed with a higher concentration than the p-type (second conductivity type) anode layer (117), and in a section of the n-type (first conductivity type) drift layer (101) that is in contact with the p-type high concentration region (129) (high concentration region of the second conductivity type), an n-type high concentration region (130) (high concentration region of the first conductivity type) is formed with a higher concentration than the n-type (first conductivity type) drift layer (101).

The application discloses a low-noise and low-working-voltage microwave diode and a preparation method thereof, and the microwave diode is a vertical heterojunction structure composed of indium selenide (InSe) and black phosphorus (BP). The traditional material for preparing an impact ionization avalanche transit time (IMPATT) microwave diode is replaced by the two-dimensional material BP, and a ballistic avalanche mechanism unique to the BP, that is, a scattering-free quantum coherent transport avalanche mode, so that the IMPATT microwave diode in the application is obviously lower than a traditional avalanche device in terms of avalanche noise, and the avalanche threshold voltage is 2-3 orders of magnitude lower than that of the traditional device. In addition, the bipolarity of the BP makes it unnecessary to chemically dope the material when the IMPATT diode is prepared, thereby reducing the preparation difficulty of the device. Compared with the IMPATT diode prepared from the traditional material, the IMPATT diode in the application not only has lower avalanche noise and avalanche breakdown voltage, but also is simple to prepare, thereby greatly improving the working performance of the device.

The application discloses a semiconductor device and an electronic device. The semiconductor device comprises a first electrode, an active region and a second electrode which are sequentially stacked. The active region comprises a first doped structure, a second doped structure and a third doped structure which are stacked in a direction away from the first electrode. The first doped structure and the third doped structure are doped with a first conductive type, and the second doped structure is doped with a second conductive type. The second doped structure comprises a drift layer. At least one of the first electrode and the second electrode is provided with a relief window which is arranged through the thickness of the electrode. The active region can receive light through the relief window to form photo-generated carriers. According to the application, the semiconductor device can realize light-triggered avalanche breakdown. By adjusting the triggering relationship between the voltage and the external light, the semiconductor device can realize active degradation protection in the electronic device.

The utility model relates to the technical field of driving circuits, and discloses a constant-voltage alternating-current signal source generating circuit and combustion equipment, and the circuit comprises a voltage conversion module, a filtering module, a rectification module, a voltage stabilization module and a feedback module. Therefore, the constant-voltage alternating-current signal source generating circuit is provided with the voltage stabilizing module, the first alternating-current voltage signal output by the voltage conversion module charges the charging capacitor of the voltage stabilizing module after being rectified by the rectifying module, and voltage division is realized through the first resistor and the second resistor of the voltage stabilizing module; and voltage feedback of the voltage conversion module is realized through a voltage stabilizing tube of the voltage stabilizing module and the feedback module. Specifically, in the charging process of the charging capacitor by the power supply conversion module, when the charging voltage of the charging capacitor reaches a set voltage value, the voltage-regulator tube is subjected to avalanche breakdown and is fed back to the voltage conversion module through the feedback module, the peak value of a first alternating current signal output by the voltage conversion module is limited, and stable constant-voltage alternating current signal output is realized.

The invention provides a super junction structure parameter optimization method and apparatus, a terminal device and a storage medium. The method comprises the steps of establishing a temperature dependence model of each physical parameter in a super junction structure; wherein the temperature dependence model is used for describing the change rule of the physical parameters along with the temperature; establishing constraint conditions according to a planar junction theory and an avalanche breakdown principle; wherein the constraint conditions comprise a collision ionization integral breakdown condition and a buffer layer boundary condition; obtaining target information based on the design target of the super junction structure; wherein the target information comprises breakdown voltage, depth-to-width ratio and temperature; solving a performance parameter optimization value of the super junction structure under the target information according to the temperature dependence model and the constraint condition; wherein the performance parameters comprise depletion layer thickness, doping concentration and specific on-resistance. According to the method, the optimization calculation of the performance parameters of the super junction structure can be realized in a larger temperature range.

The application provides a micro-current and voltage measuring device, belonging to the field of semiconductor devices, comprising a collector region, a base region, a central emitter region, a guard ring surrounding the central emitter region, a high-resistance region between the central emitter region and the guard ring, and a quenching resistor; the central emitter region and the collector region can be silicon materials, and the base region can be a germanium-silicon material; the central emitter region and the base region form an emitter junction, the guard ring and the base region form a guard ring junction, and the collector region and the base region form a collector junction; the central emitter region and the guard ring are homotypically heavily doped, the high-resistance region is a homotypically lightly doped region of the central emitter region, or the high-resistance region is a homotypically heavily doped region of the central emitter region and is relatively thin; during operation of the device, the emitter junction is forward biased, the guard ring junction is reverse biased, and the base region under the guard ring is partially or completely depleted; the collector junction is reverse biased, and the working voltage of the collector junction is greater than the avalanche breakdown voltage thereof. Compared with existing devices, the device of the application can accurately measure smaller electrical signals.

The invention discloses a medium-wave infrared tellurium-cadmium-mercury avalanche photoelectric detector and a preparation method thereof, and belongs to the technical field of photoelectric detectors, and the device structure comprises a high-Cd-component HgCdTe barrier layer coinciding with a transverse region of a multiplication region and a vertical notch groove located in a longitudinal region of the multiplication region; the preparation method comprises the following steps: growing a HgCdTe epitaxial material containing a barrier layer by adopting a molecular beam epitaxy (MBE) technology, and then performing ion implantation to form an N + metal contact region; by accurately controlling annealing process parameters, an N-multiplication region is generated, and the transverse region of the N-multiplication region is controlled to be diffused to coincide with the HgCdTe barrier layer; and finally, forming a specific longitudinal vertical notch groove in the N-multiplication region. Longitudinal grooves are used for restraining directional flowing of carriers, meanwhile, the high-Cd component barrier layer effectively restrains longitudinal diffusion of the carriers, intrinsic carrier concentration of the carriers is reduced, dark current sources are reduced, sudden increase of dark current before avalanche breakdown is restrained, high-temperature working dark current is reduced, and the high-temperature performance of the detector is improved.

The application belongs to the technical field of high-efficiency rectifier thermal management, and provides a high-efficiency rectifier thermal management method based on SiC devices, which comprises the following steps: collecting the temperature distribution of SiC devices in the high-efficiency rectifier under full load conditions, and obtaining a transient temperature rise area and a steady temperature rise area by analyzing the range of temperature change; collecting the global voltage and the local voltage of the SiC devices, determining whether a global avalanche phenomenon occurs by comparing the global voltage change rate with a typical value, if yes, calculating a thermal-electric coupling coefficient by the local voltage and the temperature, extracting a candidate grid area of the avalanche breakdown source and positioning a local avalanche origin point, and determining the specific position of the avalanche breakdown origin point; outputting a spatial overlap degree according to the thermal-electric coupling coefficient and the spatial overlap proportion, judging whether the transient temperature rise is caused by the avalanche breakdown phenomenon, and triggering avalanche breakdown protection optimization if the avalanche breakdown causes the transient temperature rise.

The invention relates to the technical field of power supply surge protection, and discloses a 1U plug-in maintenance-free power supply surge protection method and protector, and the method comprises the steps: monitoring the terminal voltage of a piezoresistor in real time through a voltage comparator, and triggering clamping discharge within nanosecond response time; a low-resistance discharge channel is formed by utilizing the avalanche breakdown characteristic of the crystal boundary layer of the piezoresistor, surge current is rapidly discharged to a protection ground wire, meanwhile, residual voltage is clamped below a preset limit value, and rear-end load equipment is effectively protected against overvoltage damage.

The invention provides a depletion type metal-oxide-semiconductor field effect transistor (MOSFET) structure with radiation hardening. According to the invention, a traditional polysilicon gate is improved into a separated gate structure; p well buffer layers are introduced below the P well regions on the left side and the right side respectively; and an N-type doped slowly-changing region is introduced between the N + substrate and the N-drift region. According to the invention, the N-type doped slowly-varying region can effectively optimize the longitudinal electric field distribution in the device, alleviate the peak electric field, and inhibit the avalanche breakdown caused by collision ionization, thereby comprehensively improving the single particle resistance of the device; the separation gate structure can effectively prevent a large number of holes from accumulating at the bottom of the central gate oxide layer after heavy ions are incident, and restrain the concentration of an electric field in the gate oxide layer, so that the single event gate penetration (SEGR) resistance of the depletion type MOSFET is remarkably improved; besides, the P-well buffer layer helps to accelerate extraction of transient holes generated by bombardment of radiation particles in the device body, enables the transient holes to flow out of the body rapidly, inhibits starting of a parasitic transistor, and has a good inhibition effect on single event burnout (SEB).

The application discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. The manufacturing method of the semiconductor device comprises the following steps: providing a semiconductor body comprising a first surface and a second surface arranged oppositely; the semiconductor body further comprises a transition first region; forming a groove on the first surface; the transition first region remaining after the groove is formed is used as a first region; the first region is located at the bottom of the groove; a first metal layer is formed on the bottom surface and the sidewall of the groove, and the first metal layer forms an ohmic contact with the first region; a second metal layer is formed on the first surface and the side of the first metal layer away from the groove, and the second metal layer forms a Schottky contact with the semiconductor body. The technical scheme of the application can enhance the avalanche breakdown capability of the device, reduce the forward conduction voltage drop of the device and increase the surge current conduction capability.

The application relates to the field of semiconductor technology and provides a shielded gate power MOSFET structure and a manufacturing method thereof. When an avalanche occurs after the device is turned off, a reverse peak voltage generated by a load inductance is applied to the drain of the device, the withstand voltage is borne by a terminal trench ring, an electric field generated by the trench ring has a repelling effect on avalanche holes, and there are no avalanche holes around the field oxide layer of the terminal trench ring. The direction of an electric field generated by additional N-type polysilicon in the terminal additional trench is from the periphery to the additional N-type polysilicon. Under the condition of the same chip area, the current density of the on-current is increased, the on-resistance is reduced, and the performance of the product is improved due to the fact that there is no region without N+ source area; the avalanche hole current flowing into the source area is reduced, the anti-avalanche breakdown characteristic of the device is improved, the avalanche tolerance EAS is increased, and the reliability of the device is improved by adopting the structure.

The invention provides a control method of a GaN power device with a vertical structure. According to the method, when the GaN power device of a vertical structure is in a normal turn-off state, if drain-source voltage of the GaN power device reaches avalanche breakdown voltage, the GaN power device is controlled to enter an avalanche mode, then, in the avalanche mode, the GaN power device clamps the drain-source voltage within an energy consumption voltage range corresponding to the avalanche breakdown voltage, and the energy consumption voltage of the GaN power device is controlled to be within the energy consumption voltage range corresponding to the avalanche breakdown voltage. According to the technical scheme of the invention, the external heat dissipation operation is carried out through the avalanche current generated by the GaN power device within the energy consumption voltage range, and after the external heat dissipation operation is finished, the GaN power device is controlled to exit the avalanche mode and enter the normal turn-off state, so that the overvoltage protection of the device can be realized without an additional external protection circuit.

The application provides a radiation-hardened IGBT structure and a motor driving system. Compared with a conventional IGBT structure, N+ buffer layers and N++ buffer layers with different doping concentrations and arranged side by side are introduced between an N-drift region and an FS field stop layer; a polysilicon gate is improved into a split gate, and a central P well region is introduced below the polysilicon gate; P well buffer layers are introduced below left, right and central P well regions respectively. The introduced N+ buffer layers and N++ buffer layers can effectively improve the IGBT back electric field distribution and inhibit the avalanche breakdown of the high-low junction composed of the N-drift region and the FS field stop region; the existence of the split gate and the central P well can effectively inhibit the concentration of the electric field in the gate oxide layer; and the P well buffer layer is helpful to accelerate the extraction of the holes generated in the IGBT body by the bombardment of radiation particles and rapidly flow out of the body. The application has good inhibiting effect on single event burnout and single event gate punchthrough.

An avalanche-protected field effect transistor includes, within a semiconductor substrate, a body semiconductor layer and a doped body contact region having a doping of a first conductivity type, and a source region a drain region having a doping of a second conductivity type. A buried first-conductivity-type well may be located within the semiconductor substrate. The buried first-conductivity-type well underlies, and has an areal overlap in a plan view with, the drain region, and is vertically spaced apart from the drain region, and has a higher atomic concentration of dopants of the first conductivity type than the body semiconductor layer. The configuration of the field effect transistor induces more than 90% of impact ionization electrical charges during avalanche breakdown to flow from the source region, to pass through the buried first-conductivity-type well, and to impinge on a bottom surface of the drain region.

The application relates to the technical field of semiconductors, and provides a terminal structure of a shield gate power MOSFET and a manufacturing method thereof. The terminal structure of the shield gate power MOSFET contains a P well region and a region of an N+ source region, and an avalanche tolerance enhancement structure is added on the basis of a conventional shield gate power MOSFET dicing groove region. The avalanche tolerance enhancement structure comprises additional groove field oxide and additional groove polysilicon. By adding an additional terminal groove structure in the dicing groove of a conventional shield gate power MOSFET wafer, the current intensity and the current density of the total avalanche hole current of the source region are reduced, the anti-avalanche breakdown characteristic of the device is improved, the avalanche tolerance EAS is increased, and therefore the reliability of the device is improved; one N+ photoetching is reduced, and the chip circulation time and the chip manufacturing cost are reduced.

The invention provides a silicon controlled electrostatic protection device with low triggering and high maintaining voltage and a preparation method thereof. A layer of P-type injection region is added below a third N + injection region bridged between a first N well and a first P well in an ion injection manner, and an avalanche breakdown surface is transferred to the third N + injection region and the P-type injection region, so that the trigger voltage of the device is reduced; by introducing the GGNMOS structure, after the SCR discharge path of the main path is opened, a shunting path on the surface still exists and is connected with the SCR discharge path in parallel for shunting, so that the maintaining voltage of the device is improved, and the overall robustness of the device is not obviously degraded due to the introduction of the GGNMOS structure. According to the invention, the trigger voltage can be reduced, the maintaining voltage can be increased, and the problem that the device structure is easy to latch due to over-high trigger voltage and over-low maintaining voltage can be avoided. Furthermore, the total finger length of the GGNMOS structure is adjusted by controlling the number of the GGNMOS transistors, and the maintaining voltage of the device can be adjusted.

This application provides an avalanche energy measurement circuit and method thereof. The avalanche energy measurement circuit includes a generating circuit, an integrating circuit, and a calculation circuit. The generating circuit causes the device under test (DUT) to undergo avalanche breakdown, forming a discharge loop between the DUT and the generating circuit. During the discharge loop, the integrating circuit acquires the voltage and current of the DUT, performs a first integral operation on the voltage and current to obtain a first integral result, and performs a second integral operation on the current to obtain a second integral result. After the discharge loop is complete, the calculation circuit calculates the avalanche energy of the DUT based on the energy calculation formula, using the first integral result, the second integral result, and the equivalent resistance of the generating circuit. The second integral result and the equivalent resistance are used to correct the calculation result of the energy calculation formula. This application effectively improves the accuracy of measuring the avalanche energy of the DUT.