476results about How to "Lower on-resistance" patented technology

A silicon carbide semiconductor device capable of achieving a decrease in ON resistance and an increase in breakdown voltage and a method for manufacturing a silicon carbide semiconductor device. A silicon carbide semiconductor device includes a silicon carbide substrate and a drift layer. The drift layer includes a breakdown voltage holding layer extending from a point where a doping concentration has a predetermined value to a surface of the drift layer. The doping concentration in the breakdown voltage holding layer continuously decreases from the point where the doping concentration has the predetermined value to a modulation point located further toward the surface of the drift layer than a midpoint in a film thickness direction of the breakdown voltage holding layer. The doping concentration in the breakdown voltage holding layer continuously increases from the modulation point to the surface of the drift layer.

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

The vertical trench MOSFET comprises: an N type epitaxial region formed on an upper surface of an N⁺ type substrate having a drain electrode on a lower surface thereof; a gate trench extending from a front surface into the N type epitaxial region; a gate electrode positioned in the gate trench so as to interpose an insulator; a channel region formed on the N type epitaxial region; a source region formed on the channel region; a source electrode formed on the source region; a source trench extending from the front surface into the N type epitaxial region; and a trench-buried source electrode positioned in the source trench so as to interpose an insulator, wherein the source electrode contacts with the trench-buried source electrode.

An enhancement mode High Electron Mobility Transistor (HEMT) comprising a p-type nitride layer between the gate and a channel of the HEMT, for reducing an electron population under the gate. The HEMT may also comprise an Aluminum Nitride (AlN) layer between an AlGaN layer and buffer layer of the HEMT to reduce an on resistance of a channel.

A series of gate drive circuits for MESFETs are provided. The gate drive circuits are intended to be used in switching regulators where at least one switching device is an N-channel MESFET. For regulators of this type, the gate drive circuits provide gate drive at the correct voltage to ensure that MESFETs are neither under driven (resulting in incorrect circuit operation) nor over driven (resulting in MESFET damage or excess current or power loss).

In a semiconductor device in which a diode and a high electron mobility transistor are incorporated in the same semiconductor chip, a compound semiconductor layer of the high electron mobility transistor is formed on a main surface (first main surface) of a semiconductor substrate of the diode, and an anode electrode of the diode is electrically connected to an anode region via a conductive material embedded in a via hole (hole) reaching a p⁺ region which is the anode region of the main surface of the semiconductor substrate from a main surface of the compound semiconductor layer.

A MESFET based buck converter includes an N-channel MESFET between a battery or other power source and a node Vx. The node Vx is connected to an output node via an inductor and to ground via a Schottky diode or a second MESFET or both. A control circuit drives the MESFET (and the second MESFET) so that the inductor is alternately connected to the battery and to ground. The maximum voltage impressed across the high side MESFET is optionally clamped by a Zener diode. In some implementations, the MESFET is connected in series with a MOSFET. The MOSFET is switched off during sleep or standby modes to minimize leakage current through the MESFET. The MOSFET is therefore switched at a low frequency compared to the MESFET and does not contribute significantly to switching losses in the converter. In other implementations, more than one MESFET is connected in series with a MOSFET the MOSFETs being switched off during periods of inactivity to suppress leakage currents.

A MOS-gated power semiconductor device is described. The MOS-gated power semiconductor device includes a semiconductor substrate that is heavily doped with impurities of a first conductivity type and used as a collector region, a drift region lightly doped with impurities of a second conductivity type on the substrate, a gate insulating layer on the drift region having a center thicker than its edges, a gate electrode on the gate insulating layer, a well region that is lightly doped with impurities of a first conductivity type on the drift region and that has a channel region overlapping a portion of the gate electrode, an emitter region that is heavily doped with impurities of a second conductivity type and that contacts the channel region, an emitter electrode electrically connected to the emitter region and isolated from the gate electrode, and a collector electrode electrically connected to the semiconductor substrate.

Methods and apparatus for ESD protection of pseudomorphic high electron mobility transistor (pHEMT) circuitry are described. In one method, an ESD surge is detected at a trigger circuit. An ESD protection circuit is triggered. Current flow within the trigger circuit is limited and ESD energy is dispersed to a ground plane via the ESD protection circuit.

A semiconductor device is provided, which is capable of improving mounting flexibility relatively and increasing general versatility, as well as realizing heat radiation characteristics and low on-resistance. Moreover, the semiconductor device is provided, which is capable of improving reliability, performing processing in manufacturing processes easily and reducing manufacturing costs. Also, the semiconductor device capable of decreasing the mounting area is provided. A semiconductor chip in which an IGBT is formed and a semiconductor chip in which a diode is formed are mounted over a die pad. Then, the semiconductor chip and the semiconductor chip are connected by using a clip. The clip is arranged so as not to overlap with bonding pads formed at the semiconductor chip in a flat state. The bonding pads formed at the semiconductor chip are connected to electrodes by using wires.

A semiconductor device includes a field effect transistor formed of a GaN-based compound semiconductor and having a source electrode, a drain electrode, and a gate electrode, and a diode formed of a semiconductor material having a gandgap energy smaller than a bandgap energy of the GaN-based compound semiconductor. A cathode electrode and an anode electrode of the diode are electrically connected to the source electrode and the gate electrode of the field effect transistor, respectively.

A power supply includes a non-isolated DC-DC converter for use in a power source system having a high side switch and a low side switch, in which HEMT or HFET or gallium nitride device with low capacity and low on-resistance is used for the high side switch and a vertical power MOSFET of silicon device with low on-resistance is used for the low side switch.

A technology capable of realizing a MOSFET with low ON-resistance and low feedback capacitance, in which the punch through of a channel layer can be prevented even when the shallow junction of the channel layer is formed in a planar type MOSFET is provided. A P type polysilicon is used for a gate electrode in a planar type MOSFET, in particular, in an N channel DMOSFET.

The invention discloses a lithium battery pack SOC (state of charge) equalization system and a lithium battery pack SOC equalization method. The equalization problems of lithium battery packs are divided into two levels, including intra-group equalization and intergroup equalization. Lithium batteries are divided into a plurality of groups, every lithium battery group is in parallel connection with a bidirectional DC-DC converter, the output ends of the bidirectional DC-DC converters are in series connection to serve as the output ends of a direct-current bus and a power generation system, and loads are in parallel connection. The batteries in every group are connected through bilateral switches and are in parallel connection with by-pass switches so as to be connected dynamically. Intergroup equalization is achieved by distributing output voltage of every group according to average SOC thereof; intra-group equalization can be achieved by controlling dynamic connection of every single battery in every group. The lithium battery pack SOC equalization system and the lithium battery pack SOC equalization method have the advantages that lithium battery pack SOC is equalized without an extra equalization circuit, so that energy transfer among the batteries is avoided, lithium battery pack equalization is achieved automatically in a charge-discharge process, the equalization speed is greatly increased and the equalization efficiency is greatly improved.

A driver circuit includes first to third transistors, a first circuit, and a second circuit. In the first transistor, a first terminal is electrically connected to a second wiring, a second terminal is electrically connected to a first wiring, and a gate is electrically connected to the second circuit and a first terminal of the third transistor. In the second transistor, a first terminal is electrically connected to the first wiring, a second terminal is electrically connected to a sixth wiring, a gate is electrically connected to the first circuit and a gate of the third transistor. A second terminal of the third transistor is electrically connected to the sixth wiring. The first circuit is electrically connected to a third wiring, a fourth wiring, a fifth wiring, and the sixth wiring. The second circuit is electrically connected to the first wiring, the second wiring, and the sixth wiring.

The present invention relates to a low on-resistance RESURF MOS transistor, comprising: a drift region; two isolation regions formed on the drift region; a first-doping-type layer disposed between the two isolation regions; and a second-doping-type layer disposed below the first-doping-type layer.

A high power FET switch comprises an N− drift layer, in which pairs of trenches are recessed to a predetermined depth; oxide side-walls extend to the trench bottoms, and each trench is filled with a conductive material. N+ and metal layers on opposite sides of the drift layer provide drain and source connections for the FET, and the conductive material in each trench is connected together to provide a gate connection. A shallow P region extends across the bottom and around the corners of each trench's side-walls into the drift layer. The application of a sufficient gate voltage causes holes to be injected from the shallow P regions into the N− drift layer, thereby modulating the drift layer's conductivity and lowering the device's on-resistance, and enabling current to flow between the drain and source connections.

The invention discloses a capacitor-clamped three-level dual-buck half-bridge inverter which comprises a first three-level duck circuit, a second three-level duck circuit, a direct-current power-supply input circuit and a load circuit, wherein each three-level duck circuit comprises two power switching tubes, two power diodes, a clamping capacitor and an inductor, and +1, -1 and 0 three-state levels are output by an inverter bridge under the actions of controlling the switching tubes and clamping the clamping capacitor, thereby realizing the three-level dual-buck half-bridge inverter. The invention has the advantages that the advantage that a DBI circuit has not problems of through bridge arms or backward recovery of switching tube body diodes is inherited; the advantage that a three-level convertor per se has small output voltage harmonic content is reserved; compared with a traditional half-bridge inverter, the voltage stress of power devices is reduced; and the whole circuit structure is simpler and easy to realize.

A silicon carbide substrate capable of reducing on-resistance and improving yield of semiconductor devices is made of single-crystal silicon carbide, and sulfur atoms are present in one main surface at a ratio of not less than 60×10¹⁰ atoms/cm² and not more than 2000×10¹⁰ atoms/cm², and oxygen atoms are present in the one main surface at a ratio of not less than 3 at % and not more than 30 at %.

The invention discloses a lithium ion battery pack modularization fast equalization circuit and an equalizing method and belongs to the field of the lithium ion battery pack modularization fast equalization circuit and the equalizing method. The lithium ion battery pack modularization fast equalization circuit and the equalizing method aim at solving the problems that the service life of a whole battery pack is short due to disequilibrium of battery cells, in series connection, in an existing lithium ion battery pack, and an existing ordinary bi-directional equalizer is long in equalizing time. According to the lithium ion battery pack modularization fast equalization circuit and the equalizing method, a lithium ion battery pack is divided into 2N three-cell battery modules, wherein each three-cell battery module is composed of three adjacent lithium ion batteries, the lithium ion battery pack further comprises 2N three-cell equilibrium sub-modules, an equilibrium main module, a switching network, N integration voltage acquisition circuit, a microcontroller, a first energy transmission bus, a second energy transmission bus, a third energy transmission bus and a fourth energy transmission bus, the switching network comprises 2N+1 switches which are M1 to M (2N+1), and the three-cell battery modules and the three-cell equilibrium sub-modules are arranged in a one-to-one corresponding mode. The lithium ion battery pack modularization fast equalization circuit and the equalizing method can be used in a series connection power battery pack.

A semiconductor device 101 in a bi-directional switch includes: a first electrode 109A, a second electrode 109B, a first gate electrode 112A, and a second gate electrode 112B. In a transition period: when the potential of the first electrode 109A is higher than the potential of the second electrode 109B, a voltage lower than the first threshold voltage is applied to the first gate electrode 112A and a voltage higher than the second threshold value voltage is applied to the second gate electrode 112B; and otherwise, a voltage higher than the first threshold value voltage is applied to the first gate electrode, and a voltage lower than the second threshold value voltage is applied to the second gate electrode.

An aspect of the present invention provides a semiconductor device that includes a semiconductor base made of a first semiconductor material of a first conductivity type, a hetero-semiconductor region forming a heterojunction with the semiconductor base and made of a second semiconductor material having a different band gap from the first semiconductor material, a first gate electrode arranged in the vicinity of the heterojunction, a first gate insulating film configured to insulate the first gate electrode from the semiconductor base, a source electrode formed in contact with the hetero-semiconductor region, a dram electrode formed in contact with the semiconductor base, and an electric field extending region partly facing the first gate electrode, the first gate insulating film and hetero-semiconductor region interposed between the electric field extending region and the first gate electrode, the electric field extending region extending a built-in electric field into the hetero-semiconductor region.

In the SiC vertical MOSFET having a low-concentration p-type deposition film provided therein with a channel region and a base region resulting from reverse-implantation to n-type through ion implantation, dielectric breakdown of gate oxide film used to occur at the time of off, thereby preventing a further blocking voltage enhancement. This problem has been resolved by interposing of a low-concentration n-type deposition film between a low-concentration p-type deposition film and a high-concentration gate layer and selectively forming of a base region resulting from reverse-implantation to n-type through ion implantation in the low-concentration p-type deposition film so that the thickness of deposition film between the high-concentration gate layer and each of channel region and gate oxide layer is increased.

In a method for producing an SiC semiconductor device, a p type layer is formed in a trench by epitaxially growing, and is then left only on a bottom portion and ends of the trench by hydrogen etching, thereby to form a p type SiC layer. Thus, the p type SiC layer can be formed without depending on diagonal ion implantation. Since it is not necessary to separately perform the diagonal ion implantation, it is less likely that a production process will be complicated due to transferring into an ion implantation apparatus, and thus manufacturing costs reduce. Since there is no damage due to a defect caused by the ion implantation, it is possible to reduce a drain leakage and to reliably restrict the p type SiC layer from remaining on the side surface of the trench.

A field effect transistor includes a source electrode (30) and a drain electrode (29) formed to be spaced apart from each other on a semiconductor substrate (2), a gate electrode (22) disposed between the source electrode (30) and the drain electrode (29), and a field plate electrode (24, 26) disposed via an insulating film (21) above the semiconductor substrate (2) in a region between the gate electrode (22) and the drain electrode (29), wherein a surface of the semiconductor substrate (2) is flat, and a distance between the semiconductor substrate (2) and the field plate electrode (24, 26) increases according as it goes along a direction from the gate electrode (22) towards the drain electrode (29). With this field effect transistor, the breakdown voltage BVdss is ensured; the chronological change in the set current is restrained; and the on-resistance of an amplifying element is reduced.

The present invention has as an object to provide a FET having low on-resistance. The FET according to the present invention includes: first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a higher band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer; a fourth nitride semiconductor layer formed on the third nitride semiconductor layer and having a higher band gap energy than the third nitride semiconductor layer. A channel is formed in a heterojunction interface between the first nitride semiconductor layer and the second nitride semiconductor layer.

Provided is an agent for dispersing an electrically conductive carbon material, in which the agent consists of a polymer which has an oxazoline group in a side chain and which is obtained by using an oxazoline group-containing monomer such as that represented by formula (1) for example, and in which the agent exhibits excellent dispersion of an electrically conductive carbon material and produces a thin film that exhibits excellent adhesion to a current collection substrate when formed into a thin film together with the electrically conductive carbon material.

(In the formula, X denotes a polymerizable carbon-carbon double bond-containing group, and R¹-R⁴ each independently denote a hydrogen atom, a halogen atom, an alkyl group optionally having a branched structure having 1-5 carbon atoms, an aryl group having 6-20 carbon atoms, or an aralkyl group having 7-20 carbon atoms.)

A MOSFET includes a silicon carbide substrate including a main surface having an off angle of not less than 50° and not more than 65° with respect to a {0001} plane, a buffer layer and a drift layer formed on the main surface, a gate oxide film formed on and in contact with the drift layer, and a p type body region of a p conductivity type formed in the drift layer to include a region in contact with the gate oxide film. The p type body region has a p type impurity density of not less than 5×10¹⁶ cm⁻³.

In a manufacturing method of a semiconductor device, first, a first semiconductor layer, a second semiconductor layer, and a p-type third semiconductor layer are sequentially epitaxially grown on a substrate. After that, the third semiconductor layer is selectively removed. Then, a fourth semiconductor layer is epitaxially grown on the second semiconductor layer. Then, a gate electrode is formed on the third semiconductor layer.