1007 results about "Silicon carbide" patented technology

The invention discloses a method of preparing aluminum oxide-silicon carbide compound porous ceramic by aluminum-silicon industrial waste residues. The primary raw materials comprise industrial waste residues, carbon powder, a pore forming substance and an adhesive. The aluminum oxide-silicon carbide compound porous ceramic is prepared by the following steps of mixing, drying, forming and sintering to obtain a final product. Treatment and high additional value utilization of the industrial waste residues are achieved. The prepared porous ceramic is remarkable in performance, and can be applied to the fields of filtration, sound isolation, heat isolation, fire fighting and the like. The method is simple in process flow and convenient for industrialized promotion; and the cost is good to control and the method has extreme economical value.

A silicon carbide source material structure for use in a sublimation system for growing single crystal silicon carbide is provided. The silicon carbide source material structure may comprise a first layer and a second layer, the first layer being different from the second layer in at least one property.

The invention discloses a preparation process of a sintering kiln silicon carbide guide roller with thermal shock resistance and high-temperature corrosion resistance. The process comprises the following steps: sequentially carrying out surface pretreatment such as reticulate pattern laser engraving, sand blasting and cleaning and drying on a silicon carbide guide roller substrate; performing plasma spraying on a pure aluminum oxide coating after preheating; carrying out segmented laser remelting on the coating to improve the compactness; and finally, coating the nano silicon carbide slurry, calcining and curing. The thermal shock resistance and the high-temperature corrosion resistance of the guide roller are remarkably improved by enhancing the binding force of the coating through laser engraving, optimizing the density of the coating through laser remelting and combining post-treatment of nano silicon carbide slurry, and the service life of the guide roller in a lithium battery positive electrode material sintering kiln is prolonged.

The invention relates to the technical field of gallium nitride transistors, and discloses a silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure, which comprises a silicon carbide device consisting of a plurality of parallel MOS (Metal Oxide Semiconductor) cells and a gallium nitride device consisting of two GaN structures, and is characterized in that the gallium nitride device is positioned on the back surface of the silicon carbide device; each MOS cell comprises a semiconductor epitaxial layer, an MOS source electrode, an MOS grid electrode and an MOS dielectric layer covering the surface of the MOS grid electrode; wherein the semiconductor epitaxial layer comprises an N substrate layer and an N diffusion layer from top to bottom. The transverse high electron mobility characteristic of the GaN HEMT and the longitudinal voltage withstanding advantage of the SiC MOSFET are combined, cooperative work of two wide bandgap semiconductors is achieved on a single substrate, the structure effectively utilizes the excellent heat conduction and voltage withstanding performance of the SiC substrate as a common carrier, meanwhile, through the series voltage withstanding design of the device level, the performance of the device level is improved, and the performance of the device level is improved. And the overall breakdown voltage is obviously improved.

Crystal growth systems for growing crystalline material comprising silicon carbide are provided. In one example, the crystal growth system includes a crucible at least partially defining a crystal growth chamber. The crystal growth chamber has a plurality of zones, each zone associated with a different processing profile. The system includes a silicon carbide crystal. The system includes a source material.

The invention relates to the technical field of silicon carbide semiconductor devices, in particular to an integrally-formed equal-depth double-groove SiC MOSFET structure and a preparation method thereof. According to the structure, an N + buffer layer and an N-drift layer are sequentially formed on an N-type SiC substrate, and a main groove and an auxiliary groove which are consistent in depth are formed in the surface of the N-type SiC substrate; a gate oxide layer and a polycrystalline silicon gate are sequentially formed in the main groove, and the auxiliary groove is filled with a SiC epitaxial material which is doped with the drift layer in the same type, so that a charge compensation and electric field regulation and control unit is formed; the P-type body region surrounds the trench structure and forms an N + source region, and the drain electrode is formed through a back metallization process. Through the collaborative design of the equal-depth double grooves, the uniformization of electric field distribution is realized, the on-resistance and the switching loss are effectively reduced, the thermal stability and the reliability of the device are improved, the integrated process is adopted for integration, the process is simplified, the production efficiency and the yield are improved, and the semiconductor device is suitable for high-frequency and high-voltage application scenes and has a wide industrialization prospect.

In a semiconductor element including a silicon carbide heterostructure, the resistance component generated due to spontaneous polarization at the hetero-matched interface is suppressed, thereby reducing the specific on-resistance of the semiconductor element. A hetero-matched interface (S X ) and 1 × 10 19 cm -3 The tunnel doped region (D T By providing the layer, a carrier transport mechanism by tunneling is realized, and the specific on-resistance of the semiconductor element is kept low.

The invention provides a high-strength winding thin-wall SiC composite cladding tube and a preparation method thereof. A preparation method of a high-strength winding thin-wall SiC composite cladding tube comprises the steps that silicon carbide fibers are wound and laid around a core mold, the winding pre-tightening force is smaller than or equal to 10 N. The winding mode comprises the first mode that one layer of annular winding is conducted firstly, then one layer of spiral winding is conducted, and the number of fiber intersection points in the whole annular direction at a certain position of the outer surface of the core mold is 1. One-layer annular winding is carried out firstly, then two-layer spiral winding is carried out, the number of fiber intersection points in the whole annular direction at a certain position of the outer surface of the core mold is 3, and a prefabricated body is obtained; carrying out a densification deposition process on the preform, wherein the densification deposition process comprises PyC pyrolytic carbon interface deposition, CVI chemical vapor infiltration and CVD chemical vapor deposition; and precise inner circle and outer circle machining is conducted, and the SiC composite cladding pipe is obtained. According to the preparation method disclosed by the invention, through a specific dry winding mode and a densification deposition process, the SiC composite material tube blank is higher in density and better in mechanical property.

The present application relates to high speed, high efficiency SiC power modules. A power converter module includes an active metal brazing (AMB) substrate, a power converter circuit, and an enclosure. The AMB substrate includes an aluminum nitride base layer, a first conductive layer on a first surface of the aluminum nitride base layer, and a second conductive layer on a second surface of the aluminum nitride base layer opposite the first surface. The power converter circuit includes a plurality of silicon carbide switching components coupled to each other via the first conductive layer. The enclosure is disposed over the power converter circuit and the AMB substrate. By using an AMB substrate with an aluminum nitride base layer, thermal dissipation of the power converter module can be significantly improved while maintaining structural integrity of the power converter module.

The invention relates to the technical field of diode detection, and particularly discloses a silicon carbide diode detection device which comprises a box body, a support, an input shaft, a power assembly and a first gear, the support is arranged on the left side of the top end of the box body, and the bottom end of the input shaft is rotatably arranged in the middle of the bottom end of an inner cavity of the box body through a bearing; the power assembly is arranged on the left side of the bottom end of the inner cavity of the box body and used for providing rotation power for the input shaft, and the first gear is connected to the bottom end of the outer wall of the input shaft in a sleeving mode and locked through a jackscrew. The device fills the blank in the aspects of packaging level thermal mechanical reliability acceleration test and service life prediction of the silicon carbide diode in the prior art, and has the remarkable advantages of short test period, real simulated working condition, comprehensive evaluation dimension, safe and reliable operation and the like; and a powerful tool is provided for product research and development, quality control and reliability evaluation of the silicon carbide diode.

The invention belongs to the technical field of power devices, and provides a preparation method of a terminal structure and a chip, an N-type drift region is formed on the front surface of an N-type silicon carbide substrate, a main junction is formed on the N-type drift region, a tail end preset region of the main junction is etched to form a tail groove, so that a first roll angle of the tail groove is smaller than 16 degrees, and a second roll angle of the tail groove is smaller than 16 degrees. The second side wall of the tail trench extends to the edge of the chip, and a field limiting ring region is arranged between the first side of the tail trench and the main junction, so that the terminal length is effectively reduced under the condition of ensuring the voltage resistance of the device by combining the field limiting ring, the junction termination extension region and the trench structure only through a mask process of adding the junction termination extension region and the tail trench; and the area occupation of the chip is reduced.

The invention belongs to the technical field of semiconductor material processing, and relates to a laser modification and low-temperature impact controllable stripping method and system for a single crystal silicon carbide wafer. The method comprises the following steps: pretreating the surface of a single crystal SiC crystal ingot to form a uniform rough surface; setting femtosecond laser initial parameters, and carrying out modification treatment in the crystal ingot to form a modified area; laser parameters are optimized through sweep-frequency optical coherence tomography and a CNN model, and optimal parameters are obtained; inducing to form a modified layer parallel to the surface in the crystal ingot by utilizing the parameters; coating a polymer on the surface of the modified layer and pre-cooling the crystal ingot; and applying a low-temperature impact load to promote the II-type crack to expand along the crystal face so as to realize controllable stripping. The method solves the problem that cracks are difficult to control in the laser stealth cutting technology.

The invention belongs to the technical field of testing and characterization of semiconductor materials, and particularly relates to a lossless characterization method of semiconductor material-based plane dislocation. Comprising the following steps: preparing a to-be-detected semiconductor material, selecting diffraction geometry according to a BPD (Bourysi vector) of the to-be-detected semiconductor material, and enabling a point product result of the diffraction geometry and the Bourysi vector to be not 0; using an X-ray morphology system to calculate corresponding detection parameters according to diffraction geometry to detect the semiconductor material, and imaging the BPD in the detection range; performing statistical analysis on an imaging result to obtain BPD quantity information in a unit area; or BPD length information in a unit volume is obtained, or a tomography imaging result is obtained. According to the method, non-extinction diffraction geometry is selected for accurate recognition and analysis, nondestructive testing of the silicon carbide material base plane dislocation is achieved, full-coverage imaging can be carried out on a large-size sample, and the destructive problem in a traditional characterization means is avoided.

A MOSFET includes a gate electrode and an etching stopper layer formed on a field insulating film of a gate pad region, and an interlayer insulating film formed on the gate electrode and the etching stopper layer. The etching stopper layer is made from a substance having a selectivity of 5.0 or more with respect to etching of the interlayer insulating film and the field insulating film, and is provided at a position farthest from the well contact hole of the under-gate well contact region at least in the gate pad region.

An example power semiconductor device includes a silicon carbide semiconductor structure. The example power semiconductor device includes at least one heterodoped layer in the silicon carbide semiconductor structure. In some implementations, the heterodoped layer includes a first layer having a first dopant concentration of a first conductivity type in a range of about 1×1017 / cm3 to about 2×1021 / cm3. The heterodoped layer includes a second layer having a second dopant concentration of the first conductivity type that is less than the first dopant concentration of the first layer. The semiconductor structure includes a drift region, wherein the drift region has a third dopant concentration of the first conductivity type. The third dopant concentration is less than the first dopant concentration.

The invention discloses a TEC photo-thermal stable thermoelectric power generation device and a preparation method thereof, and relates to the technical field of thermal power generation, and the TEC photo-thermal stable thermoelectric power generation device comprises an energy capture module, a thermoelectric power generation module and a dual-mode heat dissipation module which are sequentially arranged from top to bottom; the energy capture module comprises a silicon substrate with a micro-cone array on the surface, a phase change energy storage buffer dielectric layer coated on the surface of the micro-cone array, and a silicon carbide film layer, a titanium nitride film layer and a titanium nitride nanoparticle layer which are sequentially arranged on the surface of the phase change energy storage buffer dielectric layer; the thermoelectric power generation module comprises a corrugated metal composite substrate and a plurality of thermoelectric units arranged on the surface of the metal composite substrate. The bottleneck that a traditional single material is insufficient in solar spectrum coverage is broken through, the solar energy utilization efficiency is greatly improved, excessive heat generated by sudden change of instantaneous illumination intensity can be effectively absorbed, and continuous and stable heat source input is provided for thermoelectric conversion.

The invention relates to the technical field of reliability testing of semiconductor power devices, and discloses a short-circuit robustness testing method and system based on grid stress degradation of a silicon carbide device, and the method comprises the steps of pre-testing short circuit, grid stress application and post-testing short circuit are continuously executed under the same physical connection by configuring a coupling testing time sequence. The control unit cooperates with the driving unit to generate a static positive and negative bias and dynamic switch stress mode, and cooperates with the power loop auxiliary switch action to simulate different short circuit faults. A dynamic and static index correlation model is established to quantitatively evaluate robustness by collecting transient waveforms and measuring static parameters and calculating short-circuit energy integral, threshold voltage and drift distance of on resistance. According to the invention, the in-situ test of the aging and short-circuit characteristics of the device is realized, the contact resistance change and the loop parasitic parameter difference caused by the repeated disassembly and assembly of the device in the traditional discrete test are eliminated, and the change of the two short-circuit waveforms completely corresponds to the internal degradation of the device caused by the grid stress.

A semiconductor crystal control system for modifying a crystal growth process of silicon carbide is provided. The system can obtain one or more crystal growth parameters associated with growing a semiconductor crystal in a crystal growth assembly. The system can determine, based on the one or more crystal growth parameters, a predicted growth condition. The system can modify a crystal growth process based at least in part on the predicted growth condition.

A silicon carbide semiconductor device includes a drift layer, a channel layer on the drift layer, the channel layer having a first conductivity type, a trench in the channel layer and a mesa adjacent to the trench, and a gate region within the trench. The gate region has a second conductivity type opposite the first conductivity type, and the gate region includes an epitaxially regrown layer. A method of forming a silicon carbide semiconductor device includes providing a drift layer, forming a channel layer on the drift layer, the channel layer having a first conductivity type, etching the channel layer to form a trench in the channel layer and a mesa adjacent to the trench, and epitaxially regrowing a gate region within the trench, wherein the gate region has a second conductivity type opposite the first conductivity type.

The invention provides a silicon carbide epitaxial layer thickness infrared light measurement method and system, a medium and equipment, and relates to the technical field of thickness measurement. Based on a double-beam interference model, considering air-epitaxial layer and epitaxial layer-substrate interface reflection, deducing an optical path difference and a total phase difference, and constructing a general thickness solving model according to a refractive index relationship between an epitaxial layer and a substrate; dividing spectral intervals by adopting a sliding window, calculating the thickness of each interval by utilizing different dispersion models, and distributing weights according to relative standard deviation for weighted fusion to obtain a comprehensive thickness solving model; expanding to a multi-beam interference model, deducing a total reflectivity formula, and analyzing necessary conditions and thickness errors of multi-beam interference; and acquiring a silicon carbide epitaxial wafer to be measured, and building a fitting model by combining an Airy formula and the dispersion model to eliminate errors so as to obtain a thickness measurement result. High-precision and high-reliability non-destructive measurement of the thickness of the silicon carbide epitaxial layer is achieved, and the problems of systematic errors and insufficient result reliability caused by a traditional simplified model are solved.

The invention provides a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with an SCR (Selective Catalytic Reduction) and a manufacturing method thereof, and relates to the technical field of power semiconductor devices, the device is integrated with a PNPN four-layer structure consisting of a P + region, an N-type epitaxial layer, a P-type body region and an N + source region between a grid electrode and a source electrode, and the P + region is in metal ohmic contact with the source electrode. Through collaborative design of the distance and the doping concentration of the P + region and the N + source region, the forward and reverse trigger voltage thresholds of the PNPN structure can be accurately matched with the asymmetric driving window of the electric control main drive. The structure is arranged on the outer edge of a cellular area or a terminal area, and is electrically isolated from an active area, a field plate is arranged to suppress false triggering, ohmic contact is optimized to accelerate turn-off, and it is ensured that holding current is higher than parasitic latch triggering current, so that rapid and reliable discharge and self-protection of bidirectional surge between a gate and a source are achieved on the premise that the performance of a main device is not affected, and the reliability of the device is improved. And the gate oxide reliability is obviously improved.

This invention discloses a novel SM-JTE termination structure for a floating junction silicon carbide power device and its fabrication method. The method includes: providing an N+ substrate; fabricating at least one epitaxial structure on one side surface of the N+ substrate; the epitaxial structure includes: a first N- epitaxial layer, and a floating junction p-region and a JTE region formed by ion implantation on the side surface of the first N- epitaxial layer away from the N+ substrate; growing a second N- epitaxial layer on the side surface of the at least one epitaxial structure away from the N+ substrate, and fabricating a surface termination; growing an oxide layer on the side surface of the second N- epitaxial layer away from the substrate; fabricating a first electrode on the side surface of the second N- epitaxial layer away from the substrate, and fabricating a second electrode on the side surface of the N+ substrate away from the epitaxial structure, with the first electrode in contact with the oxide layer. This invention divides the JTE region into multiple SMJTE structures, which can disperse the single-point electric field peak of the JTE region to these SMJTE structures, thereby reducing the electric field peak and giving the power device stronger dose offset resistance.

The utility model belongs to sulphur sulphuric acid technology field, concretely is a kind of sulphur sulphuric acid sulphur burning furnace waste heat recovery device, including high-temperature flue gas waste heat recovery module, low-temperature tail gas waste heat recovery module, depth purification module and intelligent control module;High-temperature flue gas waste heat recovery module recycles high-temperature flue gas waste heat by honeycomb silicon carbide ceramic heat exchanger and circulating oil circuit;Low-temperature module recycles tail gas waste heat by finned heat exchange unit and jacketed heat exchanger;Depth purification module handles flue gas by SCR denitration, composite filtration and spray absorption;Intelligent control module monitors and regulates each component in real time;The device realizes waste heat cascade recovery and flue gas purification, improves heat utilization rate, avoids pollution.

The disclosure relates to a power device (100), comprising: an n-type doped silicon carbide drift layer (103); a p-type doped well (104); an n-type doped source contact (106); an n-type doped substrate (101) acting as a drain contact; and a composite gate dielectric layer (111, 112) comprising a first dielectric layer (111) contributing to a first gate threshold voltage (V1) of the power device and a second dielectric layer (112) contributing to a second gate threshold voltage (V2) of the power device which is occasionally lower than the first gate threshold voltage (V1). The first dielectric layer (111) is overlapping the n-type doped source contact (106) and a first portion of the p-type doped well (104) to enable formation of a first part of a gate electrons channel (107). The second dielectric layer (112) is arranged above the remaining portion of the p-type doped well (104) to enable formation of the remaining part of the gate electrons channel (107) and thus current conduction through the gate electrons channel (107) in case that the second gate threshold voltage (V2) reaches the first gate threshold voltage (V1).

The invention provides a safe shutdown method and system for a silicon carbide motor controller, and the method comprises the steps: entering a safe shutdown transition mode when a safe shutdown request is received; collecting three-phase current of the motor in real time, and predicting a three-phase current prediction value of the next period based on a sampling value; judging and controlling the conduction state of the silicon carbide power device of the corresponding bridge arm according to the predicted value, so as to guide the current to only flow through the channel and avoid the body diode; judging whether a safe turn-off condition is met or not based on the real-time sampling current value; and when the condition is met, quitting the safe turn-off mode and completely turning off all the power devices. Therefore, through combination of predictive control and real-time verification, the follow current is actively guided to flow through a silicon carbide device channel, the damage problem caused by large follow current of a body diode is fundamentally avoided, the conduction loss and the heating risk are remarkably reduced, and the safety and the reliability of the motor controller in the turn-off process are greatly improved.

This invention discloses a SiC-supported LDH nanocomposite material, its preparation method, and its application as a microwave absorbing and corrosion-resistant material. The SiC-supported LDH nanocomposite material has a core-shell structure, wherein the core is silicon carbide nanowires and the shell is a layered bimetallic hydroxide doped with a third metal. nw The loading of the third metal-doped layered bimetallic hydroxide is 43.1%–168%. This invention improves the microwave absorption performance of the composite material by adjusting the LDH shell content and doping the LDH with cobalt to form a ternary LDH. Furthermore, the core-shell structure of the SiC-loaded LDH nanocomposite not only provides multiple scattering conditions for microwaves but also acts as a physical barrier, extending the corrosion path and acting as a labyrinth effect to hinder the intrusion of corrosive media. Moreover, the LDH memory effect and anion exchange effect further resist chloride ion intrusion, achieving a lightweight, integrated application of microwave absorption and corrosion protection.

To provide an electronic device which effectively solves the problem of delamination of a passivation layer from silicon carbide (SiC) starting from the edge of the device, and to provide a manufacturing process of the electronic device.SOLUTION: The electronic device 50 includes a silicon carbide semiconductor body 50 having a surface 50 a with a first portion of the surface defining an active region 54 of the electronic device, a second portion of the surface external to the active region, metallization 55 extending over the first portion of the surface of the semiconductor body, a passivation layer 56 extending over the metallization, and an adhesive layer 57 based on one or more carbon allotropes extending over the passivation layer.SELECTED DRAWING: Figure 1

The invention relates to the technical field of high-speed generators, and discloses a double-three-phase fractional-slot winding carbon fiber reinforced high-speed generator and a design method.The double-three-phase fractional-slot winding carbon fiber reinforced high-speed generator comprises a permanent magnet synchronous motor, the permanent magnet synchronous motor adopts a double-three-phase winding surface-mounted topology and fractional-slot distribution winding, and a carbon fiber bundle is arranged on the surface of a rotor; the stator winding adopts a split transposition structure and is internally provided with an oil duct; and the controllable rectification controller adopts a three-phase two-level main power conversion topology and comprises a control circuit of a dual-digital signal processor redundancy architecture, a driving circuit of a multi-level driving architecture and a three-phase full-bridge silicon carbide main power circuit adaptive to a high-voltage multi-level topology. By adopting the dual three-phase fractional slot winding surface-mounted permanent magnet synchronous motor topology and cooperating with the split transposition winding structure, the winding circulation loss is reduced, the fault-tolerant capability is improved, and the rotor is bundled and reinforced by carbon fiber wires to counteract the high-speed rotation centrifugal force.

A main semiconductor device element and a temperature sensing section for sensing the temperature of the main semiconductor device element are provided on a semiconductor substrate containing SiC. The temperature sensing section (10) is a lateral pn-junction diode formed in a polysilicon layer (3) and provided on a front surface of a semiconductor substrate (101) by means of an interlayer insulating film (9). A p-type anode region (1) of the temperature sensing section (10) is formed by ion implantation of B or In into the polysilicon layer (3). The temperature sensing section and an n-type cathode region are formed by ion implantation of P or Sb into the polysilicon layer. The sheet resistance of the p-type anode region (1) at 25 °C is not less than 50 Ω / □ but not more than 170 Ω / □.The n-type cathode region (2) exhibits a surface resistance of not less than 80 Ω / □ but not more than 400 Ω / □ at 25 °C. Thus, the temperature sensing accuracy of the temperature sensing section (10) can be improved.