1914 results about "Silicon carbide" patented technology

The invention relates to the technical field of MOS semiconductors, and discloses a variably doped planar gate silicon carbide VDMOS device and a preparation process thereof, the variably doped planar gate silicon carbide VDMOS device comprises a plurality of MOS cells which are parallel to each other, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of a single MOS cell; lateral symmetric P-layers are arranged in the single MOS cell and located on the left side and the right side of the N drift layer, and the section contours of the corresponding sides of the lateral symmetric P-layers on the two sides are in an arc shape. By arranging the lightly doped N layer in the middle of the N drift layer and introducing the arc-shaped laterally-symmetrical P-layers to the two sides, the electric field distribution of the device is optimized, the local electric field concentration is reduced, the breakdown voltage is remarkably improved, and the charge balance capability is enhanced and the leakage current is reduced through the contact between the laterally-symmetrical P-layers and the N substrate layer.

The invention discloses a method of preparing aluminum oxide-silicon carbide compound porous ceramic by aluminum-silicon industrial waste residues. The primary raw materials comprise industrial waste residues, carbon powder, a pore forming substance and an adhesive. The aluminum oxide-silicon carbide compound porous ceramic is prepared by the following steps of mixing, drying, forming and sintering to obtain a final product. Treatment and high additional value utilization of the industrial waste residues are achieved. The prepared porous ceramic is remarkable in performance, and can be applied to the fields of filtration, sound isolation, heat isolation, fire fighting and the like. The method is simple in process flow and convenient for industrialized promotion; and the cost is good to control and the method has extreme economical value.

The invention relates to the technical field of optical engineering, in particular to an AI silicon carbide lens-oriented aspheric laser polishing precision online detection and feedback system. Comprising a detection module; the data processing module is electrically connected with the detection module and used for constructing a lens surface three-dimensional model and calculating polishing precision parameters; the feedback control module is electrically connected with the data processing module, is used for generating a feedback control strategy and comprises a strategy generation unit and a parameter optimization unit; an execution module; and an intelligent learning module. According to the design, a laser measuring head, an energy sensor array and an environment sensor are integrated through the detection module, synchronous acquisition of multi-dimensional data such as surface profile, laser energy distribution and environment parameters is realized, and three-dimensional point cloud data with consistent time and space are generated through multi-modal fusion processing (time domain synchronization, space registration and feature enhancement) of the data preprocessing unit; the physical essence of the polishing process is completely represented, and the detection comprehensiveness and the data relevance are improved.

The invention relates to the field of pressure sensors, in particular to a pressure sensor and a processing method, and a chip comprises a silicon substrate, a silicon dioxide dielectric layer, a device layer, a metal electrode and packaging glass. The device layer comprises a silicon carbide single crystal device layer and a silicon device layer; the silicon carbide single crystal device layer is arranged on the silicon device layer; the silicon device layer, the silicon dioxide dielectric layer and the silicon substrate are connected in sequence; the device layer is etched to form a sensitive resistor device layer, an annular sealing region and a micro-channel; the sensitive resistance device layer is isolated from the annular sealing area through the micro-channel; the device layer, the silicon dioxide dielectric layer and the silicon substrate are etched to form a cross beam etching area; the silicon substrate is etched to form a silicon pressure cavity and a beam film; the metal electrode is arranged on the top of the device layer; and the packaging glass anode is bonded at the top of the device layer or the bottom of the silicon substrate so as to solve the problems of low high temperature resistance and low sensitivity of the MEMS pressure sensor.

The invention discloses a joint test system, a silicon carbide metasurface grating detection method and a silicon carbide metasurface grating detection device, and belongs to the technical field of semiconductor detection. A synergistic excitation signal is generated by regulating a light source and a microwave source and is applied to the silicon carbide metasurface grating to be measured to form a light intensity and microwave field interference pattern. The method comprises the following steps: synchronously acquiring data through multiple channels, constructing a multi-dimensional matrix through time alignment, marker feature extraction and coordinate mapping, extracting defect features to establish a reference model, calculating deviation degree to judge quality, and carrying out abnormal point screening, candidate region construction and coupling verification on a defect grating to divide a potential defect region. For a potential defect area, excitation parameters are dynamically adjusted through a gradient descent algorithm, and defect grades are divided by combining the characteristic defect degree and the area. According to the invention, the problems of insufficient single-mode detection, low multi-mode alignment precision and blind adjustment of excitation parameters are solved, cross-band cooperative detection and intelligent grading are realized, and the detection reliability is improved.

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide thick-bottom oxide layer groove MOS structure and a preparation method thereof, the silicon carbide thick-bottom oxide layer groove MOS structure comprises a plurality of parallel MOS cells, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the lightly doped N layer is arranged in the middle of the N drift layer, the arc-shaped contour design with the inclined top is introduced to the two sides, the injection area is accurately controlled through the photoetching technology, the phenomenon that the edge electric field concentration of the N drift layer is effectively dispersed is effectively dispersed, in this way, electric field distribution is more uniform, breakdown voltage is improved, and local electric field concentration is reduced; moreover, the contact between the laterally symmetrical P-layer and the N substrate layer enhances the charge balance capability, and reduces the leakage current.

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide plane MOS device polysilicon gate self-alignment process and a low resistance structure, the silicon carbide plane MOS device polysilicon gate self-alignment process comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, and the N drift layer comprises a drain electrode, a source electrode and a grid electrode. The height of the P well layer in the single MOS cell is aligned with that of the grid electrode, and the P well layer is located on the left side and the right side of the grid electrode; the N well layer and the P + layer are both located above the grid electrode and the P well layer, and the P + layer is located on the outer side of the N well layer. According to the invention, the height of the P well layer is accurately aligned with the grid electrode, the P well layer is arranged at the two sides of the grid electrode, the design of the T-shaped source electrode is combined, the conduction path is optimized, and when the voltage is applied to the grid electrode, vertical channels are formed at the two sides of the P well layer, so that the path of current flowing from the drain electrode to the source electrode through the N drift layer is shorter and the distribution is uniform.

The invention discloses a silicon carbide TrenchMOS device and a manufacturing method thereof, and belongs to the field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the arc-shaped lightly-doped N layer is additionally arranged in the middle of the arc-shaped heavily-doped N layer, electric field distribution under reverse bias is smoothed through the doping concentration lower than that of the heavily-doped N layer, the interface electric field sudden change risk is reduced, dynamic loss is reduced, meanwhile, the doping concentration of the central area is diluted through the arc-shaped inner side lightly-doped N layer, a depletion area is promoted to be expanded, and the performance of the device is improved. Electric field distribution between drain gates is optimized, and stray capacitance is reduced to improve high-frequency performance.

The invention relates to the technical field of MOS semiconductors, and discloses a heterojunction-based silicon carbide groove type MOSFET device structure and a preparation process thereof.The heterojunction-based silicon carbide groove type MOSFET device structure comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a source electrode, a grid electrode and a semiconductor epitaxial layer, and each semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer; a groove is formed in the upper surface of the single MOS cell and located below the grid electrode, an N + layer is deposited in the groove, and the N + layer comprises a left N + layer and a right N + layer. Through the design of the split type left N + layer and the right N + layer in the groove and the combination of the middle N-layer or the middle P-layer filled in the middle, the electric field concentration phenomenon at the bottom of the groove is effectively dispersed, and the electric field peak value at the edge of the N drift layer is further inhibited in cooperation with the right triangle arrangement of the blocking ion bubbles, so that the breakdown voltage and the reliability of the device are remarkably improved, and the reliability of the device is improved. The method is suitable for high-voltage application scenes.

The invention belongs to the technical field of power devices, and provides a silicon carbide device structure, a preparation method thereof and a chip, a P-type heavily doped region is isolated from a junction field effect transistor region at an adjacent position by a P-type well region, and an N-type heavily doped region is isolated from the junction field effect transistor region at an adjacent position by the P-type well region. The adjacent junction field effect transistor regions are isolated by the P-type well regions, so that a super-junction-like structure is formed, the junction field effect transistor regions can have donor doping with higher doping concentration, corner arrangement is avoided, a depletion region can be completely closed, the on resistance of the device is reduced, and the reliability of the device is improved.

A silicon carbide source material structure for use in a sublimation system for growing single crystal silicon carbide is provided. The silicon carbide source material structure may comprise a first layer and a second layer, the first layer being different from the second layer in at least one property.

The invention discloses a combined passivation back contact battery which comprises an N-type silicon wafer, a second intrinsic amorphous silicon layer, a microcrystalline silicon layer, an anti-reflection layer, a second semiconductor opening region, a first semiconductor opening region and a transition region, the anti-reflection layer is a single-layer amorphous silicon carbonitride layer or a laminated structure composed of an amorphous silicon carbide layer and an amorphous silicon carbonitride layer, and the second semiconductor opening area is composed of a first intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a transparent conductive film and a metal electrode which are sequentially arranged on the back face of the silicon wafer. The first semiconductor opening area is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a transparent conductive film and a metal electrode which are sequentially arranged on the back face of the silicon wafer, and an opening is etched in the transparent conductive film on the surface of the transition area to form an insulation groove. Amorphous silicon carbonitride or amorphous silicon carbide / amorphous silicon carbonitride laminated layers are adopted as the anti-reflection layers, so that reflection loss is reduced, the reliability and durability of the cell are improved, and the conversion efficiency of the cell is improved.

The invention relates to the field of ceramic materials, in particular to a high-temperature-resistant composite ceramic material and a preparation method thereof.The high-temperature-resistant composite ceramic material is prepared from, by weight, 80-100 parts of zirconium oxide, 10-20 parts of silicon carbide, 5-10 parts of aluminum nitride, 1-5 parts of a sintering aid and 5-10 parts of modified silicon powder; the modified silicon powder takes nano silicon powder as a core body, the core body is sequentially coated with a transition metal organic polymer and oxidized asphalt, and the prepared composite ceramic material is good in mechanical strength and excellent in high temperature resistance and has important application value in the field of aerospace.

The invention discloses a junction temperature prediction method based on SiC MOSFET turn-off loss, and belongs to the technical field of power electronics and electricians. The junction temperature prediction method combines a turn-off loss model with a junction temperature prediction model based on turn-off loss, and comprises the following steps: firstly, establishing a SiC MOSFET turn-off loss model considering parasitic parameters, secondly, establishing the junction temperature prediction model based on the SiC MOSFET turn-off loss in an off-line manner, and then, calculating the turn-off loss on line according to the loss model. And finally substituting the loss data into the junction temperature prediction model to obtain a junction temperature prediction value. According to the method, the turn-off loss and the junction temperature of the SiC MOSFET under different working conditions can be predicted, and the method has the advantages of being high in real-time performance, easy to implement, high in model precision and the like; and an efficient and accurate solution is provided for thermal evaluation and junction temperature prediction of the silicon carbide power device.

An improved silicon carbide (SiC) super junction (SJ) MOSFET having at least two buried P-shield (BPS) regions facing each other for gate oxide electric-field and saturation current reductions is disclosed. The two BPS regions are spaced apart from a body region and formed either adjoining sidewalls or below a bottom of a P column region. Moreover, a saturation current pitching (SCP) structure formed in a Junction Field Effect Transistor (JFET) region sandwiched between the two BPS regions limits saturation current of the device in a forward conduction stage for the short-circuit capability improvement.

The invention belongs to the technical field of ceramic materials, and discloses a high-entropy boride composite silicon carbide ceramic with a controllable microstructure and a preparation method and application thereof. The method comprises the following steps: carrying out ball milling, drying and sieving on Zr, Ta, Nb, W, Cr, B4C and SiB6 to obtain mixed powder; the preparation method comprises the following steps: putting a boron carbide powder into a graphite mold of which the inner surface is coated with a BN layer, heating to 1850-2050 DEG C, carrying out SPS sintering, and preparing the high-entropy boride composite silicon carbide ceramic with controllable microstructure under 20-35 MPa and a vacuum degree of 10 Pa, and the molecular formula of the high-entropy boride composite silicon carbide ceramic is (Zr0. 2Ta0. 2Nb0. 2W0. 2Cr0. 2) B2-SiC. The ceramic has good mechanical properties, the hardness at room temperature is 27-32 GPa, the fracture toughness is 4.5-6 MPa.m < 1 / 2 >, the bending strength is 450-600 MPa, and the ceramic can be applied to extreme environments or the field of radiation protection.

The invention relates to a silicon carbide super-junction transverse MOS device and a manufacturing method thereof, and belongs to the technical field of semiconductor devices. The device sequentially comprises a substrate and an epitaxial layer from bottom to top, a p column region is arranged on the outer side of the epitaxial layer, a drain region is arranged on the outer side of the p column region, a p well region is arranged on the inner side of the epitaxial layer, a source region is arranged on the inner side of the p well region, a p + region is arranged on the outer side of the p well region, a groove is formed in the middle of the epitaxial layer, and a gate oxide layer is arranged in the groove. A gate polycrystalline silicon is arranged in the gate oxide layer, source electrode metal is arranged on the upper sides of the source electrode region and the p + region, drain electrode metal is arranged on the upper side of the drain electrode region, a dielectric layer is arranged between the source electrode metal and the drain electrode metal, and top layer metal is arranged at the tops of the source electrode metal and the drain electrode metal. According to the invention, the doping concentration of the drift region can be improved while the withstand voltage of the device is ensured, and higher withstand voltage and lower on resistance of the device are realized.

The invention relates to the technical field of zirconia ceramic sintering, and discloses a zirconia ceramic microwave single-die-cavity rapid sintering system and an intelligent temperature control method.The system comprises a high-temperature-resistant metal cavity, a microwave generation unit, a temperature detection and control unit, a coil base assembly and an auxiliary structure, and centralized control is achieved through an intelligent touch control computer. A microwave single-mode resonance mode is adopted, a silicon carbide wave absorbing layer is used for enhancing microwave absorption, materials are evenly heated from inside to outside, an intelligent temperature control method is used for monitoring the temperature in real time based on a short-wave infrared thermometer, a PI D control algorithm is combined, the power of a magnetron is dynamically adjusted through an adjustable power source, the temperature control precision reaches + / -2 DEG C, and the temperature control precision reaches + / -2 DEG C; the problems of non-uniform temperature, high energy consumption, high rejection rate, long sintering time and the like in a traditional zirconia ceramic sintering process are effectively solved, the production efficiency can be greatly improved, the cost is reduced, the product quality is improved, the equipment also supports multiple process modes, and diversified production requirements are met.

A shield trench power device such as a trench MOSFET or IGBT includes a substrate or an epitaxial layer of silicon, silicon carbide, gallium nitride, or gallium arsenide and employs an in-trench structure including a gate structure and an underlying polysilicon or oxide shield region that contacts a shield region in an epitaxial or crystalline layer of the device. The poly silicon region may be laterally confined by spacers in a gate trench and may contact or be isolated from the underlying shield region. Alternatively, the polysilicon region may be replaced with an insulating region.

The invention belongs to the technical field of bonding chopper and preparation thereof, and particularly relates to a ceramic chopper, a preparation method thereof and application of the ceramic chopper in thermal ultrasonic bonding packaging of a semiconductor integrated circuit. The ceramic chopper provided by the invention is prepared by taking aluminum oxide as a matrix and matching silicon carbide nanofiber, magnesium oxide and yttrium oxide in a certain proportion through ball milling, granulation, molding and high-temperature sintering processes, has the broadband ultrasonic transmission capability of 20-135kHz, and has the maximum amplitude of 3.8 mu m. Experiments show that the chopper can shorten the bonding time by 25%, increase the qualified rate to 99%, increase the shear strength by 20%, and significantly improve the bonding efficiency and reliability. The ceramic chopper disclosed by the invention can well meet the requirements of thermal ultrasonic bonding packaging of a semiconductor integrated circuit on high energy efficiency and high precision bonding, and has a wide industrial application prospect.

The invention relates to the technical field of laser cutting machining, in particular to a cutting device for forge piece machining, which comprises a worktable, a transmission rotating shaft for conveying pipes is mounted at the upper end of the worktable, a first motor is mounted at the rear end of the worktable, and a cleaning mechanism for pretreating the pipes is mounted at the front end of the worktable; a bevel conveying frame is fixedly connected to the rear end of the workbench, a chamfering mechanism used for polishing the round pipe is installed on the inner side of the bevel conveying frame, through the synergistic effect of a heating plate and a friction plate, the heating plate is attached to the curved surface of the pipe in a self-adaptive mode through a second spring, and an oxide layer is heated to the softening temperature; through cooperation with circumferential grinding of a silicon carbide friction plate, the removal rate can reach 98% or above, the problem of scrap residue in traditional dry grinding is avoided, and it is ensured that the two sets of rotating plates clamp the pipe at the synchronous rotating speed through the rotating plate synchronous closing technology and the design of the 1.2-time tooth number ratio of a fourth gear and a fifth gear.

To suppress spurious responses and also suppress degradation of main responses.SOLUTION: An elastic wave device 100 includes: a supporting substrate 10; a piezoelectric layer 14 formed on the supporting substrate 10; a pair of comb-shaped electrodes 20 provided on the piezoelectric layer 14; a first insulation layer 11 formed between the supporting substrate 10 and the piezoelectric layer 14, the first insulation layer being made of one of polycrystal or amorphous oxide aluminum and polycrystal or amorphous polysilicon; and a second insulation layer 12 formed between the first insulating layer 11 and the piezoelectric layer 14, the second insulation layer being made of aluminum nitride, silicon nitride, silicon carbide, or diamond-like carbon and having a first surface 60 adjacent to the first insulation layer 11 and a second surface 61 adjacent to the piezoelectric layer 14, and the first surface being rougher than the second surface.SELECTED DRAWING: Figure 1

The utility model relates to the technical field of single crystal preparation by a liquid phase epitaxy method, in particular to a leading forced convection introducing device for single crystal growth by a resistance heating LPE method, which comprises a graphite crucible and a graphite heating component arranged on the outer side of the graphite crucible, one end of the graphite seed crystal rod extends into the graphite crucible and is connected with the graphite seed crystal support; the seed crystal is adhered to the bottom surface of the graphite seed crystal support; the graphite annular turbofan is arranged in the graphite crucible; the graphite annular turbofan is connected with the graphite seed rod through a jackscrew clamp; the other end of the graphite seed crystal rod is externally connected with a seed crystal lifting and rotating mechanism; and the graphite seed crystal rod drives the seed crystal and the graphite annular turbofan to do lifting and rotating motion. According to the device, the influence of adverse convection on the whole flow field is weakened, and the controllability of the whole flow field can be improved; and meanwhile, an ideal temperature field for growing high-quality silicon carbide crystals in the growth cavity is ensured.

The invention relates to a SiC crystal ingot facet detection method based on Raman combined with resistivity detection, which comprises the following steps: S1, providing a silicon carbide workpiece, acquiring resistivity rho k of different detection areas on the surface layer of the workpiece based on a preset resistivity detection scanning path, and further preliminarily screening out resistivity abnormal areas; s2, on the basis of a preset Raman detection scanning path, obtaining the edge area on the surface layer of the workpiece, the Raman characteristic peak frequency omega ij of different detection points of the resistivity abnormal area obtained in the S1, a detection image, and an XY coordinate position on an XY plane perpendicular to the height direction of the workpiece; and S3, based on a preset n-rho inverse proportion function model of the doping concentration n and the resistivity rho, and a delta omega-n linear model of the Raman frequency shift delta omega and the doping concentration n, determining and associating the XY coordinate positions of the S2 and the corresponding resistivity rho ij, and constructing a resistivity distribution diagram of the surface layer of the workpiece. The method has the advantages of small detection error and short detection time.

A semiconductor device includes a foundation layer and a transistor layer. The foundation layer is based on single-crystalline silicon carbide and includes a current propagation region of a first conductivity type and a non-depletable shielding structure of a second conductivity type. The transistor layer is based on epitaxially grown single-crystalline silicon carbide and includes a transistor cell (TC) configured to control a current through the current propagation region. The transistor layer is formed on the foundation layer after formation of the shielding structure in the foundation layer such that an epitaxial interface forms between the transistor foundation layer and the layer. The current propagation region extends from the epitaxial interface between neighboring partial regions of the shielding structure. Along a vertical line orthogonal to the epitaxial interface and through a pn junction between the shielding structure and a region of the first conductivity type in the transistor layer, a net dopant concentration changes by at least 1e17 1 / cm3 per 0.1 μm at the position of the pn junction.

The invention discloses a preparation process of a sintering kiln silicon carbide guide roller with thermal shock resistance and high-temperature corrosion resistance. The process comprises the following steps: sequentially carrying out surface pretreatment such as reticulate pattern laser engraving, sand blasting and cleaning and drying on a silicon carbide guide roller substrate; performing plasma spraying on a pure aluminum oxide coating after preheating; carrying out segmented laser remelting on the coating to improve the compactness; and finally, coating the nano silicon carbide slurry, calcining and curing. The thermal shock resistance and the high-temperature corrosion resistance of the guide roller are remarkably improved by enhancing the binding force of the coating through laser engraving, optimizing the density of the coating through laser remelting and combining post-treatment of nano silicon carbide slurry, and the service life of the guide roller in a lithium battery positive electrode material sintering kiln is prolonged.

The embodiment of the invention relates to the photovoltaic field, and provides a back contact solar cell, a preparation method thereof and a photovoltaic module, and the method comprises the steps: providing a substrate which comprises a front surface and a back surface which are opposite to each other, and the back surface comprises a first region and a non-first region; sequentially stacking a first doped conductive layer and a first mask layer on the back surface of the substrate, and removing the first mask layer corresponding to a non-first region through laser; at least removing the first doped conductive layer corresponding to the non-first region, wherein the remaining first doped conductive layer forms a first emitter; a second doped conductive layer and a second mask layer are sequentially stacked on the side, away from the first emitting electrode, of the remaining first mask layer and the non-first region, and materials of the first mask layer and the second mask layer independently comprise at least one of amorphous silicon, nanocrystalline silicon and silicon carbide; at least removing the second mask layer corresponding to the first region through laser; and at least removing the second doped conductive layer corresponding to the first region, wherein the remaining second doped conductive layer forms a second emitter.

The invention relates to a preparation method of a surface acoustic wave filter integrated with a CMOS (Complementary Metal Oxide Semiconductor) process, which comprises the following steps of: preparing a CMOS radio-frequency signal processing circuit by using a silicon or silicon carbide substrate, combining a dielectric buffer layer with a piezoelectric material, and then depositing a metal interdigital structure on the surface of the piezoelectric material to prepare the surface acoustic wave filter. A passivation layer is deposited on the surface of the filter to protect the filter structure, finally a metal interconnection line and the passivation layer are prepared above the filter, and in order to not affect the performance of the filter, an air cavity is prepared between the passivation layer and the metal interconnection layer of the filter, so that the passivation layer and the metal interconnection layer are effectively isolated. According to the preparation method, the surface acoustic wave filter and the CMOS radio frequency circuit can be integrated, the problem that radio frequency front-end and rear-end signal processing cannot be integrated at the same time at present is solved, and the preparation method plays an important role in promoting development of a radio frequency chip in the directions of high integration, low cost, miniaturization and the like; and the radio frequency chip has wide practical value and economic value in the radio frequency chip application field.

The utility model provides a double-channel planar gate silicon carbide LDMOS. The double-channel planar gate silicon carbide LDMOS is characterized in that a first N-type source region is connected with a silicon carbide substrate; the first channel region is connected with the silicon carbide substrate and the first N-type source region; the isolation region is respectively connected with the first channel region, the first N-type source region and the second N-type source region; the second channel region is connected to the isolation region and the first N-type source region; the P-type well region is connected with the isolation region and the second channel region, and the P-type well region is connected to the first N-type source region; the second N-type source region is arranged in the first through hole, the second N-type source region is connected to the isolation region, the body diode metal layer is arranged in the second through hole, and the body diode metal layer is connected to the isolation region; the gate dielectric layer is connected with the P-type well region, the source metal layer is arranged in the third through hole, and the source metal layer is connected to the second N-type source region and the body diode metal layer; the gate metal layer is connected to the gate dielectric layer; the drain metal layer is connected to the first N-type source region; double-channel structure design is carried out in the transverse power device, so that the on-resistance of the device is reduced.

The invention discloses a silicon carbide continuous sintering furnace performance optimization method based on a dynamic grid technology. The method comprises the following steps that a three-dimensional simulation model of a continuous sintering furnace load silicon carbide workpiece is established, unstructured grid division is conducted, and grid encryption treatment is conducted on a heating area, the silicon carbide workpiece and a cooling water system inlet and outlet; performing three-dimensional transient heat transfer calculation, and setting a dynamic area by combining the dynamic grid model to obtain a dynamic temperature field distribution rule of the silicon carbide workpiece in the continuous moving heating process; under different heating belt structures and different temperature setting modes, the temperature difference between the center and the edge and the temperature difference between the front end face and the rear end face of the moving silicon carbide workpiece are compared and analyzed, a heating performance optimization scheme of an original furnace profile is determined, and therefore the temperature uniformity of the silicon carbide workpiece in the furnace is improved. The original furnace profile is optimized on the premise that the structural size of the furnace body is not changed, and the temperature uniformity of the silicon carbide workpiece is remarkably improved.