2578 results about "Silicon carbide" patented technology

The invention relates to the technical field of MOS semiconductors, and discloses a variably doped planar gate silicon carbide VDMOS device and a preparation process thereof, the variably doped planar gate silicon carbide VDMOS device comprises a plurality of MOS cells which are parallel to each other, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of a single MOS cell; lateral symmetric P-layers are arranged in the single MOS cell and located on the left side and the right side of the N drift layer, and the section contours of the corresponding sides of the lateral symmetric P-layers on the two sides are in an arc shape. By arranging the lightly doped N layer in the middle of the N drift layer and introducing the arc-shaped laterally-symmetrical P-layers to the two sides, the electric field distribution of the device is optimized, the local electric field concentration is reduced, the breakdown voltage is remarkably improved, and the charge balance capability is enhanced and the leakage current is reduced through the contact between the laterally-symmetrical P-layers and the N substrate layer.

The invention discloses a method of preparing aluminum oxide-silicon carbide compound porous ceramic by aluminum-silicon industrial waste residues. The primary raw materials comprise industrial waste residues, carbon powder, a pore forming substance and an adhesive. The aluminum oxide-silicon carbide compound porous ceramic is prepared by the following steps of mixing, drying, forming and sintering to obtain a final product. Treatment and high additional value utilization of the industrial waste residues are achieved. The prepared porous ceramic is remarkable in performance, and can be applied to the fields of filtration, sound isolation, heat isolation, fire fighting and the like. The method is simple in process flow and convenient for industrialized promotion; and the cost is good to control and the method has extreme economical value.

The invention relates to the technical field of optical engineering, in particular to an AI silicon carbide lens-oriented aspheric laser polishing precision online detection and feedback system. Comprising a detection module; the data processing module is electrically connected with the detection module and used for constructing a lens surface three-dimensional model and calculating polishing precision parameters; the feedback control module is electrically connected with the data processing module, is used for generating a feedback control strategy and comprises a strategy generation unit and a parameter optimization unit; an execution module; and an intelligent learning module. According to the design, a laser measuring head, an energy sensor array and an environment sensor are integrated through the detection module, synchronous acquisition of multi-dimensional data such as surface profile, laser energy distribution and environment parameters is realized, and three-dimensional point cloud data with consistent time and space are generated through multi-modal fusion processing (time domain synchronization, space registration and feature enhancement) of the data preprocessing unit; the physical essence of the polishing process is completely represented, and the detection comprehensiveness and the data relevance are improved.

The invention relates to the technical field of packaging of power electronic devices, in particular to a three-dimensional packaged double-sided heat dissipation power module. The structure comprises an upper active metal brazing base material substrate and a lower active metal brazing base material substrate, a plurality of silicon carbide MOSFET chips, conductive strips and an inserter used for fixing the chips are arranged between the upper active metal brazing base material substrate and the lower active metal brazing base material substrate, the upper half-bridge chip is annularly arranged around a direct-current positive terminal, the lower half-bridge chip is annularly arranged around a direct-current negative terminal, and heat dissipation channels are formed in the upper surface and the lower surface of each chip. The impedance of branches is controlled to be equal, the current of each branch chip is balanced, the distance and layout of the chips are optimized, the overall loop area is reduced, the parasitic stray inductance of the module is reduced, in addition, the chips and the substrate are connected in a crimping mode, the chips and the copper columns are in contact through pressure to achieve electric heat conduction, the crimping materials are graphene sheets and molybdenum sheets, and the cost is low. Good contact between the chip and the copper columns is ensured, and contact resistance and thermal resistance are reduced. According to the invention, the effects of improving the heat dissipation efficiency, reducing parasitic stray inductance, balancing the current distribution of the parallel chips, and enhancing the module reliability and the conversion efficiency are achieved.

The invention relates to the field of pressure sensors, in particular to a pressure sensor and a processing method, and a chip comprises a silicon substrate, a silicon dioxide dielectric layer, a device layer, a metal electrode and packaging glass. The device layer comprises a silicon carbide single crystal device layer and a silicon device layer; the silicon carbide single crystal device layer is arranged on the silicon device layer; the silicon device layer, the silicon dioxide dielectric layer and the silicon substrate are connected in sequence; the device layer is etched to form a sensitive resistor device layer, an annular sealing region and a micro-channel; the sensitive resistance device layer is isolated from the annular sealing area through the micro-channel; the device layer, the silicon dioxide dielectric layer and the silicon substrate are etched to form a cross beam etching area; the silicon substrate is etched to form a silicon pressure cavity and a beam film; the metal electrode is arranged on the top of the device layer; and the packaging glass anode is bonded at the top of the device layer or the bottom of the silicon substrate so as to solve the problems of low high temperature resistance and low sensitivity of the MEMS pressure sensor.

The invention discloses a joint test system, a silicon carbide metasurface grating detection method and a silicon carbide metasurface grating detection device, and belongs to the technical field of semiconductor detection. A synergistic excitation signal is generated by regulating a light source and a microwave source and is applied to the silicon carbide metasurface grating to be measured to form a light intensity and microwave field interference pattern. The method comprises the following steps: synchronously acquiring data through multiple channels, constructing a multi-dimensional matrix through time alignment, marker feature extraction and coordinate mapping, extracting defect features to establish a reference model, calculating deviation degree to judge quality, and carrying out abnormal point screening, candidate region construction and coupling verification on a defect grating to divide a potential defect region. For a potential defect area, excitation parameters are dynamically adjusted through a gradient descent algorithm, and defect grades are divided by combining the characteristic defect degree and the area. According to the invention, the problems of insufficient single-mode detection, low multi-mode alignment precision and blind adjustment of excitation parameters are solved, cross-band cooperative detection and intelligent grading are realized, and the detection reliability is improved.

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide thick-bottom oxide layer groove MOS structure and a preparation method thereof, the silicon carbide thick-bottom oxide layer groove MOS structure comprises a plurality of parallel MOS cells, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the lightly doped N layer is arranged in the middle of the N drift layer, the arc-shaped contour design with the inclined top is introduced to the two sides, the injection area is accurately controlled through the photoetching technology, the phenomenon that the edge electric field concentration of the N drift layer is effectively dispersed is effectively dispersed, in this way, electric field distribution is more uniform, breakdown voltage is improved, and local electric field concentration is reduced; moreover, the contact between the laterally symmetrical P-layer and the N substrate layer enhances the charge balance capability, and reduces the leakage current.

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide plane MOS device polysilicon gate self-alignment process and a low resistance structure, the silicon carbide plane MOS device polysilicon gate self-alignment process comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, and the N drift layer comprises a drain electrode, a source electrode and a grid electrode. The height of the P well layer in the single MOS cell is aligned with that of the grid electrode, and the P well layer is located on the left side and the right side of the grid electrode; the N well layer and the P + layer are both located above the grid electrode and the P well layer, and the P + layer is located on the outer side of the N well layer. According to the invention, the height of the P well layer is accurately aligned with the grid electrode, the P well layer is arranged at the two sides of the grid electrode, the design of the T-shaped source electrode is combined, the conduction path is optimized, and when the voltage is applied to the grid electrode, vertical channels are formed at the two sides of the P well layer, so that the path of current flowing from the drain electrode to the source electrode through the N drift layer is shorter and the distribution is uniform.

The invention discloses a silicon carbide TrenchMOS device and a manufacturing method thereof, and belongs to the field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the arc-shaped lightly-doped N layer is additionally arranged in the middle of the arc-shaped heavily-doped N layer, electric field distribution under reverse bias is smoothed through the doping concentration lower than that of the heavily-doped N layer, the interface electric field sudden change risk is reduced, dynamic loss is reduced, meanwhile, the doping concentration of the central area is diluted through the arc-shaped inner side lightly-doped N layer, a depletion area is promoted to be expanded, and the performance of the device is improved. Electric field distribution between drain gates is optimized, and stray capacitance is reduced to improve high-frequency performance.

The disclosure relates to a π type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

The present invention relates to a reaction chamber comprising a removable reaction unit and a susceptive casing. The present invention further relates to a reactor incorporating said reaction chamber, and to an assembly comprising said reactor. Additionally, the present invention relates to a method adapted to reduce the preventive maintenance times of the reactor hereinbefore described, and to the use of said reactor in the homoepitaxial or heteroepitaxial deposition of silicon carbide or gallium nitride films on a semiconductor substrate.

The invention discloses a laser processing device, a silicon carbide crystal ingot cutting method and a laser processing system. The laser processing device comprises a laser used for emitting a laser beam with preset laser parameters; the beam splitting element is used for splitting the laser beam into a plurality of sub-beams arranged along a preset direction; the spherical aberration compensation element is used for performing spherical aberration compensation on the plurality of sub-beams and outputting a plurality of spherical aberration compensation beams; and the scanning mechanism is used for focusing the plurality of spherical aberration compensation light beams and cutting the silicon carbide crystal ingot according to a preset cutting path and a preset cutting speed by utilizing the plurality of focused spherical aberration compensation light beams. Spherical aberration compensation is carried out on the sub-beams, the spot size of the focused sub-beams in the silicon carbide crystal ingot in the optical axis direction can be remarkably reduced, the length of a growth area of microcracks is reduced, and then a high-quality silicon carbide wafer is obtained. In addition, the coverage area of the plurality of sub-beams on the surface of the silicon carbide crystal ingot is larger, so that the cutting efficiency is improved.

The present invention discloses a prediction method for a crosstalk spike in a half bridge of current-source inverter with silicon carbide devices, where, the prediction method includes calculation of the crosstalk voltage spike in the circuit of current-source type double-pulse test and analysis of the effect of each parameter on the magnitude of the crosstalk spike. The prediction method of the present invention analyzes the horizontal conduction crosstalk mechanism between the gate-source junction of the MOSFET caused by the high-frequency switching action of the silicon carbide (SiC) MOSFET and the SiC Schottky diode connected in series, and derives the prediction model for the crosstalk voltage spike in the half-bridge of current-source inverter. Based on the equivalent circuit of the current-source-type double-pulse test and the crosstalk-induced mechanism, the extreme value of crosstalk voltage spike is accurately predicted, which is helpful to analyze the effects of the drive circuit and the parameters of the power circuit on the crosstalk voltage spike through the prediction model.

The invention relates to the technical field of MOS semiconductors, and discloses a heterojunction-based silicon carbide groove type MOSFET device structure and a preparation process thereof.The heterojunction-based silicon carbide groove type MOSFET device structure comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a source electrode, a grid electrode and a semiconductor epitaxial layer, and each semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer; a groove is formed in the upper surface of the single MOS cell and located below the grid electrode, an N + layer is deposited in the groove, and the N + layer comprises a left N + layer and a right N + layer. Through the design of the split type left N + layer and the right N + layer in the groove and the combination of the middle N-layer or the middle P-layer filled in the middle, the electric field concentration phenomenon at the bottom of the groove is effectively dispersed, and the electric field peak value at the edge of the N drift layer is further inhibited in cooperation with the right triangle arrangement of the blocking ion bubbles, so that the breakdown voltage and the reliability of the device are remarkably improved, and the reliability of the device is improved. The method is suitable for high-voltage application scenes.

The invention discloses a high-voltage SiC MOSFET cellular structure. The high-voltage SiC MOSFET cellular structure comprises an N + type silicon carbide power substrate, an N type drift region and a current expansion layer which are stacked in sequence, the electric field modulation regions are arranged on the left side and the right side of the current expansion layer, the P-body region is arranged above the current expansion layer, and the N + type source region and the P + type source region are arranged above the P-body region; the gate trench is arranged in the middle of the current expansion layer, a P + type shielding region is arranged at the bottom of the gate trench, a gate is arranged in the gate trench, and the gate is located above the P + type shielding region; and the gate oxide layer covers the upper surfaces of the gate, the N + type source region and the P + type source region. According to the structure, the electric field modulation areas are arranged on the two sides of the current expansion layer, the peak electric field intensity of the bottom of the groove of the UMOSFET device is reduced, the reverse breakdown voltage of the device is greatly improved, and meanwhile, the N-type areas in the electric field modulation areas also effectively reduce the characteristic on-resistance when the power device is conducted.

The invention relates to a nanometer aluminum oxide polishing solution for a silicon carbide substrate slice as well as a preparation method and application of the nanometer aluminum oxide polishing solution. The nano aluminum oxide polishing solution is prepared from the following components in percentage by weight: 0.5 to 6.0 percent of alpha-Al2O3 abrasive, 0.5 to 5.0 percent of oxidant, 0.1 to 1.0 percent of pro-oxidant, 0.05 to 0.50 percent of pH (Potential of Hydrogen) regulator, 0.10 to 0.50 percent of dispersing agent and the balance of water, the D10 of the alpha-Al2O3 grinding material ranges from 0.100 to 0.140 [mu] m, the D50 of the alpha-Al2O3 grinding material ranges from 0.180 to 0.230 [mu] m, the D90 of the alpha-Al2O3 grinding material ranges from 0.240 to 0.300 [mu] m, the D100 of the alpha-Al2O3 grinding material ranges from 0.340 to 0.420 [mu] m, and The preparation method of the alpha-Al2O3 abrasive material comprises the following steps: preparing alpha-Al2O3 powder into alpha-Al2O3 slurry, adding potassium citrate, grinding, and carrying out particle classification on the alpha-Al2O3 slurry after grinding, so as to obtain the alpha-Al2O3 abrasive material. Compared with the prior art, graded alpha-Al2O3 is selected as abrasive particles for silicon carbide polishing, potassium permanganate with higher oxidability is selected as an oxidizing agent, and the prepared nanometer aluminum oxide polishing solution is applied to chemical mechanical polishing of a silicon carbide substrate slice; the surface roughness of the silicon carbide substrate slice is reduced while the removal rate of the silicon surface material of the silicon carbide substrate slice is improved, and the atomic-scale smooth surface quality is obtained.

The present application relates to nuclear fuel claddings, and more particularly to zirconium alloy tubes with a ceramic covering. A first coating layer is applied to the ceramic covering. A second coating layer is over the first coating layer. The first coating layer includes Nb. The second coating layer includes Cr.

The invention discloses a composite terminal structure of a silicon carbide PIN diode and a design method of the composite terminal structure. The composite terminal structure comprises a device cell and a device terminal. The device cell comprises an N + type heavily doped substrate, an N-type lightly doped drift layer and a P + type heavily doped layer which are arranged in sequence; the device terminal is located in the N-type lightly doped drift layer, the device terminal comprises two parts of P + type junction terminal expansion regions and three groups of P + type field limiting ring structures, P + injection rings formed by P + type ion injection are arranged in the P + type junction terminal expansion regions, a plurality of P + injection rings form the P + type field limiting ring structures, the adjacent P + injection rings are separated by the P + type junction terminal expansion regions, and the P + type field limiting ring structures are arranged in the N-type lightly doped drift layer. And the upper surfaces of the P + type junction terminal expansion region and the P + injection ring are covered with oxide layers. The high-voltage power device has the advantages of being compact in structure, small in device area, low in production cost and the like, higher breakdown voltage, better process robustness and long-term reliability are achieved within the limited chip area, and the requirements of the next-generation high-voltage power device are met.

The invention belongs to the technical field of power devices, and provides a silicon carbide device structure, a preparation method thereof and a chip, a P-type heavily doped region is isolated from a junction field effect transistor region at an adjacent position by a P-type well region, and an N-type heavily doped region is isolated from the junction field effect transistor region at an adjacent position by the P-type well region. The adjacent junction field effect transistor regions are isolated by the P-type well regions, so that a super-junction-like structure is formed, the junction field effect transistor regions can have donor doping with higher doping concentration, corner arrangement is avoided, a depletion region can be completely closed, the on resistance of the device is reduced, and the reliability of the device is improved.

A silicon carbide source material structure for use in a sublimation system for growing single crystal silicon carbide is provided. The silicon carbide source material structure may comprise a first layer and a second layer, the first layer being different from the second layer in at least one property.

The invention discloses a combined passivation back contact battery which comprises an N-type silicon wafer, a second intrinsic amorphous silicon layer, a microcrystalline silicon layer, an anti-reflection layer, a second semiconductor opening region, a first semiconductor opening region and a transition region, the anti-reflection layer is a single-layer amorphous silicon carbonitride layer or a laminated structure composed of an amorphous silicon carbide layer and an amorphous silicon carbonitride layer, and the second semiconductor opening area is composed of a first intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a transparent conductive film and a metal electrode which are sequentially arranged on the back face of the silicon wafer. The first semiconductor opening area is composed of a tunneling oxide layer, an N-type polycrystalline silicon layer, a transparent conductive film and a metal electrode which are sequentially arranged on the back face of the silicon wafer, and an opening is etched in the transparent conductive film on the surface of the transition area to form an insulation groove. Amorphous silicon carbonitride or amorphous silicon carbide / amorphous silicon carbonitride laminated layers are adopted as the anti-reflection layers, so that reflection loss is reduced, the reliability and durability of the cell are improved, and the conversion efficiency of the cell is improved.

The invention discloses a low stray inductance structure of a plastic package module, which comprises a silicon carbide chip, a negative terminal, a positive terminal, an AC terminal and a plastic package body which are arranged on a lining plate, the silicon carbide chip, the negative terminal, the positive terminal and the AC terminal are wrapped by the plastic package body, the negative terminal and the positive terminal are of a laminated arrangement structure, and the silicon carbide chip, the negative terminal, the positive terminal and the AC terminal are arranged on the lining plate. And the positive terminal is fixedly connected with the negative terminal through an insulating bonding sheet to form a power terminal. The positive terminal and the negative terminal are laminated, so that the distance between copper bars is reduced to the maximum extent, and the stray inductance of a module end is reduced; and the bus capacitor matched with the module also adopts a laminated structure, so that the stray inductance at the bus capacitor is reduced.

The invention relates to the field of ceramic materials, in particular to a high-temperature-resistant composite ceramic material and a preparation method thereof.The high-temperature-resistant composite ceramic material is prepared from, by weight, 80-100 parts of zirconium oxide, 10-20 parts of silicon carbide, 5-10 parts of aluminum nitride, 1-5 parts of a sintering aid and 5-10 parts of modified silicon powder; the modified silicon powder takes nano silicon powder as a core body, the core body is sequentially coated with a transition metal organic polymer and oxidized asphalt, and the prepared composite ceramic material is good in mechanical strength and excellent in high temperature resistance and has important application value in the field of aerospace.

The invention provides a preparation method of a high-performance silicon nitride ceramic substrate, and relates to the field of production and preparation of silicon nitride ceramic substrates, and the high-performance silicon nitride ceramic substrate comprises the following raw materials by weight: 40-130 parts of silicon nitride powder, 20-110 parts of an organic solvent, 3-15 parts of a sintering aid, 5-15 parts of a binder, 2-6 parts of a plasticizer, and 1-6 parts of a dispersant. A tape casting method is adopted, the silicon nitride ceramic substrate is prepared through glue discharging and air pressure sintering, and the silane coupling agent, the silicon powder, the beta-phase silicon nitride powder, the silicon carbide whiskers and other ingredients can remarkably improve the strength and the thermal conductivity of the silicon nitride ceramic substrate.

The invention discloses a silicon carbide step groove MOSFET and a manufacturing method thereof. The MOSFET comprises a semiconductor drain region, a semiconductor drift region, a second conductive type semiconductor well region, a first conductive type semiconductor source region, a second conductive type semiconductor contact region, a first groove, a first conductive type carrier diffusion layer, a second groove, a second conductive type semiconductor shielding region, a gate dielectric layer, a gate electrode, an interlayer dielectric layer and a contact hole. And a source end metal electrode and a drain end metal electrode. A first conductive type semiconductor carrier diffusion layer (CSL) is prepared in a local region of the bottom and the side wall of a first groove, so that the specific on-resistance (Ron, sp) of the device is reduced; second conductive type semiconductor shielding regions short-circuited with the source end metal electrode are prepared in all regions of the bottom and the side wall of the second groove, so that the gate-oxide electric field can be remarkably reduced compared with a shielding region introduced only at the bottom of the groove, and the reliability of the device is improved.

The invention discloses a junction temperature prediction method based on SiC MOSFET turn-off loss, and belongs to the technical field of power electronics and electricians. The junction temperature prediction method combines a turn-off loss model with a junction temperature prediction model based on turn-off loss, and comprises the following steps: firstly, establishing a SiC MOSFET turn-off loss model considering parasitic parameters, secondly, establishing the junction temperature prediction model based on the SiC MOSFET turn-off loss in an off-line manner, and then, calculating the turn-off loss on line according to the loss model. And finally substituting the loss data into the junction temperature prediction model to obtain a junction temperature prediction value. According to the method, the turn-off loss and the junction temperature of the SiC MOSFET under different working conditions can be predicted, and the method has the advantages of being high in real-time performance, easy to implement, high in model precision and the like; and an efficient and accurate solution is provided for thermal evaluation and junction temperature prediction of the silicon carbide power device.

An improved silicon carbide (SiC) super junction (SJ) MOSFET having at least two buried P-shield (BPS) regions facing each other for gate oxide electric-field and saturation current reductions is disclosed. The two BPS regions are spaced apart from a body region and formed either adjoining sidewalls or below a bottom of a P column region. Moreover, a saturation current pitching (SCP) structure formed in a Junction Field Effect Transistor (JFET) region sandwiched between the two BPS regions limits saturation current of the device in a forward conduction stage for the short-circuit capability improvement.

The invention discloses a deposition system for chemical vapor deposition silicon carbide ring production, and relates to the field of high-end equipment manufacturing. The deposition system for producing the chemical vapor deposition silicon carbide ring comprises a furnace body, wherein a reaction chamber and a heating module are arranged in the furnace body; the plurality of spray head groups are connected with gas pipelines; the graphite support is installed at the inner bottom of the bottom cover, the graphite support is used for supporting the annular single crystal substrate, and the graphite support is detachable; the stabilizing mechanism comprises a lifting seat, the supporting arm is fixed to the lifting seat, and the clamping assembly is installed on the supporting arm; the device comprises a furnace body, a nozzle group, a conveying mechanism and a lifting mechanism, and is characterized in that gas containing silicon and carbon is sprayed into the furnace body through the nozzle group, so that the gas containing silicon and carbon can be quickly and uniformly dispersed into a reaction chamber in the furnace body, and the deposition rate and uniformity of silicon carbide on an annular single crystal substrate are ensured; the detachable graphite support is formed by combining a plurality of splicing columns, horizontal supporting rods and clamping needles, and the influence of the graphite support on airflow is reduced by adjusting the number of the splicing columns.

The invention belongs to the technical field of ceramic materials, and discloses a high-entropy boride composite silicon carbide ceramic with a controllable microstructure and a preparation method and application thereof. The method comprises the following steps: carrying out ball milling, drying and sieving on Zr, Ta, Nb, W, Cr, B4C and SiB6 to obtain mixed powder; the preparation method comprises the following steps: putting a boron carbide powder into a graphite mold of which the inner surface is coated with a BN layer, heating to 1850-2050 DEG C, carrying out SPS sintering, and preparing the high-entropy boride composite silicon carbide ceramic with controllable microstructure under 20-35 MPa and a vacuum degree of 10 Pa, and the molecular formula of the high-entropy boride composite silicon carbide ceramic is (Zr0. 2Ta0. 2Nb0. 2W0. 2Cr0. 2) B2-SiC. The ceramic has good mechanical properties, the hardness at room temperature is 27-32 GPa, the fracture toughness is 4.5-6 MPa.m < 1 / 2 >, the bending strength is 450-600 MPa, and the ceramic can be applied to extreme environments or the field of radiation protection.

The invention relates to a silicon carbide super-junction transverse MOS device and a manufacturing method thereof, and belongs to the technical field of semiconductor devices. The device sequentially comprises a substrate and an epitaxial layer from bottom to top, a p column region is arranged on the outer side of the epitaxial layer, a drain region is arranged on the outer side of the p column region, a p well region is arranged on the inner side of the epitaxial layer, a source region is arranged on the inner side of the p well region, a p + region is arranged on the outer side of the p well region, a groove is formed in the middle of the epitaxial layer, and a gate oxide layer is arranged in the groove. A gate polycrystalline silicon is arranged in the gate oxide layer, source electrode metal is arranged on the upper sides of the source electrode region and the p + region, drain electrode metal is arranged on the upper side of the drain electrode region, a dielectric layer is arranged between the source electrode metal and the drain electrode metal, and top layer metal is arranged at the tops of the source electrode metal and the drain electrode metal. According to the invention, the doping concentration of the drift region can be improved while the withstand voltage of the device is ensured, and higher withstand voltage and lower on resistance of the device are realized.