603 results about "Stress induced" patented technology

An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.

A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.

By recessing a semiconductor layer, preferably by locally oxidizing the semiconductor layer, a stress-inducing material and/or a dopant species may be introduced into the thinned semiconductor layer in the vicinity of a gate electrode structure by means of a subsequent epitaxial growth process. In particular, the stress-inducing material formed adjacent to the gate electrode structure exerts compressive or tensile stress, depending on the type of material deposited, thereby also enhancing the mobility of the charge carriers in a channel region of the transistor element.

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.

A method for manufacturing a thin film direct bandgap semiconductor active solar cell device comprises providing a source substrate having a surface and disposing on the surface a stress layer having a stress layer surface area in contact with and bonded to the surface of the source substrate. Operatively associating a handle foil with the stress layer and applying force to the handle foil separates the stress layer from the source substrate, and leaves a portion of the source substrate on the stress layer surface substantially corresponding to the area in contact with the surface of the source substrate. The portion is less thick than the source layer. The stress layer thickness is below that which results in spontaneous spalling of the source substrate. The source substrate may comprise an inorganic single crystal or polycrystalline material such as Si, Ge, GaAs, SiC, sapphire, or GaN. In one embodiment the stress layer comprises a flexible material.

A method for restoring hydrophobicity to the surfaces of organosilicate glass dielectric films which have been subjected to an etchant or ashing treatment. These films are used as insulating materials in the manufacture of integrated circuits to ensure low and stable dielectric properties in these films. The method deters the formation of stress-induced voids in these films. An organosilicate glass dielectric film is patterned to form vias and trenches by subjecting it to an etchant or ashing reagent in such a way as to remove at least a portion of previously existing carbon containing moieties and reduce hydrophobicity of said organosilicate glass dielectric film. The vias and trenches are thereafter filled with a metal and subjected to an annealing treatment. After the film is subjected to the etchant or ashing reagent, but before being subjected to an annealing treatment, the film is contacted with a toughening agent composition to restore some of the carbon containing moieties and increase the hydrophobicity of the organosilicate glass dielectric film.

One embodiment of the present invention includes a non-volatile magnetic memory element including a fixed layer, a barrier layer formed on top of the fixed layer, and a free layer formed on top of the barrier layer, wherein the electrical resistivity of the barrier layer is reduced by placing said barrier layer under compressive stress. Compressive stress is induced by either using a compressive stress inducing layer, or by using inert gases at low pressure during the sputtering process as the barrier layer is deposited, or by introducing compressive stress inducing molecules into the molecular lattice of the barrier layer.

A process for assembling a medical device made from a nickel-titanium alloy for use in a mammalian body while avoiding the formation of stress-induced martensite and a medical device used in combination with a delivery system for deployment into the mammalian body are disclosed. By heating the nickel-titanium alloy of the medical device to a temperature above M_d, and deforming and installing the device into a delivery system or holding capsule, it is possible to avoid the formation of stress-induced martensite in the stent, which stays in the austenitic phase throughout.

A semiconductor device includes a metal oxide semiconductor (MOS) transistor including two source/drain regions located at a surface layer side of the semiconductor substrate, a stress-inducing film formed so as to cover the source/drain region of the MOS transistor, the stress-inducing film applying stress to a channel region formed between the source/drain regions and having an opening corresponding to an electrical connection region of the source/drain regions, the opening having a first dimension with respect to a propagation direction of a charge carrier moving within the channel region of the MOS transistor and a second dimension with respect to a direction perpendicular to the propagation direction of the MOS transistor, the first dimension being larger than the second dimension.

A magnetic field angle sensor for measurement of a magnetic field angle over a 360° range has magnetic tunnel junction elements oriented at multiple angles. The magnetic field angle sensor includes multiple magnetic tunnel junction elements formed on a substrate that have an anti-ferromagnetic layer and pinned synthetic multiple layer. The magnetic tunnel junction elements are patterned to have a large dimensional aspect ratio and large anisotropies the pinned synthetic multiple layer of the magnetic tunnel junction elements. The magnetic tunnel junction elements are annealed in the presence of a strong magnetic field in a direction of the reference axis and the annealed for a second time with no external magnetic field so that exchange pinning is reduced and strong stress induced anisotropies of the pinned synthetic multiple layer align magnetization of the pinned synthetic multiple layer align a long axis of each of the magnetic tunnel junction elements.

The present invention to provide a new technique to reduce a variation in switching field of a magnetization free layer in a magnetic memory. The magnetic memory according to the present invention includes a magnetization free layer including a ferromagnetic layer having a shape magnetic anisotropy in a first direction and a magnetic strain constant is positive; and a stress inducing structure configured to apply a tensile stress to said magnetization free layer in a same direction as the first direction.

The present invention relates generally to methods for designing and optimizing the number, placement, and size of fractures in a subterranean formation and more particularly to methods that account for stress interference from other fractures when designing and optimizing the number, placement, and size of fractures in the subterranean formation. The present invention optimizes the number, placement and size of fractures in a subterranean formation. The present invention determinines one or more geomechanical stresses induced by each fracture based on the dimensions and location of each fracture. The present invention determinines a maximum number of fractures and a predicted stress field based on the geomechanical stresses induced by each of the fractures

In a micro-electromechanical structure, a rotor has a centroidal axis and includes a suspended structure which carries mobile electrodes. A stator carries fixed electrodes facing the mobile electrodes. The suspended structure is connected to a rotor-anchoring region via elastic elements. The stator includes at least one stator element, which carries a plurality of fixed electrodes and is fixed to a stator-anchoring region. One of the rotor-anchoring regions and stator-anchoring regions extends along the centroidal axis and at least another of the rotor-anchoring regions and stator-anchoring regions extends in the proximity of the centroidal axis.

MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material and the second semiconductor material is forced lower into the stress-inducing layer. The stress-inducing layer may be either a recessed region or non-recessed region. A first method involves forming a stress-inducing layer, such as SiGe, in the source/drain regions and performing a nitridation or oxidation process. A nitride or oxide film is formed in the top portion of the stress-inducing layer, forcing the Ge lower into the stress-inducing layer. Another method embodiment involves forming a reaction layer over the stress-inducing layer and performing a treatment process to cause the reaction layer to react with the stress-inducing layer.

An integrated circuit in which measurement of the alignment between subsequent layers has less susceptibility to stress induced shift. A first layer of the structure has a first overlay mark. A second and/or a third layer are formed in the alignment structure and on the first layer. Portions of the second and/or third layer are selectively removed from regions in and around the first overlay mark. A second overlay mark is formed and aligned to the first overlay mark. The alignment between the second overlay mark and first overlay mark may be measured with an attenuated error due to reflection and refraction or due to an edge profile shift of the first overlay mark.

A semiconductor structure and a method of fabricating the same in which strain enhancement is achieved for both nFET and pFET devices is provided. In particular, the present invention provides at least one spacerless FET for stronger strain enhancement and defect reduction. The at least one spacerless FET can be a pFET, an nFET, or a combination thereof, with spacerless pFETs being particularly preferred since pFETs are generally fabricated to have a greater width than nFETs. The at least one spacerless FET allows to provide a stress inducing liner in closer proximity to the device channel than prior art structures including FETs having spacers. The spacerless FET is achieved without negatively affecting the resistance of the corresponding silicided source/drain diffusion contacts, which do not encroach underneath the spacerless FET.

A method for fabricating a stressed MOS device in and on a semiconductor substrate is provided. The method comprises the steps of forming a gate electrode overlying the semiconductor substrate and etching a first trench and a second trench in the semiconductor substrate, the first trench and the second trench formed in alignment with the gate electrode. A stress inducing material is selectively grown in the first trench and in the second trench and conductivity determining impurity ions are implanted into the stress inducing material to form a source region in the first trench and a drain region in the second trench. To preserve the stress induced in the substrate, a layer of mechanically hard material is deposited on the stress inducing material after the step of ion implanting.

A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.