MOSFET structure with high mechanical stress in the channel

Abstract

The present invention provides a semiconducting device including at least one gate region including a gate conductor located on a surface of a substrate, the substrate having an exposed surface adjacent the gate region; a silicide contact located adjacent the exposed surface; and a stress inducing liner located on the silicide contact, the exposed surface of the substrate adjacent to the gate region and the at least one gate region, wherein the stress inducing liner provides a stress to a device channel portion of the substrate underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 200 MPa to about 2000 MPa. The present invention also provides a method for forming the above-described semiconducting device.

Description

FIELD OF THE INVENTION[0001]The present invention relates to semiconductor devices having enhanced electron and hole mobilities, and more particularly, to semiconductor devices that include a silicon (Si)-containing layer having enhanced electron and hole mobilities. The present invention also provides methods for forming such semiconductor devices.BACKGROUND OF THE INVENTION[0002]For more than three decades, the continued miniaturization of silicon metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. A concise summary of near-term and long-term challenges to continued complementary metal oxide semiconductor (CMOS) scaling can be foun...

AI Technical Summary

Benefits of technology

This approach increases device performance by 5% to 50% compared to prior FETs, while maintaining or improving conformality and reducing unwanted stress effects, and allows for superior stress distribution without the need for additional processing steps.

Problems solved by technology

However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits.

Since it has become increasingly difficult to improve MOSFETs and therefore CMOS performance through continued scaling, methods for improving performance without scaling have become critical.

This results in changes in carrier transport properties, which can be dramatic in certain cases.

This approach is unacceptable since it limits the scaling of the distance between the contact 50 and the gate conductor 3.

This approach is also unacceptable because it requires additional processing and has negative effects on the portions of the device in which a stress in not desired.

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