14471 results about "CMOS" patented technology

A tissue ablation system is described. The tissue ablation system can include a plurality of electrodes, a viewing window between adjacent electrodes, illuminating elements, and an image sensor. The image sensor can be a CMOS device.

Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (i.e., B and P) into the body. The invention reduces the problem of short channel effects such as drain induced barrier lowering and the leakage current from the source to drain regions via the hetero-junction and while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. The problem of scalability of the gate length below 100 nm is overcome by the heterojunction between the source and body regions.

A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.

Disclosed embodiments comprise an energy harvesting computer device in association with a communication device comprising interactive user interface operatively configured with CMOS multiple antennas on chip for boosting signal receptions and for providing faster data transmission speed. Disclosed embodiment encompasses three modes of communications—the Cell phone, wireless Internet applications, and Global communication and media information. Embodiments provide communication apparatus operable to enhance mobile communication efficiency with touch sensitive display comprising energy harvesting platform in communication with a charging circuit board configured with memories, processors, sensors, and modules. Embodiments further provide a gaming device, a wireless media device configured with touch pads comprising sensors being embedded in silicon substrate and fused in nano-fiber/microfiber material having excellent electrical characteristics. Certain embodiments provide communication apparatus configured for voice enabled applications comprising human voice auditory operable to convert text into voice auditory and/or voice auditory into text applications.

A method utilizing localized amorphization and recrystallization of stacked template layers is provided for making a planar substrate having semiconductor layers of different crystallographic orientations. Also provided are hybrid-orientation semiconductor substrate structures built with the methods of the invention, as well as such structures integrated with various CMOS circuits comprising at least two semiconductor devices disposed on different surface orientations for enhanced device performance.

Semiconductor structures, devices, and methods of forming the structures and device are disclosed. Exemplary structures include multi-gate or FinFET structures that can include both re-channel MOS (NMOS) and p-channel MOS (PMOS) devices to form CMOS structures and devices on a substrate. The devices can be formed using selective epitaxy and shallow trench isolation techniques.

The invention relates to devices and methods for nanopore sequencing. The invention includes arrays of nanopores having incorporated electronic circuits, for example, in CMOS. In some cases, the arrays of nanopores comprise resistive openings for isolating the electronic signals for improved sequencing. Methods for controlling translocation of through the nanopore are disclosed.

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. A multi step epitaxial process can be used to extend the ridges with different dopant types, high mobility semiconductor, and or advanced multi-layer strutures. For CMOS integrated circuits a capping layer is formed over the a first region. Epitaxial layers are formed in a second region. Then the capping layer is removed from the first region and a capping layer is formed over the second region. Epitaxial layers can than be formed in the first region.

A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.

A penetrating endoscope provides visualization of organ or tissue structures or foreign objects in a body. The penetrating endoscope includes an elongate penetrating member, a complementary metal dioxide semiconductor (CMOS) image sensor and an objective lens. The CMOS image sensor is substantially planar and includes a plurality of pixels with a pixel signal processing circuit for generating a color image ready signal. The CMOS image sensor converts image light energy into electrical color image ready signal energy for transmission out of the body. The color image ready signal is viewed on a color image display. The CMOS image sensor is carried on the elongate penetrating member adjacent a distal end of the elongate penetrating member. The objective lens is also carried on the distal end of the elongate penetrating member on an optical axis and focuses an image corresponding to an endoscope field of view at an image plane intersecting the optical axis. The CMOS image sensor is mounted with the CMOS image sensor pixels disposed substantially in the image plane and on the optical axis. The penetrating endoscope may include end effectors such as cutters and forceps.

A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the first and second dopant source regions comprises a dielectric material which contains dopants; causing the dopants to diffuse from the first and second dopant source regions into the semiconductor region so as to form first and second source/drain extension regions, respectively, wherein the first and second source/drain extension regions define a channel region disposed between; forming a gate dielectric region on a channel region; and forming a gate region on the gate dielectric region, wherein the gate dielectric region electrically insulates the gate region from the channel region.

The invention features an image reader and a corresponding method for capturing a sharp distortion free image of a target, such as a one or two-dimensional bar code. In one embodiment, the image reader comprises a two-dimensional CMOS based image sensor array, a timing module, an illumination module, and a control module. The time during which the target is illuminated is referred to as the illumination period. The capture of the image by the image sensor array is driven by the timing module that, in one embodiment, is able to simultaneously expose substantially all of the pixels in the array. The time during which the pixels are collectively activated to photo-convert incident light into charge defines the exposure period for the sensor array. In one embodiment, at least a portion of the exposure period occurs during the illumination period.

Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D integration scheme of the present invention, first semiconductor devices are pre-built on a semiconductor surface of a first silicon-on-insulator (SOI) substrate and second semiconductor devices are pre-built on a semiconductor surface of a second SOI substrate. After pre-building those two structures, the structure are bonded together and interconnect through wafer-via through vias. In a second 3D integration scheme, a blanket silicon-on-insulator (SOI) substrate having a first SOI layer of a first crystallographic orientation is bonded to a surface of a pre-fabricating wafer having second semiconductor devices on a second SOI layer that has a different crystallographic orientation than the first SOI layer; and forming first semiconductor device on the first SOI layer.

A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS transistors on the vertical surfaces thereof. The complementary NMOS and PMOS transistors form a CMOS transistor pair. The transistors are preferably used in structures such as memory circuits, e.g., DRAMs, which are, in turn, used in a processor-based system. Ideally, the deep sub-micron NMOS and PMOS transistors are operated in velocity saturation for optimal switching operation.

A structure, and method of fabrication, for high performance field effect devices is disclosed. The MOS structures include a crystalline Si body of one conductivity type, a strained SiGe layer epitaxially grown on the Si body serving as a buried channel for holes, a Si layer epitaxially grown on the SiGe layer serving as a surface channel for electrons, and a source and a drain containing an epitaxially deposited, strained SiGe of opposing conductivity type than the Si body. The SiGe source/drain forms a heterojunction and a metallurgical junction with the Si body that coincide with each other with a tolerance of less than about 10 nm, and preferably less than about 5 nm. The heterostructure source/drain is instrumental in reducing short channel effects. These structures are especially advantageous for PMOS due to increased hole mobility in the compressively strained SiGe channel. Representative embodiments include CMOS structures on bulk and on SOI.

An electronic device, and SRAM and a method of forming the electronic device and SRAM. The semiconductor device including: a pass gate transistor having a fin body having opposing sidewalls aligned in a first direction and having a first majority carrier mobility and a gate adjacent to both sidewalls of the fin body; a pull down latch transistor having a fin body having opposing sidewalls aligned in a second direction and having a second majority carrier mobility and a gate adjacent to both sidewalls of thc fin body; a pull up latch transistor having a fin body having opposing sidewalls aligned in a third direction and having a third majority carrier mobility and a gate adjacent to both sidewalls of the fin body; and CMOS chevron logic circuits, wherein crystal planes of each fin body and of CMOS transistor of the chevron logic are co-aligned.