32 results about "Reverse short-channel effect" patented technology

A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (i.e., B and P) into the body. The invention reduces the problem of short channel effects such as drain induced barrier lowering and the leakage current from the source to drain regions via the hetero-junction and while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. The problem of scalability of the gate length below 100 nm is overcome by the heterojunction between the source and body regions.

In one embodiment, a semiconductor circuit includes a first group of field effect transistors having a body and parameters including a net channel doping level DL1. The circuit also includes a conductor to provide a first voltage to the body to forward body bias the first group of transistors, the first group of transistors having a forward body bias threshold voltage (VtFBB) when forward body biased, wherein DL1 is at least 25% higher than a net channel doping level in the first group of transistors that would result in a zero body bias threshold voltage equal to VtFBB, with the parameters other than the net channel doping level being unchanged. In another embodiment, the semiconductor circuit includes a first circuit including a first group of field effect transistors having a body. The circuit also includes a first voltage source to provide a first voltage to the body such that the field effect transistors have a forward body bias, the first voltage being at a level leading to the circuit experiencing a reduced rate of soft error failures as compared to when the circuit is not forward biased.

A method of fabricating a transistor of a semiconductor device is disclosed. The method of fabricating a transistor comprises forming a sacrificial layer on a substrate; forming a source/drain region in the substrate by performing a first ion implantation using the sacrificial layer as a mask; forming a barrier layer over the substrate with the sacrificial layer; removing a portion of the sacrificial layer to form an opening through which a portion of the substrate is exposed; performing a second ion implantation using the opening as a mask to implant ions for adjustment of a threshold voltage of the substrate; forming a gate electrode on the substrate exposed through the opening; and performing a third ion implantation to adjust doping concentration in the gate electrode. Accordingly, the present invention can reduce the occurrences of a short channel effect and a reverse short channel effect in a transistor.

The invention discloses a method for manufacturing a semiconductor device layer. The method comprises the following steps of: after a well is formed on a substrate of a semiconductor device, forming an isolation shallow trench, and forming a grid on the substrate of the semiconductor device; performing ion implantation of carbon impurity on the grid and the substrate of the semiconductor device; after the surface of the grid and the surface of the substrate of the semiconductor device are re-oxidized, performing light dope on the grid and the substrate of the semiconductor device to form a shallow junction on the substrate of the semiconductor device; forming a nitrogen oxide side wall of the grid, doping the grid and the substrate of the semiconductor device, and performing deposition on the semiconductor device to form a drain and a source; and depositing metals on the surface of the grid and the semiconductor substrate by adopting a self-alignment silicide method to form metalized silicon layers, then performing quick annealing treatment, and etching the un-reacted metals. The method can effectively reduce the transient enhanced diffusion (TED) generated in the re-oxidation process of the grid so as to remarkably prevent the short trench of the semiconductor device from generating short channel effect (SCE) and reverse short channel effect (RSCE).

The invention discloses a forming method of an N-channel metal oxide semiconductor (NMOS) transistor, which comprises the following steps of: providing a semiconductor substrate which is divided into an isolation region and an active region; forming a doped well in the semiconductor substrate of the active region; forming a gate dielectric layer and a polycrystalline silicon gate on the semiconductor substrate of the active region in turn, wherein the gate dielectric layer and the polycrystalline silicon gate form a gate structure; re-oxidizing the gate structure; injecting ions into the semiconductor substrates on two sides of the gate by taking the gate structure as a mask to form a source/drain extension region; forming side walls on two sides of the gate structure, and then forming a Vt injection region in the semiconductor substrate; and forming source/drain electrodes in the semiconductor substrates on two sides of the gate structure and the side walls. The forming method ensures that ions of the Vt injection region of a channel region positioned below the gate are uniformly distributed to prevent a reverse short channel effect (RSCE).

The invention provides methods for improving a reverse narrow channel effect and manufacturing a metal oxide semiconductor (MOS) transistor. The method for improving the reverse narrow channel effect comprises the following steps of: providing a semiconductor substrate on which shallow trenches are formed in turn; forming a lining oxide layer on the inner wall of each shallow trench; and performing angular ion implantation on the side wall of the shallow trench. By the method, the reverse narrow channel effect of the MOS transistor is effectively improved.

Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off, at shorter channel lengths. The FDTB FET embodiments are configured with either an edge back-gate or split back-gate that can be biased in order to selectively adjust the potential barrier between the source/drain regions and the channel region for minimizing off-state leakage current between the drain region and the source region and/or for varying threshold voltage. These unique back-gate structures avoid the need for halo doping to ensure linear threshold voltage (Vtlin) roll-up at smaller channel lengths and, thus, avoid across-chip threshold voltage variations due to random doping fluctuations. Also disclosed are method embodiments for forming such FETs.

An electronic circuit (10) comprises at least two transistors (T12, T14) coupled in parallel, wherein the second transistor channel length is configured such that the threshold voltage of the second transistor (T14) is at a peak on a threshold voltage versus channel lengths curve arising from reverse short channel effects for a given semiconductor process. The first transistor (T12) is biased with a first gate-source voltage and a first drain-source voltage. The second transistor (T14) is biased with a second gate-source voltage and a second drain-source voltage. The first gate-source voltage and the second gate-source voltage are offset from each other by a gate-source voltage offset and the first drain-source voltage and the second drain-source voltage are offset from each other by a drain-source voltage offset. These bias conditions result in the transistors (T12, T14) operating in different regions so that the second and third-order nonlinearities of the transistors (T12, T14) substantially cancel each other out simultaneously.

The invention relates to self-alignment channel doping for restraining a CMOS (Complementary Metal Oxide Semiconductor) short channel effect and a preparation method thereof, which solve the following problems in the prior art: 1, doping of a source and a drain is compensated to cause the increase of parasitic resistances of the source and the drain; 2, profiles of PN junctions of a source substrate and a drain substrate are influenced to cause the increase of reversed biased leakage current of the source substrate and the drain substrate; and 3, the junction depth Xj of the PN junctions of the source substrate and the drain substrate can be increased to cause counteractive on the restraint on the SCE (Short Channel Effect). According to the self-alignment channel doping for restraining the CMOS short channel effect and the preparation method thereof, disclosed by the invention, self-alignment doping on CMOS device channel regions is realized, a heavy-doped buried layer under a channel is formed, and source and drain regions are not influenced, thus the SCE is effectively restrained, and the performances of devices are improved.

The invention provides a method for restraining the reverse short channel effect and a manufacturing method of an NMOS (N-Channel Metal Oxide Semiconductor) device. After phosphorus ions are injected into the drain region of a shallow doping source, a fluorine ion injection procedure is added, and low-temperature annealing long-time treatment is performed on the drain region of the shallow doping source. The injected fluorine ions are combined with vacancy and interstitial atoms and the like in a grid edge area, so that the diffusion of boron elements in a P-type well region can be prevented, and the reverse short channel effect is restrained. Moreover, the fluorine ions can restrain hot carrier injection, so that the reliability of hot carrier injection does not become poor while the fluorine ions are injected.

The invention discloses a sub-threshold digital circuit time sequence optimization method and system. The method comprises the following steps: firstly, determining a logic unit circuit capable of improving the performance by utilizing a reverse short channel effect; performing time sequence analysis on a given integrated circuit to obtain all signal paths which do not meet the time sequence requirement; then determining a plurality of main delay units capable of improving the performance by utilizing a reverse short channel effect in each signal path which does not meet the time sequence requirement; and finally, increasing the gate length of the device of the main time delay unit by using a reverse short channel effect according to a preset time sequence constraint condition to carry outadjustment, and adjusting the gate length size to optimize the time sequence of the sub-threshold digital circuit. According to the invention, the gate length of a device of a main time delay unit isincreased by using a reverse short channel effect, so that time sequence optimization is realized, the circuit performance of a sub-threshold digital circuit is improved, and the time delay time of the unit is reduced; and meanwhile, the consistency of unit delay is improved by increasing the area, so that the robustness of the circuit is enhanced.

A method of implementing a transistor circuit comprises coupling first and second transistors in parallel, wherein the first transistor has a channel length corresponding to a peak in the transistor's voltage threshold curve arising from reverse short channel effects, and the second transistor has a longer channel length and, therefore, a lower threshold voltage. Exploiting reverse short channel effects in this manner enables the implementation of 'composite' transistor circuits that exhibit improved linearity.