33 results about "Reverse short-channel effect" patented technology

Techniques for gate workfunction engineering using a workfunction setting material to reduce short channel effects in planar CMOS devices are provided. In one aspect, a method of fabricating a CMOS device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. A patterned dielectric is formed on the wafer having trenches therein present over active areas in which a gate stack will be formed. Into each of the trenches depositing: (i) a conformal gate dielectric (ii) a conformal gate metal layer and (iii) a conformal workfunction setting metal layer. A volume of the conformal gate metal layer and / or a volume of the conformal workfunction setting metal layer deposited into a given one of the trenches are / is proportional to a length of the gate stack being formed in the given trench. A CMOS device is also provided.

An innovative dual-port subthreshold static random access memory (SRAM) cell for sub-threshold voltage operation is disclosed. During write mode, the dual-port subthreshold SRAM cell would cut off the positive feedback loop of the inverters and utilize the reverse short-channel effect to enhance write capability. The single-ended read / write port structure further reduces power consumption of the lengthy bit line. Therefore, the dual-port subthreshold SRAM cell is a suitable for long operation in a first-in first-out memory system. Although the lower voltage reduces the stability of the memory cell, the dual-port subthreshold SRAM cell of the present invention can still stably operate.

A semiconductor device including an NMOSFET which has an n-type source / drain main region containing arsenic and an n-type source / drain buffer region having arsenic and phosphorous of which a concentration is lower than that of the source / drain main region, and the concentration of the phosphorous in the source / drain buffer region is smaller than the concentration of the arsenic therein. The semiconductor device has a suppressed reverse short channel effect and reduced p-n junction leakage current. Further, the semiconductor device has a larger margin to a certain gate length and a specified threshold voltage to elevate a production yield.

Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off, at shorter channel lengths. The FDTB FET embodiments are configured with either an edge back-gate or split back-gate that can be biased in order to selectively adjust the potential barrier between the source / drain regions and the channel region for minimizing off-state leakage current between the drain region and the source region and / or for varying threshold voltage. These unique back-gate structures avoid the need for halo doping to ensure linear threshold voltage (Vtlin) roll-up at smaller channel lengths and, thus, avoid across-chip threshold voltage variations due to random doping fluctuations. Also disclosed are method embodiments for forming such FETs.

A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased.

The invention relates to a high-integration, high-mobility source-drain-gate assisted junction-free transistor, which adopts two independently controlled gate electrodes, such as a source-drain control gate electrode and a gate electrode, so that the device can be guaranteed at a low doping concentration. High mobility can be achieved in the channel, avoiding the decline of device mobility and stability caused by the enhancement of random scattering effect under high doping concentration, and at the same time, a lower source can be obtained through the independent control of the source-drain control gate electrode and the gate electrode. Leakage resistance, thus effectively solving the contradiction between the increase of the source-drain resistance caused by the low doping concentration of the channel of ordinary junctionless transistors, and the high doping concentration will lead to the decrease of device mobility and stability. In addition, by adopting the groove-shaped channel design, compared with the ordinary planar structure, the effective channel length is significantly increased without increasing the additional chip area to reduce the short channel effect of the device at the deep nanoscale, so it is suitable for Promote apps.

The invention provides a method for restraining the reverse short channel effect and a manufacturing method of an NMOS (N-Channel Metal Oxide Semiconductor) device. After phosphorus ions are injected into the drain region of a shallow doping source, a fluorine ion injection procedure is added, and low-temperature annealing long-time treatment is performed on the drain region of the shallow doping source. The injected fluorine ions are combined with vacancy and interstitial atoms and the like in a grid edge area, so that the diffusion of boron elements in a P-type well region can be prevented, and the reverse short channel effect is restrained. Moreover, the fluorine ions can restrain hot carrier injection, so that the reliability of hot carrier injection does not become poor while the fluorine ions are injected.