4results about How to "Short delay time" patented technology

The invention discloses a method and a device based on Interlanceamp. The invention discloses an infrared detector driving imaging method in a Binning mode. According to the method, a pair of complete image data is generated, a detector needs to carry out integration operation twice, and effective data of different subframes can be generated after each time of integration is completed. Effective data generated by the first integration is a first sub-frame, and the sub-frame is all even-numbered lines of the complete image. Effective data generated after the second integration time is completed are second subframes, and the subframes are all odd-numbered lines of the complete image. According to the method, image data of a first sub-frame and image data of a second sub-frame output by an infrared detector are cached respectively, odd-even row sorting, time sequence recombination processing and the like are carried out on cached effective image data of the first sub-frame and the second sub-frame, and finally a complete image with the size of 640 * 512 is obtained. And the image is finally output through an image format of a camera link interface protocol.

This invention relates to aircraft propulsion systems, specifically to an online real-time monitoring system and method for aircraft solenoid valves and self-locking valves. The system provided by this invention comprises a host computer, valve testing equipment, solenoid valves and / or self-locking valves, a solenoid valve and / or self-locking valve actuator, GNC monitoring equipment, cables, and network cables. The solenoid valve and / or self-locking valve actuator, GNC monitoring equipment, and solenoid valves and / or self-locking valves are connected to the valve testing equipment via cables; the valve testing equipment is connected to the host computer via a network cable. This connection method integrates the valve testing equipment with the solenoid valve and / or self-locking valve control pathways, enabling long-term online real-time monitoring of the solenoid valve and / or self-locking valve's operational characteristics data, eliminating the need for offline, post-processing interpretation. Furthermore, this invention offers advantages such as multiple parallel testing pathways, high time accuracy, long operating time, strong versatility, high real-time performance, strong compatibility, and low latency.

The invention discloses an event-driven airborne embedded task application framework design method, which comprises the following steps of: creating an application task thread, and creating a corresponding event signal and a business event queue; creating an auxiliary task thread to carry out application task thread heartbeat management and application timer list management; the task service module generates an application message event by releasing an application buffer message, stores the application message event into a corresponding service event queue and triggers a corresponding event signal; the task service module registers an application timing processing function by creating an application timer and updates the function to an application timer list, after the application timer is started, an auxiliary task thread periodically judges whether the application timer expires or not, and an application timing event is generated when the application timer expires; the application software task thread waits for the event signal, when the event signal is triggered, if the application message event is obtained from the service event queue, application message event processing is executed, and if the application timing event is obtained from the application timer list, application timing event processing is executed.

This invention relates to the field of analog integrated circuit design, specifically to an adaptive comparator delay loop SAR ADC applicable to ultra-high-speed SAR ADCs. Based on the inconsistency in the MSB-LSB setup time within the DAC capacitor array, this invention adjusts the number of adjustable delay stages N in the loop delay module. This allows the comparator to adjust the reset time T for each subsequent comparison after the first comparison. CMP_RST By matching the DAC voltage establishment time, the comparator loop delay is adaptively adjusted to reduce the comparator loop delay time. Depending on the different designs of the delay stages N in the adaptive adjustment module, the time utilization rate can reach 100%. This invention minimizes the comparator loop delay time to the greatest extent while ensuring accurate DAC voltage establishment.