1results about How to "Short delay time" patented technology

This invention relates to the field of analog integrated circuit design, specifically to an adaptive comparator delay loop SAR ADC applicable to ultra-high-speed SAR ADCs. Based on the inconsistency in the MSB-LSB setup time within the DAC capacitor array, this invention adjusts the number of adjustable delay stages N in the loop delay module. This allows the comparator to adjust the reset time T for each subsequent comparison after the first comparison. CMP_RST By matching the DAC voltage establishment time, the comparator loop delay is adaptively adjusted to reduce the comparator loop delay time. Depending on the different designs of the delay stages N in the adaptive adjustment module, the time utilization rate can reach 100%. This invention minimizes the comparator loop delay time to the greatest extent while ensuring accurate DAC voltage establishment.