42 results about "Fifo queue" patented technology

The invention discloses a multi-camera synchronization method, device and equipment and a computer readable storage medium. The method comprises the following steps: a frame synchronization signal generation unit generates a frame synchronization signal and sends the frame synchronization signal to a timestamp generation unit and N cameras, wherein N is a positive integer greater than or equal to 2; when the timestamp generation unit receives the frame synchronization signal, the timestamp at the current moment is put into an FIFO queue corresponding to each camera; when each camera receives the frame synchronization signal, executing a shooting action; and the forwarding unit reads the timestamps from the FIFO queues corresponding to the cameras when receiving image data obtained by each camera based on the shooting action, and sends the image data and the read timestamps to an image processing end. According to the method and the device, the plurality of cameras can synchronously execute the shooting action, and the image processing end at the rear end can accurately determine the synchronously exposed image data.

The invention provides a TCAM-based message header data processing method and related equipment, and the method comprises the steps: caching and inputting message header data through an FIFO queue, and scheduling the message header data to a message header processing assembly line composed of a TCAM memory, an RAM memory and a parallel processor through an arbiter; a round processing mechanism is combined and adopted, a lookup key value of the current round is matched with an index value in a TCAM in each round of processing, an action table in an RAM is read according to the index value, and a message header analysis instruction of the current round, a group key instruction of the next round and a jump state value of the next round are obtained; executing the instruction through the parallel processor to obtain and update message metadata; when each round is finished, whether the round is finished or not is judged based on the jump state value of the next round; and after the round is finished, outputting the obtained final message metadata by the order-preserving cache queue. According to the invention, the message header data is analyzed by using the TCAM-based data processing technology, so that the flexibility of message header analysis is improved.

The invention discloses a design method, device and equipment of a many-core processor architecture and a storage medium, and relates to the technical field of distributed computing. Comprising the steps of 1, dividing all cores into groups, 2, integrating a CPU assembly line, an intra-core private memory, a hardware FIFO queue and a DMA engine in each core, 3, labeling the cores in each group according to coordinates, storing shared data of processors in the group by using an intra-group shared memory, and storing the shared data of the processors in the group. The method comprises the following steps: step 1, transmitting and receiving an NoC data packet through an intra-group main core control inter-group communication interface for intra-group communication, and step 4, planning an inter-group optimal transmission path for inter-group communication according to the transmitted core coordinates of a source processor group and a target processor group. According to the method, the shortest path between the groups is automatically calculated, and NoC transmission is dynamically optimized; hardware FIFO and a DMA engine are adopted to realize low-delay data transmission, and a main core efficiently exchanges data among groups through an NoC to realize response.

The invention provides an FIFO (First In First Out) data reading method, device, system, equipment and medium, the method comprises the following steps: when a data reading request is triggered, calculating a read address according to a data reading address carried in the data reading request; the read address is used for representing a value when the read address register is about to be updated in the previous clock period; selecting target data from the next beat of data of the register file or the beat-to-write data through the multiplexer according to the beat-to-read address; the next beat of data of the register file refers to data stored in the register file in the next clock period; the current data are data which are currently written into a first-in first-out (FIFO) queue; and performing a beating operation on the target data through a register, and performing a reading operation through a data reading interface of the FIFO queue. According to the scheme, the overall delay of data reading is reduced, the running speed and performance of the whole system are improved, and then the running speed of a chip is increased.

The invention provides a self-adaptive data packet scheduling method based on approximate quantiles and multiple queues on a programmable data plane, and aims to solve the problem that the scheduling performance and the resource efficiency are difficult to balance in the prior art. According to the method, lightweight ranking scoring, dynamic queue mapping and a cascade enqueue strategy are combined. A relative priority score of the data packet is efficiently calculated through a minimum-maximum normalization mechanism; adaptively mapping the data packets to one of a plurality of FIFO queues according to the scores and real-time congestion conditions of the queues, and providing a fast channel for extremely high priority traffic; and when the target queue is full, trying to store the data packet into a queue with a lower priority in a cascading manner so as to avoid unnecessary discarding. According to the method, resource consumption and implementation complexity are remarkably reduced while the approximate ideal PIFO scheduling performance is achieved, and the method is particularly suitable for resource-limited environments such as a software-defined network and edge computing.

The present invention is related to a method and a computer program code for handling requests in a multi-core system. In a first step, a request for a globally shared resource is received (S1) from a task belonging to a processing core. In case a FIFO queue associated with the globally shared resource is empty, the request is satisfied (S2). In case the FIFO queue associated with the globally shared resource is not empty, the request is queued (S4) in the FIFO queue. When the queued request reaches the head of the FIFO queue, the task is treated (S6) as eligible to enter the respective critical section. The invention is further directed towards a multi-core system using such a method.

The invention discloses a high-speed Ethernet communication node secondary queue message receiving method and a high-speed Ethernet communication node secondary queue message receiving system, which enable a high-speed Ethernet communication node to send messages by adopting multiple links, improve independence among subsystem applications in a multi-core and multi-task scene, avoid mutual exclusion operation of critical resources of a sending queue, and improve the service life of the high-speed Ethernet communication node. The execution efficiency of a message sending interface is optimized, and the network throughput rate and the network bandwidth of the high-speed Ethernet can be developed; the blocking operation of each partition application in the partition system caused by the message sending access sending queue and descriptor is effectively avoided, the execution time of the partition application message sending is further optimized and improved, the receiving buffer area is managed by adopting the receiving idle FIFO queue, the receiving buffer area does not need to be dynamically managed by applying for a large buffer pool, and the message sending efficiency is improved. Therefore, the overhead of memory resources is reduced, and the system overhead caused by applying or releasing the receiving buffer area is also avoided; and the network communication bandwidth and throughput are improved, and the capacity expansion and speed increase of the network are facilitated.

Disclosed in the present application are a data reading method and apparatus for an MSC interface. The method comprises: acquiring data reading state information of an MSC interface, and the number of instructions in a FIFO queue; and on the basis of the state information and the number of instructions, generating a control strategy set, wherein the control strategy set comprises at least one of the following: controlling the MSC interface to send a reading instruction and controlling the data reading state of the MSC interface to be a busy state; controlling a reading instruction to be sent to join to the FIFO queue at the tail; controlling the MSC interface to send a reading instruction located at the head of the FIFO queue and controlling the data reading state of the MSC interface to be a busy state; and controlling the data reading state of the MSC interface to be an idle state. The present application solves the technical problem of unstable data reading caused by the inconsistency in uplink and downlink rates of an MSC interface.

The invention provides an MQTT message processing method based on combination of FIFO and priority scheduling, which optimizes the sending and response of MQTT messages in Internet of Things communication by a concentrator, ensures that a system has good stability, real-time performance and fault-tolerant capability, and improves the reliability of the system. Comprising a retransmission strategy of a synchronization request, timeout processing logic and a verification and priority processing mechanism for a received synchronization response message, and is suitable for structured communication based on MQTT among a plurality of application programs or modules. A common MQTT message FIFO combined priority scheduling scheme is a message processing mechanism considering both efficiency and fairness, not only retains the sequence and predictability of a traditional FIFO queue, but also introduces a flexible priority scheduling mechanism, so that a concentrator can dynamically adjust the message processing sequence according to different service scenes, and the message processing efficiency is improved. And the response speed, stability and resource utilization rate of the system are obviously improved.

The invention provides a radar echo simulation method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining a radar signal, copying the radar signal, and obtaining a first signal and a second signal; according to the target speed and the target distance in the scene, the echo time delays of the current beat and the next beat are solved, and a solving result is obtained; respectively receiving the first signal and the second signal through an FIFO queue according to a resolving result; according to the time takt, the first signal and the second signal in the FIFO queue are stored and read in a circulating switching mode, and a radar echo simulation result is obtained. The method has the beneficial effect that the accuracy of Doppler radar testing and calibration is improved.

The application discloses a logical time management service method and system for joint tests, wherein participants set time control strategies and time limited strategies, and initiate logical time advancing requests and request processing callback requests to middleware according to preset time steps, and register callback functions; a time adjuster calculates a timestamp lower limit to provide data guarantee for time advancing; the middleware receives the logical time advancing requests, checks whether the participants have the right of the time control strategies, updates the current timestamp lower limit, receives the processing callback requests, checks FIFO queues and processes queue messages, checks the time limited strategies of the participants, checks TSO queue states and processes queue messages, checks the relationship between the time requested by the participants and the timestamp lower limit, and calls the callback functions allowed by the time advancing to the participants; the application provides an efficient and accurate logical time management mechanism, and solves the problem that the middleware of the existing joint test platform does not support logical time management.

The invention relates to a CAN gateway high-load-rate frame loss prevention method and device, equipment and a medium, and belongs to the technical field of automobile electronic communication. The CAN gateway high-load-rate frame loss prevention method comprises the following steps: if a target hardware mailbox needs to send message data and the target hardware mailbox is in a non-idle state, writing the message data to be sent into a circular FIFO queue for caching; the circular FIFO queue is an independent queue set for each CAN controller channel and is used for caching to-be-sent message data when a target hardware mailbox is not idle; and after the message data stored in the target hardware mailbox is sent, triggering and transmitting a sending completion interrupt signal, and writing the to-be-sent message data cached in the circulating FIFO queue into the target hardware mailbox for sending. According to the scheme, the problems of frame loss and high CPU occupation in a high-load scene are solved through a mechanism of circulating FIFO queue caching and interrupt triggering type sending, and a communication guarantee with functional safety and system stability is provided for the vehicle-mounted ECU.

The invention discloses a management system compatible with an advanced cache algorithm in a content distribution network CDN. The management system comprises an Inode table, an algorithm library, a multi-stage FIFO queue, a controller and a recovery pool, the Inode table is a hash table stored in a memory and is used for quickly associating key information of each data object; the algorithm library comprises a plurality of cache strategies based on lists, and the cache strategies are processed as priority queues; the multi-level FIFO queues construct a layered storage structure, and each FIFO queue is used for managing a storage device strip; the controller is based on an in-memory cache simulator, and the working process comprises a preprocessing stage and a real-time adjustment stage; and the recycling pool is used for storing and managing the virtual stripes and the physical stripes. According to the system, the problems of write amplification and significant overhead caused when a traditional cache algorithm is applied to persistent storage can be solved, the requirement of high hit rate can be considered, and the I / O overhead can be effectively reduced.

The application relates to the technical field of production line data processing, in particular to a pharmaceutical appearance high-speed detection data processing method and system. Through multi-cooperative innovation, high-speed and high-precision detection and rejection of aluminum-plastic blister medicines are realized. A self-defined message structure is adopted to compactly encapsulate key information such as a starting point pulse, a defect mark and a rejection state, direct offset addressing of PLC is supported, analysis overhead is saved, and data processing delay is greatly reduced. A FIFO queue and an encoder pulse binding mechanism are constructed to ensure that the position data of each product is not lost, and the loss rate of position data is greatly reduced. A rejection closed-loop verification system is established, three-way matching of rejection action feedback, a downstream residual sensor and an encoder position is realized, whether rejection is truly completed is determined in a confirmation area, and the quality and automation reliability of medicine packaging are significantly improved.

The invention relates to a software configurable processor device. A software configurable processor device includes a plurality of processor cores having respective storage elements configurable to implement one or more first-in first-out (FIFO) queues or first-level (L1) cache blocks for respective processor cores of the plurality of processor cores. Configuration hardware is provided to configure a first storage element associated with a first processor core of the set of processor cores based on a configuration definition of the processor device to implement a set of FIFO queues for the first processor core in the first storage element.

This invention discloses a dynamic weighted resource allocation method based on a FIFO queue, relating to the field of resource scheduling technology. The method includes: S1, real-time collection of connection queue monitoring data and preprocessing of the data; S2, identification of pre-order blocking requests corresponding to each request and further calculation of the pre-order blocking propagation value; S3, calculation of connection contention constraint values ​​corresponding to each request, and determination of the blocking type for each request based on the pre-order blocking propagation value; S4, calculation of the FIFO order compensation value and dynamic weight allocation value corresponding to each request, determination of the priority request set for this round, and then, based on the blocking type, execution of connection acquisition qualification allocation and generation of the next round's priority retention flag, outputting dynamic weighted resource allocation data. This method solves the problem of inaccurate characterization of pre-order blocking propagation in existing shared connection resource allocation processes, leading to an imbalance in connection acquisition qualification allocation under a FIFO queue.

The present invention relates to the field of integrated circuit technology, and specifically discloses an AXI bus matrix interface based on a priority queue, which includes a data encapsulator, a priority decoder, a first data distributor, a second data distributor, a plurality of FIFO queues, a first data selector, a second data selector, and a priority arbiter. Among them, the data encapsulator is connected to the first data distributor, the priority decoder is respectively connected to the first data distributor, the second data distributor, and the second data selector, each FIFO queue is respectively connected to the first data distributor, the second data distributor, the first data selector, the second data selector, and the priority arbiter, and the priority arbiter is connected to the first data selector. The present invention can perform priority decoding and scheduling on transactions, so as to ensure that transactions with higher priorities are processed first, eliminate the priority inversion problem, and improve the real-time performance of the system.

The present invention discloses a design method, device, equipment and storage medium for a many-core processor architecture, relating to the field of distributed computing technology. The design method comprises the following steps: 1: dividing all cores into groups; 2: integrating a CPU pipeline, an intra-core private memory, a hardware FIFO queue and a DMA engine within each core; 3: labeling the cores within each group according to their coordinates, storing shared data of the processors within the group using the intra-group shared memory, and controlling the inter-group communication interface through the intra-group master core to transmit and receive NoC data packets for intra-group communication; and 4: planning an optimal inter-group transmission path based on the coordinates of the cores of the source processor group and the target processor group for transmission, for inter-group communication. The present invention dynamically optimizes NoC transmission by automatically calculating the shortest path between groups. The hardware FIFO and DMA engine are used to achieve low-latency data transmission, and the master core exchanges data efficiently between groups through the NoC to achieve response.

The invention relates to a packing method and system for improving cross-DIE transmission efficiency and a storage medium, and the method comprises the steps: selecting an assembly line through an arbiter according to a preset assembly line arbitration level; fIFO queue depths of items contained in a request transmission channel, a response transmission channel and a data transmission channel are read, the number of available items is recorded through a first counter, and the number of sent items is recorded through a second counter; according to the values of the first counter and the second counter, determining an optimal format for entry packaging; reading entries from different FIFO queues according to the optimal format and writing the entries into slots corresponding to the frame segments; and transmitting the packed frame segments to a packing transmitter, and further transmitting the packed frame segments to a physical layer of the assembly line so as to complete packing transmission. According to the method, assembly line two-way fairness, multi-channel queuing fairness, channel flow control and tradeoff between the packing utilization rate and delay are achieved from packing logic, and the high-frequency time sequence requirement of the DIE assembly line is met.

The embodiment of the invention discloses a data caching circuit and method, a processor, electronic equipment and a chip product, and relates to the technical field of electronics. The data caching circuit comprises a static random access memory (SRAM) which is provided with a plurality of virtual first-in first-out queues; a plurality of input registers for storing valid data sent by an upstream circuit; wherein one input register corresponds to one virtual first-in first-out queue; and the first arbiter is used for determining a first target virtual FIFO queue from the plurality of virtual FIFO queues and controlling effective data in the input register corresponding to the first target virtual FIFO queue to be transmitted to the first target virtual FIFO queue for storage. According to the embodiment, the hardware area can be reduced under the condition of realizing data caching.

This invention provides a PCI planning method, apparatus, electronic device, and storage medium, belonging to the field of communication technology. The method includes: triangulating a target area to determine the topology of base stations; selecting an unplanned base station and adding it to a first-in-first-out (FIFO) queue; designating the first base station in the FIFO queue as the target base station; determining the degree of influence between the cells to be planned under the target base station and each neighboring cell based on the topology; determining the PCI of the cells to be planned based on each degree of influence; after determining the PCI of all cells under the target base station, adding the unplanned base stations adjacent to the target base station to the FIFO queue in sequence, and returning to the step of designating the first base station in the FIFO queue as the target base station, until the FIFO queue is empty. This invention can realize batch PCI planning of contiguous base stations within a region, improving PCI planning efficiency.

The invention discloses a data prefetching method and device based on a PSRAM, a medium and a program product, and belongs to the technical field of data storage. Before the bus sends out a first request for reading data stored in the pseudo-static random access memory, issuing second request information to a register for controlling a first-in first-out queue through the controller; and controlling the register of the first-in first-out queue to read data stored in the pseudo-static random access memory by taking the second initial address as a starting point according to the second request information, and storing the read data in the first-in first-out queue controlled by the register, the length of the data stored in the first-in first-out queue controlled by the register is the second reading length; and when the register for controlling the first-in first-out queue receives a first request sent by the bus, transmitting data to the bus from the first-in first-out queue controlled by the register according to a first initial address and a first reading length corresponding to the first request and a first-in first-out reading rule.

The invention provides a method for supporting large-capacity SDH virtual cascade grouping on an FPGA chip, and belongs to the technical field of optical transmission. The method comprises the following steps of: creating a shared cache region on an FPGA (Field Programmable Gate Array), and sharing the shared cache region for all virtual cascade groups; the shared cache region comprises a blocky RAM (Random Access Memory) cache region and an RAM management unit; the block RAM cache region is obtained by all block RAM sets used for processing virtual cascade group data reduction on the FPGA chip; and the RAM management unit dynamically applies for a cache region for the virtual cascade group according to the number of members of the virtual cascade group, and is provided with a logic initialization module, a management FIFO queue and a resource use counter. The method provided by the invention can support the processing of a larger number of virtual cascade packets, and can also support the processing of a larger access bandwidth at the same time, thereby avoiding the problem that hardware can only be expanded due to excessive virtual cascade packets of access signals in a practical application scene.

The invention belongs to the related technical field of hardware acceleration, and particularly relates to a hardware acceleration system and method oriented to large model reasoning, and the system comprises an FPGA reasoning acceleration module; according to calculation dimensions of different stages in the reasoning process, a linear calculation kernel, a multi-head attention calculation kernel, a feedforward neural network layer calculation kernel and a quantization normalization and residual connection kernel are divided; the four cores are distributed in different SLR regions of the FPGA, and the whole of each core is located in the same SLR region; hardware-level FIFO queues are integrated at data transmission interfaces among the cores; blocking type data flow control logic is adopted, each kernel autonomously starts or pauses calculation operation of the kernel only according to data availability of an input queue and space availability of an output queue of the kernel, a calculation result is directly pushed to an input queue of a downstream kernel, and a self-triggering execution chain based on data flow is formed. According to the method, the problems of relatively low reasoning efficiency and high resource consumption of the edge scene under the word element sequence can be solved.

Methods and systems for managing a first-in-first-out (FIFO) queue. A method includes receiving an end pointer and a done count from a producer. The method includes reading multiple values from memory: a checkpoint location in the FIFO queue, a count of data items marked complete before the checkpoint, an offset of the furthest location written to, and a total number of data items written. The method calculates new values for these parameters, and calculates a location within the FIFO queue prior to which all data has been written, and is therefore safe to consume. The method handles various forms of wrapping. This process ensures efficient tracking and management of data items within the FIFO queue, facilitating accurate and timely updates to the queue's state.

A system for a wearable personal inside-out location tracking may include a hands-free wearable display configured to display augmented reality optics among other navigation-related visualizations, a camera and an inertial sensor, and a personal computing system. The personal computing system may be configured to store information and perform computations relating to a method for personal location tracking. Such a method may include initializing a personal navigation history comprising a first-in-first-out (FIFO) queue, inserting into the FIFO queue a waypoint in an order generated by a personal tracking system, generating a cone of visibility by pruning the user's personal navigation history according to a parametric model representing both an egocentric visibility constraint and an environment constraint, and determining a backtracking route based on the cone of visibility. Visualization data may be generated based on the backtracking route, resulting visualizations meant to guide a user back to an origin location.

A network device (1) for packet switching according to bounded end-to-end latency is disclosed. The network device comprises a plurality (11) of first-in first-out (FIFO) queues, the number of FIFO queues being n, the plurality of FIFO queues being serviceable according to a polling-based service policy and a fixed packet processing time (T). A respective queue of the plurality of FIFO queues is associated with a bounded latency (Dmax), which depends on a service policy of the plurality of queues and is a function of an adjustable buffer capacity (Be) of the respective queue. The network device further comprises a processor (12) configured to: determine a threshold crossing of a reserved range of buffer capacities for the respective queues; and adjusting the buffer capacity of the corresponding queue according to the determined threshold crossing. This enables network devices of the network to balance QoS and capacity locally in a distributed manner without the need for a centralized controller.

Disclosed are an asynchronous FIFO read / write control method and system, and an electronic device, belonging to the technical field of data read / write technology. The asynchronous FIFO read / write control method comprises: parsing data received by a front-end interface to obtain a data packet length and valid video data; determining an almost empty threshold of a first FIFO queue and a second FIFO queue according to the data packet length, and writing the valid video data into the first FIFO queue and the second FIFO queue in a ping-pong manner; determining a minimum time interval of FIFO readings according to a sending time sequence of a back-end interface, and reading data from the first FIFO queue and the second FIFO queue in the ping-pong manner according to the almost empty threshold and the minimum time interval, so as to output the read data through the back-end interface.

The embodiment of the invention discloses a satellite communication transmission optimization method and device, electronic equipment and a storage medium, and relates to the technical field of satellite communication and data transmission optimizing.The method comprises the steps that a stream context table is inquired by extracting a data packet head quintuple, and a new stream is created and synchronously updated when the data packet head quintuple is not hit. An ROHC compressor is used for compressing the head of a data packet, a compressed data segment containing a CID is generated and stored in an FIFO queue, after the size or duration condition is met, the compressed data segment is packaged into an aggregation frame, and FEC coding is added for sending, so that the transmission redundancy is reduced, and the transmission efficiency is improved for a high-error-code long-delay environment. By dynamically increasing the number of IR packet sending times, the state of a compressor is adaptively adjusted, light NACK is sent, and a flow context table is periodically cleaned. And dividing priorities according to service types, configuring differentiated aggregation parameters, reading TCP layer state information in real time for dynamic adjustment, and marking an NACK packet as the highest priority. According to the invention, the problems of efficiency bottleneck and poor transmission robustness in the prior art are effectively solved.

This invention discloses a configurable routing distribution method for SSD controller command processing, belonging to the field of solid-state drive technology. The method includes: setting up a BXM module in the SSD controller; the BXM module includes an interface module, a two-layer routing table, a FIFO queue, processing nodes, and a crossbar switch; receiving commands through the host interface and generating data packets containing headers and payloads; the BXM module querying the two-layer routing table based on the operation reference field in the data packet header to determine the target engine and operation instructions; routing the data packets to the target engine for processing via the crossbar switch; repeating the routing and processing steps until all operation processes are completed and the final engine terminates processing, and the data packets are no longer forwarded. This invention uses the BXM module for routing, replacing traditional CPU-centralized processing, significantly reducing command processing latency and improving system energy efficiency.