16 results about "Fifo queue" patented technology

The invention provides a TCAM-based message header data processing method and related equipment, and the method comprises the steps: caching and inputting message header data through an FIFO queue, and scheduling the message header data to a message header processing assembly line composed of a TCAM memory, an RAM memory and a parallel processor through an arbiter; a round processing mechanism is combined and adopted, a lookup key value of the current round is matched with an index value in a TCAM in each round of processing, an action table in an RAM is read according to the index value, and a message header analysis instruction of the current round, a group key instruction of the next round and a jump state value of the next round are obtained; executing the instruction through the parallel processor to obtain and update message metadata; when each round is finished, whether the round is finished or not is judged based on the jump state value of the next round; and after the round is finished, outputting the obtained final message metadata by the order-preserving cache queue. According to the invention, the message header data is analyzed by using the TCAM-based data processing technology, so that the flexibility of message header analysis is improved.

The invention provides an MQTT message processing method based on combination of FIFO and priority scheduling, which optimizes the sending and response of MQTT messages in Internet of Things communication by a concentrator, ensures that a system has good stability, real-time performance and fault-tolerant capability, and improves the reliability of the system. Comprising a retransmission strategy of a synchronization request, timeout processing logic and a verification and priority processing mechanism for a received synchronization response message, and is suitable for structured communication based on MQTT among a plurality of application programs or modules. A common MQTT message FIFO combined priority scheduling scheme is a message processing mechanism considering both efficiency and fairness, not only retains the sequence and predictability of a traditional FIFO queue, but also introduces a flexible priority scheduling mechanism, so that a concentrator can dynamically adjust the message processing sequence according to different service scenes, and the message processing efficiency is improved. And the response speed, stability and resource utilization rate of the system are obviously improved.

The invention relates to a software configurable processor device. A software configurable processor device includes a plurality of processor cores having respective storage elements configurable to implement one or more first-in first-out (FIFO) queues or first-level (L1) cache blocks for respective processor cores of the plurality of processor cores. Configuration hardware is provided to configure a first storage element associated with a first processor core of the set of processor cores based on a configuration definition of the processor device to implement a set of FIFO queues for the first processor core in the first storage element.

This invention discloses a dynamic weighted resource allocation method based on a FIFO queue, relating to the field of resource scheduling technology. The method includes: S1, real-time collection of connection queue monitoring data and preprocessing of the data; S2, identification of pre-order blocking requests corresponding to each request and further calculation of the pre-order blocking propagation value; S3, calculation of connection contention constraint values ​​corresponding to each request, and determination of the blocking type for each request based on the pre-order blocking propagation value; S4, calculation of the FIFO order compensation value and dynamic weight allocation value corresponding to each request, determination of the priority request set for this round, and then, based on the blocking type, execution of connection acquisition qualification allocation and generation of the next round's priority retention flag, outputting dynamic weighted resource allocation data. This method solves the problem of inaccurate characterization of pre-order blocking propagation in existing shared connection resource allocation processes, leading to an imbalance in connection acquisition qualification allocation under a FIFO queue.

The embodiment of the invention discloses a data caching circuit and method, a processor, electronic equipment and a chip product, and relates to the technical field of electronics. The data caching circuit comprises a static random access memory (SRAM) which is provided with a plurality of virtual first-in first-out queues; a plurality of input registers for storing valid data sent by an upstream circuit; wherein one input register corresponds to one virtual first-in first-out queue; and the first arbiter is used for determining a first target virtual FIFO queue from the plurality of virtual FIFO queues and controlling effective data in the input register corresponding to the first target virtual FIFO queue to be transmitted to the first target virtual FIFO queue for storage. According to the embodiment, the hardware area can be reduced under the condition of realizing data caching.

The invention discloses a data prefetching method and device based on a PSRAM, a medium and a program product, and belongs to the technical field of data storage. Before the bus sends out a first request for reading data stored in the pseudo-static random access memory, issuing second request information to a register for controlling a first-in first-out queue through the controller; and controlling the register of the first-in first-out queue to read data stored in the pseudo-static random access memory by taking the second initial address as a starting point according to the second request information, and storing the read data in the first-in first-out queue controlled by the register, the length of the data stored in the first-in first-out queue controlled by the register is the second reading length; and when the register for controlling the first-in first-out queue receives a first request sent by the bus, transmitting data to the bus from the first-in first-out queue controlled by the register according to a first initial address and a first reading length corresponding to the first request and a first-in first-out reading rule.

The invention belongs to the related technical field of hardware acceleration, and particularly relates to a hardware acceleration system and method oriented to large model reasoning, and the system comprises an FPGA reasoning acceleration module; according to calculation dimensions of different stages in the reasoning process, a linear calculation kernel, a multi-head attention calculation kernel, a feedforward neural network layer calculation kernel and a quantization normalization and residual connection kernel are divided; the four cores are distributed in different SLR regions of the FPGA, and the whole of each core is located in the same SLR region; hardware-level FIFO queues are integrated at data transmission interfaces among the cores; blocking type data flow control logic is adopted, each kernel autonomously starts or pauses calculation operation of the kernel only according to data availability of an input queue and space availability of an output queue of the kernel, a calculation result is directly pushed to an input queue of a downstream kernel, and a self-triggering execution chain based on data flow is formed. According to the method, the problems of relatively low reasoning efficiency and high resource consumption of the edge scene under the word element sequence can be solved.

A system for a wearable personal inside-out location tracking may include a hands-free wearable display configured to display augmented reality optics among other navigation-related visualizations, a camera and an inertial sensor, and a personal computing system. The personal computing system may be configured to store information and perform computations relating to a method for personal location tracking. Such a method may include initializing a personal navigation history comprising a first-in-first-out (FIFO) queue, inserting into the FIFO queue a waypoint in an order generated by a personal tracking system, generating a cone of visibility by pruning the user's personal navigation history according to a parametric model representing both an egocentric visibility constraint and an environment constraint, and determining a backtracking route based on the cone of visibility. Visualization data may be generated based on the backtracking route, resulting visualizations meant to guide a user back to an origin location.

The embodiment of the invention discloses a satellite communication transmission optimization method and device, electronic equipment and a storage medium, and relates to the technical field of satellite communication and data transmission optimizing.The method comprises the steps that a stream context table is inquired by extracting a data packet head quintuple, and a new stream is created and synchronously updated when the data packet head quintuple is not hit. An ROHC compressor is used for compressing the head of a data packet, a compressed data segment containing a CID is generated and stored in an FIFO queue, after the size or duration condition is met, the compressed data segment is packaged into an aggregation frame, and FEC coding is added for sending, so that the transmission redundancy is reduced, and the transmission efficiency is improved for a high-error-code long-delay environment. By dynamically increasing the number of IR packet sending times, the state of a compressor is adaptively adjusted, light NACK is sent, and a flow context table is periodically cleaned. And dividing priorities according to service types, configuring differentiated aggregation parameters, reading TCP layer state information in real time for dynamic adjustment, and marking an NACK packet as the highest priority. According to the invention, the problems of efficiency bottleneck and poor transmission robustness in the prior art are effectively solved.

This invention discloses a configurable routing distribution method for SSD controller command processing, belonging to the field of solid-state drive technology. The method includes: setting up a BXM module in the SSD controller; the BXM module includes an interface module, a two-layer routing table, a FIFO queue, processing nodes, and a crossbar switch; receiving commands through the host interface and generating data packets containing headers and payloads; the BXM module querying the two-layer routing table based on the operation reference field in the data packet header to determine the target engine and operation instructions; routing the data packets to the target engine for processing via the crossbar switch; repeating the routing and processing steps until all operation processes are completed and the final engine terminates processing, and the data packets are no longer forwarded. This invention uses the BXM module for routing, replacing traditional CPU-centralized processing, significantly reducing command processing latency and improving system energy efficiency.

This invention discloses a processor speed-down tracing and debugging method, apparatus, device, and storage medium, relating to the field of computer technology and applied to a dual-core processor system. The method includes: caching the processor core's tracing data into a first-in-first-out (FIFO) queue using a data processing component in the system; monitoring the current cached data volume in the FIFO queue using a threshold detection component in the system; if the current cached data volume of a certain queue is not less than a threshold, then sending a speed-down prompt signal to the kernel control component and the corresponding data processing component in the system through the threshold detection component to slow down the corresponding processor core; until the current cached data volume of that queue is less than the threshold, then reverting to the step of caching the tracing data using the data processing component; and transmitting the tracing data in the FIFO queue to a debugger for analysis through an interface controller in the system. This invention improves the precision and debugging capabilities in kernel tracing and debugging.

The invention discloses a multi-camera high-speed synchronous imaging system and method based on an FPGA, and belongs to the technical field of industrial automatic visual inspection. The technical problem to be solved is that the prior art cannot give consideration to the triggering precision, the system real-time performance and the multi-target concurrent processing reliability at the same time. According to the technical scheme, the method is characterized in that FPGA hardware control is adopted, and an upper computer converts distance parameters of a sensor and a camera into encoder count values and configures the encoder count values to an FPGA; when the sensor detects a target, the FPGA latches the position of the encoder and writes the position into the FIFO queue A trigger position is calculated based on the absolute position, real-time parallel comparison is performed through a hardware circuit, and a trigger signal is output if conditions are met; the FIFO manages multiple targets according to a target detection sequence, data pops up after all cameras are triggered, multi-camera synchronous imaging with high precision and high real-time performance is achieved, and the system is easy to expand and adapts to high-speed assembly line detection.

The invention discloses an inter-core mutual exclusion method, an inter-core communication method, an inter-core interruption method and a terminal.The inter-core mutual exclusion method comprises the steps that a task is responded to initiate a resource access request, a priority label of the task is identified, and the task priority is determined according to the priority label; for the priority processing task, the priority processing task obtains a hardware spin lock through a preset instruction, and if the hardware spin lock obtaining operation is completed within a preset period, the hardware spin lock is obtained within a first preset delay time, and a watchdog timer is started; for the real-time / best effort processing task, the real-time / best effort processing task enters an MCS linked list queuing lock, a thread corresponding to the real-time / best effort processing task performs variable spinning in a local memory, the MCS linked list queuing lock is obtained within second preset delay time, and a watchdog timer is started; and during the lock holding period, the watchdog continuously monitors, and if the lock holding time exceeds a preset multiple of the worst task execution time, the lock is forcibly released and an alarm is given. According to the inter-core mutual exclusion method, an MCS linked list queuing lock is adopted to replace a traditional spin lock when tasks are processed in real time or as much as possible, disordered competitive self-rotation is converted into FIFO queue waiting, a precursor node only spins locally and actively notifies a subsequent node, the problems of bus cache consistency storm and hunger are thoroughly solved, and fairness and predictable delay of multi-core access are guaranteed.

The application relates to a planning method for realizing quick response and smooth following of a mechanical arm in cooperation with a sampler, comprising the following steps: acquiring position data of the sampler, wherein the position data comprises position information at multiple time points and a sampling interval of position information at adjacent time points; performing timeout denoising on the position data of the sampler according to the sampling interval, to obtain denoised position data; storing the filtered position data into a FIFO queue with a fixed length; determining a differential speed of a median value, position information of the median value and a speed stability value; determining a target position and a target speed of each trajectory planning segment based on the differential speed of the median value, the position information of the median value and the speed stability value; and planning each trajectory planning segment according to the target position and the target speed, to obtain a planning trajectory of each trajectory planning segment. The method can make the response speed of the mechanical arm relatively fast and smooth, and can realize linkage control of quick and smooth following in cooperation with the sampler.

This invention discloses a dual BFS hardware accelerator for sparse matrix RCM reordering, belonging to the field of sparse matrix computation and hardware acceleration technology. The accelerator includes: a top-level control module, a BFS engine module employing a dual BFS positioning architecture, a degree table module, a neighbor sorter module with a degree-first comparison network, a single-cycle access marker bit vector, and a hardware stack manager module. The BFS engine module achieves automatic pseudo-peripheral node positioning through a three-stage pipeline: the first stage starts BFS from the node with the lowest degree and finds the first farthest node through a hierarchy tracing circuit; the second stage starts BFS again from that node to determine the globally optimal starting point; and the third stage executes degree-first RCM traversal. An extended FIFO queue is used to transmit hierarchy information, and an external memory is interacted with through a decoupled interface. The hardware stack manager achieves single-cycle reverse output. This invention achieves a processing latency of less than 1.2ms on a 1000-node graph, reducing the average matrix bandwidth by 73.85%, and improving upon existing software by 31.85%.

The application relates to the field of underground safety monitoring of coal mines, and discloses an underground STM32F407 laser radar point cloud data acquisition, storage and transmission system, which comprises a core control unit, a power management unit and a data acquisition, storage and transmission interface unit. The core control unit adopts STM32F407, a three-level buffer management architecture is constructed, the rate matching problem of high-speed acquisition and low-speed writing of an SD card is solved through DMA ring buffer, ping-pong processing and FIFO queue. The power management unit is integrated with super capacitors, the core control unit executes power-off protection logic based on a voltage threshold value, and forced data landing is completed by using standby power. The system also has functions of roadway deformation edge calculation monitoring, CAN bus dynamic priority scheduling and large data packet fragmentation and recombination. Through hierarchical fault self-recovery and physical protection design, the system realizes real-time capture, reliable storage and stable transmission of massive point cloud data in the underground.