Ethernet exchange chip output queue management and dispatching method and device

A technology of output queues and switching chips, applied in data exchange networks, data exchange through path configuration, transmission systems, etc., can solve problems such as inability to provide service quality, affecting queue resource usage, data frame selection and discarding, etc., to achieve low cost. , improve practicality, and reduce the effect of mutual influence
CN1411211AInactive Publication Date: 2003-04-16HISILICON TECH

Patent Information

Authority / Receiving Office
CN Β· China
Current Assignee / Owner
HISILICON TECH
Publication Date
2003-04-16
Estimated Expiration
Not applicable Β· inactive patent

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Abstract

A management method and device of Ethernet chip output quene is that a single / multi message control separation module outputs queue from the frame control module based on single, multimessage separation way of each interface, the single data frame control module sets single-message queue in mode with multiple priority queue and uses congestion control algorithm to safeguard the single queue, the multiple one organizes in a way of FIFO queue to apply congestion control algorithm to directly discard queue end then carry out single / multi message priority quene matched arrangement. After interface dispatch between interfaces and priority dispatch inside interface in output quene dispatches, if single / multiple in priority.
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Description

[technical field]

[0001] The invention relates to electrical digital data processing technology and equipment, in particular to a method and device for managing and scheduling an output queue of an Ethernet switching chip. [Background technique]

[0002] The forwarding process of the shared buffer Ethernet switch chip working in the store-forward mode can be described as follows with the following processing steps, as shown in Figure 1:

[0003] 1. Receive and cache data frames: The data frames entering the switch chip from the external port are cached in the shared cache through the input interface, and the allocation of the shared cache is managed by the cache management module through the address pointer. In the process of subsequent processing, the data frame The body will always be stored in the shared cache, and only the cache address pointer is passed in the chip until the forwarding command reaches the output interface, and then the output interface reads the data fr...

Claims

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