Message analysis method and device based on FPGA hardware parallel pipelines

A message parsing and pipeline technology, applied in the field of network communication, can solve the problems of dynamic adjustment of inability to transmit messages, waste of resources and power, etc.

Active Publication Date: 2017-07-18
THE PLA INFORMATION ENG UNIV
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  • Description
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Problems solved by technology

In different environments and different time periods, the size of network traffic is also different, but the packet analysis of the device is still performed according to a specifi

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  • Message analysis method and device based on FPGA hardware parallel pipelines
  • Message analysis method and device based on FPGA hardware parallel pipelines
  • Message analysis method and device based on FPGA hardware parallel pipelines

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Embodiment Construction

[0034] In order to make the purpose, technical solution and advantages of the present invention more clear and understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and technical solutions. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0035] Examples, see figure 1 and 2 As shown, a message parsing method based on the FPGA hardware parallel pipeline, the FPGA hardware parallel pipeline includes a multi-stage FPGA programmable hardware pipeline, and each stage of the FPGA programmable hardware pipeline includes a storage unit and a logic processing unit, and the storage unit is used to store the A standardized protocol analysis tree node with protocol analysis capability, the logical processing unit is used to control the search of the data message sequence and complete the p...

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Abstract

The invention relates to a message analysis method and device based on FPGA hardware parallel pipelines. The method comprises the steps of measuring traffic parameters of real-time data streams under network interfaces; allocating data messages to parallel FIFO queues for processing; dynamically selecting analysis clock frequencies according to the traffic parameters; extracting front end quintuple information; and carrying out multilevel pipeline message analysis according to the selected analysis clock frequencies, if the protocol message analysis is normal, polling each pipeline in sequence for protocol message output, otherwise, carrying out abnormality analysis on the unidentified protocol messages, adjusting scheduling and then carrying out protocol message output. According to the method and the device, on the basis of a high-speed parallel pipeline structure, a message analysis rate is improved; working frequencies are dynamically changed through traffic detection; the system power consumption cost is greatly reduced; a solidified and sealed mode of a traditional network is broken through; a utilization rate of link resources is improved; and the basic network construction cost is reduced.

Description

technical field [0001] The invention belongs to the technical field of network communication, and in particular relates to a message parsing method and a device thereof based on an FPGA hardware parallel pipeline. Background technique [0002] The huge number of Internet users, the continuous emergence of new applications and the rapid growth of network bandwidth lead to a sharp increase in network services in the IP backbone network, and the number of packets that need to be forwarded by the backbone router per second also increases sharply. How to improve the IP forwarding processing capability of the router It directly affects the development of my country's Internet. As the basis for routers to perform IP forwarding processing, the flexible packet analysis technology can conveniently construct the connection of the underlying heterogeneous physical network topology, realize the fast transmission of data packets carried by different protocols in the Internet, and break the...

Claims

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Application Information

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IPC IPC(8): H04L29/06H04L12/26H04L12/863
CPCH04L43/0894H04L43/18H04L47/6245H04L69/22
Inventor 董永吉李玉峰于松林黄万伟王文功袁征张霞
Owner THE PLA INFORMATION ENG UNIV
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