24 results about "Programmable hardware" patented technology

The invention discloses a low-complexity cascade predistortion device and method for out-of-band spectrum suppression. The device comprises a predistorter unit, a model identification and trimming unit, a subtracter, a DAC unit, a power amplifier PA, a transmitting antenna, an ADC unit, a power normalization unit and a filter. The predistorter unit comprises a plurality of stages of predistortion modules; and the model identification and trimming unit is used for carrying out modeling, screening and parameter extraction on each stage of pre-distortion module, outputting a screened coefficient model coefficient and feeding back the coefficient model coefficient to the pre-distorter unit. The method is oriented to strong distortion conditions and specified frequency band out-of-band suppression, is low in training sample requirement, is low in implementation complexity, and is convenient to deploy a digital pre-distortion technical route on general programmable hardware, so that the supervision and standard indexes are met, the energy consumption and the engineering cost are reduced, and the adaptability to complex and changeable scenes is improved.

Techniques are described herein in which a programmable logic device (PLD) is integrated into a baseboard management controller (BMC). A programming-enhanced BMC is powered on by a PLD that is integrated into the programming-enhanced BMC and that is coupled to an internal bus of the programming-enhanced BMC. A configuration file is provided from immutable BMC hardware in the BMC to the PLD based at least on the programming-enhanced BMC being powered on. The configuration file specifies a configuration to be programmatically applied to programmable hardware of the PLD. The programmable hardware of the PLD is programmed by loading the configuration file, which causes the programmable hardware to render a peripheral interface that is defined by the configuration file natively on the internal bus of the programming-enhanced BMC.

The application discloses a bottom-layer security defense architecture and method based on thermodynamic entropy and nanosecond physical short circuit, which comprises a thermodynamic chaotic true random number generator configured to collect physical thermal noise and generate a true random number; a time-space jump memory management configured to dynamically remap the physical storage address of a volatile memory based on the true random number; a programmable hardware logic unit configured to run independently of a host processor and perform out-of-band polling on a physical intrusion detection signal; and a physical short circuit module connected between the power supply rail and the ground of the volatile memory, wherein the programmable hardware logic unit sends a trigger signal to the physical short circuit module when detecting the physical intrusion signal, and the physical short circuit module responds to the trigger signal to short the power supply rail of the volatile memory to the ground within a preset transient time threshold, so that the physical level data destruction less than 5 nanoseconds and the dynamic address confusion driven by the true random number are realized.

Systems or methods of the present disclosure may provide efficient circuit implementation on processing circuitry. The processing circuitry may include a processor, a programmable hardware, or both. The systems and methods may include determining and removing unused and / or redundant portions of predefined software and hardware description instructions before implementing associated circuitry. The implemented circuitry may perform various functions including parsing, pipelining, deparsing, temporary storage and combining, math operations, or a combination thereof, among other things.

The application discloses a data packet processing method and device, equipment, medium and product. The method is applied to a network device, the network device is configured with a programmable hardware forwarding chip, the method is executed by the programmable hardware forwarding chip, and the method comprises the following steps: obtaining a first data packet received by the network device, wherein the first data packet comprises a header extension option field, the header extension option field is a variable-length and non-fixed-structure option field; based on a hardware alignment constraint of the programmable hardware forwarding chip, the header extension option field is parsed to obtain a parsing result, and the parsing result comprises a target option field in the header extension option field; when it is determined that the target option field meets a modification condition, the target option field is modified, the first data packet is updated based on the modified target option field, and a second data packet is obtained. The application can improve the processing efficiency of the data packet.

This invention discloses a programmable data plane high-intensity traffic response method and system based on feature distribution, belonging to the field of network traffic classification technology. The programmable data plane high-intensity traffic response method based on feature distribution includes: extracting features from each flow in the data plane and determining whether the features are matched by the current rule; if matched, processing according to the corresponding rule; if not matched, processing as an outlier and recording it; periodically sampling processed flows, triggering rule updates when outliers reach a preset threshold; the control plane uses a density-based clustering algorithm to cluster sampled points to obtain the current traffic feature distribution shape, extracting the boundaries of each cluster to form a high-dimensional rectangle as a new rule, and formulating corresponding processing measures based on spatial features and meta-features, and issuing them to the data plane. This invention achieves line-rate processing and dynamic adaptation on resource-constrained programmable hardware, effectively addressing feature drift under high-intensity traffic while ensuring interpretability.

An information processing method, a computer device, and a storage medium are provided. The method includes: acquiring communication information to be processed; extracting a key information character of the communication information to be processed by using a programmable hardware unit of a data processor; and according to the key information character, determining whether there is matching target processing operation information in a generated character mapping table, a character mapping table is generated by the programmable software unit of the data processor according to historical key information characters of historical communication information and their corresponding historical processing operation information, and the target processing operation information includes at least one micro-service processing operation; if yes, executing the micro-service processing operation included in the target processing operation information for the communication information to be processed.

Embodiments of the present disclosure provide a message processing method, a programmable network card device, a physical server, and a storage medium. In the embodiments of the present disclosure, a virtual switch in software form is deployed on the programmable network card device, and a message parsing acceleration module and a hardware message queue providing message parsing service for the virtual switch are implemented on the programmable network card device based on programmable hardware. The embodiments of the present disclosure can greatly reduce the message parsing cost of the virtual switch and achieve high message forwarding performance. At the same time, all operations except parsing of the header information of the message are performed by the virtual switch in software form, which can meet flexible application requirements and ensure rapid iteration and evolution of the application requirements.

The invention provides a programmable hardware system for integrating SDN (Software Defined Network) service in the radio and television industry. The system comprises a hardware panel body, an industrial mainboard module, a panel key module, an embedded SDN service module and a power management module. And the industrial mainboard module is used for running an embedded SDN service program, automatically detecting ST2110 compatible equipment through a network interface and dynamically constructing a logic topological graph. And after the system collects a signal switching operation instruction of the physical key, the signal switching operation instruction is directly issued to target network equipment through a locally generated flow table rule, so that routing control of a video signal is realized. And the embedded SDN service module adopts a layered software architecture, and realizes independent management and control separated from a server by using a built-in lightweight database. According to the invention, software and hardware integration of the SDN service and the hardware panel is realized, the problems of complex deployment, high network dependency and poor portability in the prior art are solved, and the system has the advantages of low delay, high reliability, simple deployment and strong shock resistance.

The application discloses a semantic-level ICS zero-trust platform based on in-network computing, aiming at solving the two difficult problems of difficult deployment and guaranteeing deterministic transmission of the semantic-level ICS zero-trust mechanism. Through in-network computing technology and programmable hardware devices, semantic-level secure transmission and deterministic transmission are realized. The application mainly includes a modular processing flow and an optimized pipeline architecture, can be deployed on programmable hardware devices such as FPGAs, ensures efficient forwarding of data packets and semantic-level permission verification, effectively balances the three requirements of semantic-level protection, easy deployment and deterministic transmission, provides protection for industrial control system network security, and has a wide application prospect.

The invention relates to the technical field of intelligent management and control, and discloses an intelligent management and control system based on equipment identifier dynamic detection, and the system comprises a sensing module which is used for continuously collecting multi-dimensional physical fingerprint data of unmanned equipment, and dynamically reconstructing a physical fingerprint collection logic according to a risk level; the modeling module is used for modeling the physical fingerprint data into a dynamic entropy matrix and a dynamic physical fingerprint spectrum; and the analysis module is used for carrying out real-time analysis on the dynamic entropy matrix and the dynamic physical fingerprint spectrum based on a pre-trained baseline model. Through deep perception and active enhancement mechanisms of multi-modal physical fingerprints, a programmable hardware security unit periodically injects micro-perturbation to generate a dynamic response spectrum, and physical fingerprint acquisition logic is dynamically adjusted or reconstructed at a high risk, so that the problem that a traditional single static identifier is easily counterfeited or bypassed is effectively solved; and the identification precision and the anti-attack capability of the system on physical tampering and illegal replacement are greatly improved.

The invention relates to the technical field of industrial communication networks, in particular to a wireless communication chip prototype verification method and device, and the method comprises the steps: receiving an original data stream of industrial field wireless communication equipment, and carrying out the preprocessing and format conversion to generate a digital signal; loading a WIA-FA protocol stack model by utilizing a programmable hardware platform to carry out hardware-level protocol simulation; a dual-radio-frequency chip architecture is adopted to fix transmitting and receiving modes, and noise introduced by existing transmitting and receiving switching is avoided; time sequence deviation and signal distortion are identified by monitoring time delay, throughput and reliability indexes in real time; dynamically adjusting protocol parameters or radio frequency configuration based on the deviation analysis result; in-phase / orthogonal unbalanced self-calibration is realized by combining a coupling loop structure; and finally generating a comprehensive verification report to compare a hardware simulation result with an expected performance index. According to the WIA-FA protocol verification method, the deviation between a simulation environment and real hardware deployment is effectively reduced, and the accuracy and efficiency of WIA-FA protocol verification are improved.

This application discloses a method, apparatus, device, medium, and product for processing data packets. The method is applied to a network device equipped with a programmable hardware forwarding chip. The method is executed by the programmable hardware forwarding chip and includes: acquiring a first data packet received by the network device, the first data packet including a header extension option field, the header extension option field being a variable-length and non-fixed-structure option field; parsing the header extension option field based on the hardware alignment constraints of the programmable hardware forwarding chip to obtain a parsing result, the parsing result including a target option field in the header extension option field; modifying the target option field when it is determined that the target option field meets the modification conditions; and updating the first data packet based on the modified target option field to obtain a second data packet. This application can improve the processing efficiency of data packets.

This invention discloses a method for accelerating UPF functionality based on programmable hardware, belonging to the field of 5G mobile communication networks. It offloads the traditional CPU-based UPF functionality to the Data Processing Unit (DPU), fully leveraging the architectural advantages of DPU's hardware-software co-processing to significantly reduce packet processing latency and improve system throughput. By parsing and reconstructing dependent matching rules, it generates independent, dependency-free rules, reducing redundancy and conflicts in the hardware rule table. Simultaneously, a traffic classification mechanism is used to divide network traffic into large and small flows, mapping them to hardware and software paths respectively, maximizing the performance advantages of hardware-software co-processing. This invention can significantly optimize packet processing capabilities under high-load scenarios, effectively reduce latency bottlenecks, and improve overall system throughput and resource utilization.

The present disclosure relates to a vector processor implemented on programmable hardware (e.g., a field programmable gate array (FPGA) device). The vector processor includes a plurality of vector processor channels, wherein each vector processor channel includes a vector register file having a plurality of register file libraries and a plurality of execution units. Implementations described herein include features for optimizing resource availability on programmable hardware units and enabling superscalar execution when coupled with Time Single Instruction Multiple Data (SIMD).

The invention provides a board card configuration method and system with a multi-service transmission function, and relates to the technical field of multi-service transmission board cards, and the method comprises the steps: dividing an FPGA into dynamic reconfigurable logic units based on a heterogeneous architecture of the FPGA and a multi-core processor in a board card, and forming a programmable hardware resource pool; based on a virtual port of the programmable hardware resource pool, calling a field mapping table through a protocol converter to convert Ethernet, OTN and FC protocols, and outputting messages adaptive to different manufacturer devices; collecting board card operation state data of the programmable hardware resource pool, constructing a corresponding digital twin mirror image in the board card management platform, and outputting mirrored board card operation state data; and fault analysis is carried out on the mirrored board card operation state data, potential operation faults are predicted, and a maintenance work order is generated, so that the resource utilization rate of the board card in a mixed service transmission scene is improved, the protocol adaptation flexibility is improved, the operation and maintenance response speed is accelerated, and the potential faults are predicted and processed in advance.

System and methods are provided for updating firmware used by a managed hardware component of an Information Handling System (IHS). A remote access controller of the IHS, that operates separate from CPUs of the IHS and that provides remote management of the IHS, initiates an update of firmware used to operate the hardware component. A programmable hardware accelerator is detected within an inventory of managed hardware components of the IHS. Availability of the hardware accelerator is determined for transmission of data to the hardware component. Transmission of a firmware image to the hardware component is delegated to the hardware accelerator, providing faster transmission of the firmware image than would be possible by the remote access controller. Upon transmission of the firmware image by the hardware accelerator, the firmware of the hardware component is updated using the firmware image transmitted by the hardware accelerator.

This invention discloses a programmable delay-triggered system for large-scale high-speed data acquisition, solving the underlying technical problems of severe waste of cache resources and insufficient synchronization accuracy in cross-board distribution caused by traditional global rigid triggering mechanisms. The system consists of a host computer parameter scheduling module, a programmable hardware trigger control chassis, and a large-scale data acquisition array. The host computer issues ASCII scientific notation configuration frames containing independent delay and pulse width parameters for each channel; the FPGA asynchronously preloads parameters during non-acquisition periods and outputs the set trigger pulses in parallel under the drive of an external global reference edge. The system integrates a cross-level collaborative alignment mechanism of "FPGA internal logic IOB constraints," "PCB-level equal-length trace matching," and "channel-end RC precision calibration circuit," controlling the trigger delay difference of multiple channels within ±500ps.

Techniques for integrating a programmable logic device (PLD) into a baseboard management controller (BMC) are described herein. The program-enhanced BMC is energized by a PLD that is integrated into the program-enhanced BMC and coupled to an internal bus of the program-enhanced BMC. The configuration file is provided to the PLD from immutable BMC hardware in the BMC based at least on the programming-enhanced BMC being energized. The configuration file specifies a configuration of programmable hardware to be programmatically applied to the PLD. Programmable hardware of the PLD is programmed by loading the configuration file, so that the programmable hardware originally presents a peripheral interface defined by the configuration file on an internal bus of the programming-enhanced BMC.

The invention discloses a defect detection method, system and device and semiconductor measurement equipment, and relates to the technical field of semiconductor manufacturing, and the method comprises the steps: obtaining image data of a semiconductor sample to be detected, and carrying out the preprocessing operation of data combination and the like determined according to the input requirement of a defect detection algorithm on the image data through a first programmable hardware processor, and generating target processing data, then sending the target processing data to the cluster server, executing defect detection calculation on the target processing data by using the cluster server, and outputting a defect detection result of the semiconductor sample to be detected. The first programmable hardware processor is used for executing preprocessing operation on the image data, data combination and preprocessing are completed before the cluster server executes defect detection of the image data, participation of a processor of the cluster server is not needed, the calculation burden of the server in the preprocessing stage of the image data can be greatly reduced, and the processing efficiency is improved. Therefore, the technical effect of reducing the number of cluster servers is achieved.

Systems and methods are described for training and deploying a logic gate neural network. In various examples, a computing system receives a training data set of input vectors with target outputs and instantiates an untrained network whose nodes are parameterized over a predefined set of potential logic operators. Training may include forward propagating a batch of input vectors, computing node outputs as differentiable functions of the potential operators, aggregating outputs by summation to form scores, evaluating a loss, and updating the differentiable parameters. A fixed network is defined after multiple iterations by selecting a single logic operator for each respective node. Examples of suitable logic operators include AND, OR, NAND, NOR, XOR, constants, inverters, direct connections, and the like. The fixed network can be implemented as an application-specific integrated circuit (ASIC) or stored in a non-transitory memory and implemented in programmable hardware, such as a field-programmable gate array (FPGA).

The invention discloses a protocol simulation verification device oriented to an SRv6 scene. The core of the device is a protocol processing task scheduler which collects state information of virtual and real sides through a virtual and real network synchronization module; a mapping rule between an SRv6 protocol verification task in a virtual network and entity programmable hardware resources is dynamically generated through a task analysis-rule generation module, and the mapping rule is converted into a flow table rule which can be recognized by entity programmable hardware and is used for processing an SRv6 data packet; according to the method, tunnel packaging and analysis are carried out on SRv6 data traffic of a virtual network through a traffic interaction module, so that the SRv6 data traffic of the virtual network and a verification task context associated with the SRv6 data traffic are accurately identified and linearly processed in entity programmable hardware, and an SRv6 protocol verification result from the entity programmable hardware is received. The core contradiction between poor simulation environment performance fidelity and insufficient entity test environment flexibility is overcome, and rapid and high-fidelity verification of the SRv6 scene protocol is realized.

A software agent generates packet sessions and hands off the task of generating and routing the packets to a programmable hardware logic block, such as a packet processor. The software agent provides entries in one or more tables that are subsequently used by the packet processor to generate and route the packets. During a first stage, the packets are generated at an ingress pipeline. The packets are then transferred to an egress pipeline from which pipeline the packets are reinjected back into the ingress pipeline. During the second stage and at the ingress pipeline, routing information, representative of a network layer or a tunnel, to which the packets are to be routed, are added to the packets. The packets are then forwarded to the egress pipeline and subsequently routed to a next hop or tunnel leading to the packets' respective destination addresses.

Provided is a system and a method for determining a set of parameters to be used for cell categorization at a cell analysis device, and a non-transitory, computer-readable medium comprising a program code that, when the program code is executed on a processor, a computer, or a programmable hardware component, causes the processor, computer, or programmable hardware component to perform the method. The system comprises storage circuitry and processor circuitry. The system is configured to obtain an image showing a plurality of cells, perform an image analysis algorithm on the image using an initial set of parameters to determine a categorization of objects shown in the image, generate indicia of the respective categorization of the objects overlaid over the image, provide a user interface for changing at least one of a parameter of the set of parameters and a categorization of an object, with the user interface comprising the image and the indicia, obtain an input from a user, the input including at least one of a change to at least one parameter of the set of parameters or a change to the categorization of at least one object, and repeat performing at least a portion of the image analysis algorithm and generating the indicia based on the input obtained from the user to update the initial set of parameters based on the input from the user.