65 results about "Programmable hardware" patented technology

The invention discloses a solid state disk management system and a data processing method, and relates to the technical field of solid state disk management. Flexible task scheduling and resource management are provided through a lightweight operating system module, and a computing task program defined by a user is supported to be dynamically loaded; edge computing or machine learning operators are efficiently executed in combination with a programmable hardware processing unit and a DMA channel of the computing acceleration engine module, the data preloading module is utilized to predict and preload data to DDR based on LBA access history, access delay is reduced, an NVMe protocol is expanded by means of the task unloading interface module, host task issuing and result returning are achieved, and the data processing efficiency is improved. And hardware-level memory protection is ensured through the security isolation module, so that the data calculation processing capacity of the solid state disk is remarkably improved, localized calculation tasks such as edge calculation and machine learning are supported, mass data transmission is effectively reduced, and bus and network loads are relieved.

Described herein are systems and methods for programmable, hardware-accelerated congestion monitoring and / or control. At least one circuit can configure a plurality of hardware circuits with one or more rules that, when satisfied, cause the plurality of hardware circuits to generate one or more congestion events indicative of congestion in a network. The at least one circuit can receive the one or more congestion events generated by the plurality of hardware circuits based on one or more network signals in the network satisfying the one or more rules. In response to receipt of the one or more congestion events from the plurality of hardware circuits configured with the one or more rules to detect the congestion in the network, the at least one circuit can analyze the one or more congestion events to address the congestion in the network. Various other methods, systems, and computer-readable media are also disclosed.

The invention discloses a PCIe interface verification method and a PCIe interface verification system, and relates to the technical field of test.According to the PCIe interface verification method, after a PCIe interface is divided into a PCIe controller and a PCIe physical layer, a simulation PCIe controller can be constructed based on programmable hardware resources in a programmable logic device, and the simulation PCIe controller can be constructed in non-programmable hardware resources of the programmable logic device; at least a portion of the physical layer is selected as a simulated PCIe physical layer. After the simulation PCIe controller and the simulation PCIe physical layer are connected, the simulation PCIe controller and the simulation PCIe physical layer can communicate with each other, namely, the combination of the simulation PCIe controller and the simulation PCIe physical layer can be regarded as a simulation PCIe interface. Therefore, prototype verification of the PCIe interface can be realized based on the simulation PCIe interface, so that the problem that prototype verification cannot be performed on the PCIe interface in some technologies is solved.

Techniques are described herein in which a programmable logic device (PLD) is integrated into a baseboard management controller (BMC). A programming-enhanced BMC is powered on by a PLD that is integrated into the programming-enhanced BMC and that is coupled to an internal bus of the programming-enhanced BMC. A configuration file is provided from immutable BMC hardware in the BMC to the PLD based at least on the programming-enhanced BMC being powered on. The configuration file specifies a configuration to be programmatically applied to programmable hardware of the PLD. The programmable hardware of the PLD is programmed by loading the configuration file, which causes the programmable hardware to render a peripheral interface that is defined by the configuration file natively on the internal bus of the programming-enhanced BMC.

The invention discloses a self-adaptive optical distortion compensation device and compensation method based on high-speed closed-loop control, and the device comprises an optical path front-end interface which is used for connecting a coupling wind tunnel or a laser emission system; the wavefront sensor is used for measuring a local wavefront slope by adopting a distributed array; the FPGA controller comprises a wavefront reconstruction processor and a closed-loop logic controller and is used for reconstructing wavefront and generating a control instruction; the MEMS deformable mirror array comprises a plurality of MEMS drivers and is used for correcting a wavefront phase; the feedback monitoring module is used for performing dual verification through deformation capacitance measurement and CCD image feedback; and the imaging / laser output end is used for converting the corrected optical signal into an image and outputting the image. The method can be widely applied to the fields of high-speed aircraft wind tunnel testing, laser communication, infrared imaging guide head calibration, high-energy laser beam shaping and the like, a programmable hardware platform, a high-speed parallel operation structure and a predictive control algorithm are introduced, and unprecedented sub-microsecond closed-loop compensation is achieved.

The invention discloses a low-complexity cascade predistortion device and method for out-of-band spectrum suppression. The device comprises a predistorter unit, a model identification and trimming unit, a subtracter, a DAC unit, a power amplifier PA, a transmitting antenna, an ADC unit, a power normalization unit and a filter. The predistorter unit comprises a plurality of stages of predistortion modules; and the model identification and trimming unit is used for carrying out modeling, screening and parameter extraction on each stage of pre-distortion module, outputting a screened coefficient model coefficient and feeding back the coefficient model coefficient to the pre-distorter unit. The method is oriented to strong distortion conditions and specified frequency band out-of-band suppression, is low in training sample requirement, is low in implementation complexity, and is convenient to deploy a digital pre-distortion technical route on general programmable hardware, so that the supervision and standard indexes are met, the energy consumption and the engineering cost are reduced, and the adaptability to complex and changeable scenes is improved.

An electronic device (110) is presented. The electronic device (110) comprises: • a plurality of non-programmable hardware elements (118), each non-programmable hardware element (118) configured to provide at least one non-programmable function; • at least one programmable hardware element (120) configured to provide at least one programmable function, wherein the programmable hardware element (120) comprises at least one standby entity (122), wherein the standby entity (122) is configured to provide at least one programmable function to replace the non-programmable functions of at least two non-programmable hardware elements (118); and • at least one arbiter (124) configured to deactivate at least one non-programmable hardware element (118) and to activate the standby entity (122) to replace at least one non-programmable function provided by the non-programmable hardware element (118) with at least one programmable function. Furthermore, an embedded system (112), a method for operating the electronic device (110) and a use of the electronic device (110) and the method for operating the electronic device (110) are presented.

Techniques are described herein in which a programmable logic device (PLD) is integrated into a baseboard management controller (BMC). A programming-enhanced BMC is powered on by a PLD that is integrated into the programming-enhanced BMC and that is coupled to an internal bus of the programming-enhanced BMC. A configuration file is provided from immutable BMC hardware in the BMC to the PLD based at least on the programming-enhanced BMC being powered on. The configuration file specifies a configuration to be programmatically applied to programmable hardware of the PLD. The programmable hardware of the PLD is programmed by loading the configuration file, which causes the programmable hardware to render a peripheral interface that is defined by the configuration file natively on the internal bus of the programming-enhanced BMC.

The application discloses a bottom-layer security defense architecture and method based on thermodynamic entropy and nanosecond physical short circuit, which comprises a thermodynamic chaotic true random number generator configured to collect physical thermal noise and generate a true random number; a time-space jump memory management configured to dynamically remap the physical storage address of a volatile memory based on the true random number; a programmable hardware logic unit configured to run independently of a host processor and perform out-of-band polling on a physical intrusion detection signal; and a physical short circuit module connected between the power supply rail and the ground of the volatile memory, wherein the programmable hardware logic unit sends a trigger signal to the physical short circuit module when detecting the physical intrusion signal, and the physical short circuit module responds to the trigger signal to short the power supply rail of the volatile memory to the ground within a preset transient time threshold, so that the physical level data destruction less than 5 nanoseconds and the dynamic address confusion driven by the true random number are realized.

Techniques are disclosed herein for reconfiguring reprogrammable hardware in an autonomous vehicle system. According to an embodiment, an autonomous driving system includes sensors and a configurable circuit having physical logic units. The autonomous driving system aggregates data observed from each of the sensors. The autonomous driving system detects a trigger indicative of a defect in the configurable circuit. The defect is identified as a function of the aggregated data. The autonomous driving system performs, in response to the trigger, a reconfiguration action on the configurable circuit to repair the defect.

A programmable hardware system for machine learning (ML) includes a core and a streaming engine. The core receives a plurality of commands and a plurality of data from a host to be analyzed and inferred via machine learning. The core transmits a first subset of commands of the plurality of commands that is performance-critical operations and associated data thereof of the plurality of data for efficient processing thereof. The first subset of commands and the associated data are passed through via a function call. The streaming engine is coupled to the core and receives the first subset of commands and the associated data from the core. The streaming engine streams a second subset of commands of the first subset of commands and its associated data to an inference engine by executing a single instruction.

A quantum error correction hardware decoder and chip, relating to the fields of artificial intelligence and quantum technology, includes: an instruction storage device configured to store computer instructions; a control unit configured to read the computer instructions from the instruction storage device and control at least one neural network processing unit based on the computer instructions; the at least one neural network processing unit configured, in response to control by the control unit, to decode error syndrome information of a quantum circuit based on a neural network model to obtain an output result of the neural network model, where the error syndrome information indicates an error syndrome obtained by performing error measurements on the quantum circuit; and an error batch search unit configured to determine error information based on the output result, where the error information indicates a quantum bit in the quantum circuit where an error has occurred and an error type corresponding to the error. The programmable hardware architecture provided in this application can ensure decoding performance while sufficiently reducing decoding delay and improving scalability and flexibility.

An electronic device comprises a plurality of non-programmable hardware elements, each non-programmable hardware element being configured for providing at least one non-programmable function; at least one programmable hardware element configured for providing at least one programmable function, wherein the programmable hardware element comprises at least one standby entity, wherein the standby entity is configured for providing at least one programmable function for replacing the non-programmable functions of at least two non-programmable hardware elements; and at least one arbiter configured for deactivating at least one non-programmable hardware element and for activating the standby entity for replacing at least one non-programmable function provided by the non-programmable hardware element with at least one programmable function.

The embodiment of the present application provides a kind of computing system, data processing method, offload card and storage medium.In the embodiment of the present application, the programmable hardware unit in programmable offload card, can be obtained to the access request of storage protocol conversion, obtain the access request of the storage protocol that follows the network storage system support, then, the network card in programmable offload card can be sent to the network storage system by the access request of the storage protocol that follows the network storage system support, access to network storage system is realized.The whole network storage system access process will be converted to programmable hardware unit in the process of storage protocol, so that protocol conversion process is executed by hardware, without the CPU of programmable offload card is involved, shorten IO link path, can reduce the number of data replication, realize the hardware acceleration of network storage system access.

Systems or methods of the present disclosure may provide efficient circuit implementation on processing circuitry. The processing circuitry may include a processor, a programmable hardware, or both. The systems and methods may include determining and removing unused and / or redundant portions of predefined software and hardware description instructions before implementing associated circuitry. The implemented circuitry may perform various functions including parsing, pipelining, deparsing, temporary storage and combining, math operations, or a combination thereof, among other things.

The application discloses a data packet processing method and device, equipment, medium and product. The method is applied to a network device, the network device is configured with a programmable hardware forwarding chip, the method is executed by the programmable hardware forwarding chip, and the method comprises the following steps: obtaining a first data packet received by the network device, wherein the first data packet comprises a header extension option field, the header extension option field is a variable-length and non-fixed-structure option field; based on a hardware alignment constraint of the programmable hardware forwarding chip, the header extension option field is parsed to obtain a parsing result, and the parsing result comprises a target option field in the header extension option field; when it is determined that the target option field meets a modification condition, the target option field is modified, the first data packet is updated based on the modified target option field, and a second data packet is obtained. The application can improve the processing efficiency of the data packet.

This invention discloses a programmable data plane high-intensity traffic response method and system based on feature distribution, belonging to the field of network traffic classification technology. The programmable data plane high-intensity traffic response method based on feature distribution includes: extracting features from each flow in the data plane and determining whether the features are matched by the current rule; if matched, processing according to the corresponding rule; if not matched, processing as an outlier and recording it; periodically sampling processed flows, triggering rule updates when outliers reach a preset threshold; the control plane uses a density-based clustering algorithm to cluster sampled points to obtain the current traffic feature distribution shape, extracting the boundaries of each cluster to form a high-dimensional rectangle as a new rule, and formulating corresponding processing measures based on spatial features and meta-features, and issuing them to the data plane. This invention achieves line-rate processing and dynamic adaptation on resource-constrained programmable hardware, effectively addressing feature drift under high-intensity traffic while ensuring interpretability.

Technologies are provided for a programmable hardware proxy (PHP) for assessment of control logic. A control sequence that controls execution of an automation task within a physical automation system can be accessed to generate a virtual representation of physical control connections among sensor devices and a control device associated with an automation subsystem. The virtual representation constitutes a realistic virtual control interface that can be exposed to the automation subsystem in virtual domain. The virtual control interface can replace the control device in virtual domain, while preserving the functionality of the control device. The virtual control interface constitutes the PHP for the sensors devices and the control device. The PHP can be used to assess control logic for the automation subsystem, without reliance on hardware present in the automation subsystems.

An information processing method, a computer device, and a storage medium are provided. The method includes: acquiring communication information to be processed; extracting a key information character of the communication information to be processed by using a programmable hardware unit of a data processor; and according to the key information character, determining whether there is matching target processing operation information in a generated character mapping table, a character mapping table is generated by the programmable software unit of the data processor according to historical key information characters of historical communication information and their corresponding historical processing operation information, and the target processing operation information includes at least one micro-service processing operation; if yes, executing the micro-service processing operation included in the target processing operation information for the communication information to be processed.

Embodiments of the present disclosure provide a message processing method, a programmable network card device, a physical server, and a storage medium. In the embodiments of the present disclosure, a virtual switch in software form is deployed on the programmable network card device, and a message parsing acceleration module and a hardware message queue providing message parsing service for the virtual switch are implemented on the programmable network card device based on programmable hardware. The embodiments of the present disclosure can greatly reduce the message parsing cost of the virtual switch and achieve high message forwarding performance. At the same time, all operations except parsing of the header information of the message are performed by the virtual switch in software form, which can meet flexible application requirements and ensure rapid iteration and evolution of the application requirements.

The present invention provides an FPGA acceleration method based on a programmable hardware floating-point library, which relates to the technical field of FPGA acceleration methods. The method includes adopting a dspfloat data type; the dspfloat data type includes a 1-bit wide sign bit, an exponent bit, and a mantissa bit; a sign bit value of 0 indicates a positive number, and a sign bit value of 1 indicates a negative number; the exponent bit is the NEXP bit; the mantissa bit is the NFRAC bit; the exponent bits are stored in a two's complement format; the mantissa bit represents the valid floating-point data, hiding the high-order bit 1; and the bit widths of the exponent and mantissa bits can be customized. The exponent and mantissa bit widths of the dspfloat provided by the present invention can be customized, avoiding the defects of insufficient precision of the float data type and excessive bit width of the double data type. While ensuring the precision required by the application, the method achieves a higher frequency, reduces computing resource usage, and improves computing speed.

Techniques are disclosed herein for reconfiguring reprogrammable hardware in an autonomous vehicle system. According to an embodiment, an autonomous driving system includes sensors and a configurable circuit having physical logic units. The autonomous driving system aggregates data observed from each of the sensors. The autonomous driving system detects a trigger indicative of a defect in the configurable circuit. The defect is identified as a function of the aggregated data. The autonomous driving system performs, in response to the trigger, a reconfiguration action on the configurable circuit to repair the defect.

The invention provides a programmable hardware system for integrating SDN (Software Defined Network) service in the radio and television industry. The system comprises a hardware panel body, an industrial mainboard module, a panel key module, an embedded SDN service module and a power management module. And the industrial mainboard module is used for running an embedded SDN service program, automatically detecting ST2110 compatible equipment through a network interface and dynamically constructing a logic topological graph. And after the system collects a signal switching operation instruction of the physical key, the signal switching operation instruction is directly issued to target network equipment through a locally generated flow table rule, so that routing control of a video signal is realized. And the embedded SDN service module adopts a layered software architecture, and realizes independent management and control separated from a server by using a built-in lightweight database. According to the invention, software and hardware integration of the SDN service and the hardware panel is realized, the problems of complex deployment, high network dependency and poor portability in the prior art are solved, and the system has the advantages of low delay, high reliability, simple deployment and strong shock resistance.

The invention relates to an atomic communication receiving system and method based on software radio. The system comprises a photoelectric detection module; the signal amplification module is connected with the photoelectric detection module; an analog-to-digital conversion module; the digital down-conversion module is connected with the analog-to-digital conversion module and is used for down-converting the high-frequency digital signal into a baseband signal through digital frequency mixing and decimation filtering; the band-pass filtering module is connected with the digital down-conversion module and is used for carrying out band-pass filtering on the baseband signal so as to extract effective signal components; the signal demodulation module is connected with the band-pass filtering module and is used for demodulating the filtered signal to recover original data; the digital down-conversion module, the band-pass filtering module and the signal demodulation module are based on the software radio technology, and functions are achieved through software programs on a programmable hardware platform. According to the invention, synchronous and independent measurement of multi-path signal power can be realized in a multi-satellite parallel test scene so as to support satellite batch test requirements.

The application discloses a semantic-level ICS zero-trust platform based on in-network computing, aiming at solving the two difficult problems of difficult deployment and guaranteeing deterministic transmission of the semantic-level ICS zero-trust mechanism. Through in-network computing technology and programmable hardware devices, semantic-level secure transmission and deterministic transmission are realized. The application mainly includes a modular processing flow and an optimized pipeline architecture, can be deployed on programmable hardware devices such as FPGAs, ensures efficient forwarding of data packets and semantic-level permission verification, effectively balances the three requirements of semantic-level protection, easy deployment and deterministic transmission, provides protection for industrial control system network security, and has a wide application prospect.

The invention relates to the technical field of intelligent management and control, and discloses an intelligent management and control system based on equipment identifier dynamic detection, and the system comprises a sensing module which is used for continuously collecting multi-dimensional physical fingerprint data of unmanned equipment, and dynamically reconstructing a physical fingerprint collection logic according to a risk level; the modeling module is used for modeling the physical fingerprint data into a dynamic entropy matrix and a dynamic physical fingerprint spectrum; and the analysis module is used for carrying out real-time analysis on the dynamic entropy matrix and the dynamic physical fingerprint spectrum based on a pre-trained baseline model. Through deep perception and active enhancement mechanisms of multi-modal physical fingerprints, a programmable hardware security unit periodically injects micro-perturbation to generate a dynamic response spectrum, and physical fingerprint acquisition logic is dynamically adjusted or reconstructed at a high risk, so that the problem that a traditional single static identifier is easily counterfeited or bypassed is effectively solved; and the identification precision and the anti-attack capability of the system on physical tampering and illegal replacement are greatly improved.

The invention discloses a high-efficiency brain-like intelligent algorithm heterogeneous edge reasoning platform, and relates to the technical field of Internet of Things. The platform comprises an edge computer, a coprocessor and a routing forwarding switch; the edge computer and the coprocessor are respectively connected with the route forwarding switch through the Ethernet; the routing forwarding switch is connected with external equipment through the Ethernet; the edge computer comprises an edge CPU, an edge DRAM and a GPU; the edge CPU is connected with the route forwarding switch, the edge DRAM and the GPU; the coprocessor comprises a reasoning CPU, a reasoning DRAM and an FPGA; the reasoning CPU is connected with the route forwarding switch, the reasoning DRAM and the FPGA, and the reasoning DRAM is connected with the FPGA. By integrating the high-performance embedded computing unit and the programmable hardware accelerator, the intelligent reasoning system with the characteristics of low delay and high energy efficiency is constructed, efficient edge computing is realized by integrating an advanced hardware architecture and an innovative algorithm, and efficient support for a complex deep learning task is realized.

The invention discloses a UPF function acceleration method based on programmable hardware, belongs to the field of 5G mobile communication networks, unloads a UPF function which is realized by relying on a CPU in a server traditionally to a data processing unit DPU, makes full use of the architecture advantage of software and hardware cooperative processing of the DPU, and realizes significant reduction of data packet processing time delay and improvement of system throughput performance. The matching rules with the dependency relationship are analyzed and reconstructed to generate independent rules which can be issued independently, so that redundancy and conflicts of a hardware rule table are reduced. Meanwhile, a traffic classification mechanism is used, network traffic is divided into large and small streams which are respectively mapped to hardware and software paths for processing, and the performance advantage of software and hardware co-processing is exerted to the maximum extent. According to the method, the data packet processing capability can be obviously optimized in a high-load scene, the delay bottleneck is effectively reduced, and the overall throughput rate and the resource utilization rate of the system are improved.

The invention belongs to the technical field of chip configuration, and provides an FPGA chip configuration method and device, a program product, a medium and electronic equipment. The method comprises the steps that the operation index of each converter module in a deep learning model is acquired, and the operation index is used for representing the operand of the converter module; obtaining the total amount of programmable hardware resources in an FPGA chip, wherein the FPGA chip is used for executing an operation task on the deep learning model; a plurality of processing units are configured in the FPGA chip according to the operation indexes of the converter modules and the total hardware resource amount, and the processing units are matched with the operation amount of the converter modules. Through the technical scheme provided by the invention, hardware resources capable of dynamically adapting to the operation requirements of the deep learning model can be efficiently provided for the deep learning model.

The present application discloses a video processing method, apparatus, and computer-readable storage medium. According to some embodiments, the video processing apparatus includes a programmable hardware encoder configured to perform encoding processing on a plurality of input video frames. The video processing apparatus further includes a controller coupled to the programmable hardware encoder. The controller is configured to execute an instruction set to cause the video processing device to: determine first information of the plurality of input video frames and adjust the encoding processing based on the first information.