35 results about "Protocol verification" patented technology

The invention relates to a modeling and formalized verification method for cache consistency protocol verification, and the method comprises the steps: building a protocol model which comprises a plurality of processor nodes, directory nodes and a communication mechanism through a structured modeling mode, and constructing an asynchronous message mechanism to simulate disordered concurrent communication; protocol behavior rules such as processor requests, directory responses and network receiving are defined, protocol property invariants are set, semantic constraints such as data consistency, confirmation before writing and sharing state legality are covered, model verification is carried out in a state space traversal mode, breadth-first search and a symmetry recognition mechanism are supported, and the method is suitable for the protocol behavior rules. A protocol error or deadlock state is effectively found, a traceable error path is generated, a verifier can automatically generate source codes through a compiler and operate on a host platform, and rapid verification and result output of a protocol model are achieved. The method has good protocol adaptability and model reusability, and is suitable for formalized verification of various cache consistency protocols.

The invention discloses a verification system of an FSMC multi-memory interface based on a UVM, and belongs to the technical field of chip verification. The verification system of the FSMC multi-memory interface based on the UVM comprises a test layer, a simulation instruction definition layer, an AHB bus interface component, an assertion inspection component and an external memory interface component. The problems that in the prior art, a single memory is mainly connected for verification, only a single protocol can be verified, the verification means is limited, and the efficiency and the coverage rate are not high are solved, the transmission type of the AHB is defined in the environment configuration component, therefore, the verification diversity is improved, the verification requirements for verifying different memory interfaces are well met, and the verification efficiency is improved. According to the interface protocol verification method and device, the randomized excitation and self-checking function conforming to the protocol can be generated, the verification comprehensiveness is greatly improved, the pertinence and correctness of the verified module are greatly improved, the verification efficiency is improved, the code cost is reduced, and the accuracy of interface protocol verification is improved.

The invention relates to the technical field of integrated circuits and provides a physical IP verification device and method, computer equipment and a medium. The physical IP verification device comprises a first reusable multimode test sequence generator, a verification component physical interface, a second reusable multimode test sequence generator and a verification component serial interface. Therefore, different simulation requirements and scenes such as accelerated simulation efficiency and integrated verification can be considered, protocol consistency verification, functional verification completeness of a physical layer subsystem level and standardized protocol verification are supported, and abundant test vector sets are provided; according to the method, the requirements of butt joint test scenes and completeness verification of different levels such as a transaction layer, a data link layer and a physical layer can be met, debugging interaction interfaces and debugging means with rich levels are supported, different physical interface versions and interface data bus bit widths are supported, and hierarchical and fine-granularity low-power-consumption management is also supported.

The embodiment of the invention discloses a UVM-based UFCS protocol verification IP system and method, and the system comprises a UVM protocol driving unit which is used for generating UFCS protocol verification excitation and comprises a Baud rate training controller and a protocol wrapper; the UVM protocol analysis unit is used for verifying the UFCS protocol message received from the equipment to be tested and comprises a version self-adaptive decoder and a verification engine; the UVM intelligent monitoring unit is used for monitoring a protocol interaction process and performing compliance analysis, and comprises a violation detector and a coverage rate statistical model; and the UVM reusable test library is used for providing a standardized test sequence and an industrial standard test scene for the to-be-tested equipment and adjusting the test grade and the test content in response to a test adjustment instruction received by the configuration interface. According to the embodiment of the invention, the technical problems of insufficient compatibility verification, limited abnormal scene coverage, low verification efficiency and the like in UFCS protocol verification can be solved, full-stack verification from a physical layer to a protocol layer is realized, and the efficiency and reliability of UFCS protocol verification are improved.

The invention discloses an information interaction method and device. A data layer, an aggregation layer, a front data verification layer, a protocol adaptation layer, a protocol verification layer and an interconnection and intercommunication layer are arranged in a server, declaration data for a target resource providing platform are obtained through the data layer, and standardization processing is conducted on the declaration data through the aggregation layer. Performing prepositive verification on the standardized data through a prepositive data verification layer to obtain a first anomaly detection result, and processing the standardized data through a protocol adaptation layer according to a protocol of a target resource providing platform to obtain combined data in response to the first anomaly detection result that the standardized data is not abnormal, and performing protocol verification on the combined data through the protocol verification layer to obtain a second anomaly detection result, and sending the combined data to the target resource providing platform through the interconnection and intercommunication layer in response to the second anomaly detection result that the combined data is not abnormal. Therefore, abnormal data can be eliminated, and the accuracy of resource declaration is improved.

SYSTEM AND METHOD FOR EVALUATING UNIFORM RESOURCE LOCATOR 5 Disclosed is a system (100) and a method (500) for evaluating a Uniform Resource Locator (URL). The method (500) comprises extracting the URL from a message and assigning an initial risk score. The method (500) further comprises performing a protocol verification to verify a protocol of the URL and a domain assessment operation to determine whether the URL is an IP-address based URL, or FQDN 10 based URL. Furthermore, the method (500) comprises calculating a risk score for the URL based on protocol verification, domain assessment, evaluation of length of the URL, association with reputed domains, analyzing mean value of the URL, and identifying whether an entry corresponding to the URL is stored in a distributed ledger (108). Thereafter, the method (500) comprises determining a probability of 15 the URL being secure based on the calculated risk score and evaluating the credibility of the URL based on the probability.

This application relates to the field of integrated circuit technology and provides a physical IP verification device, verification method, computer equipment, and medium. The physical IP verification device includes: a first reusable multi-mode test sequence generator, a verification component physical interface, a second reusable multi-mode test sequence generator, and a verification component serial interface. This allows for the consideration of different simulation needs and scenarios, such as accelerating simulation efficiency and integrating verification. It supports protocol consistency verification, physical layer subsystem-level functional verification completeness, and standardized protocol verification. It provides a rich set of test vectors to meet the interfacing test scenarios and completeness verification needs of different layers, including the transaction layer, data link layer, and physical layer. It supports richly layered debugging interfaces and debugging methods, different physical interface versions and interface data bus widths, and also supports hierarchical and fine-grained low-power management.

This invention discloses a method, apparatus, device, medium, and product for formal verification of security protocols. The method includes establishing a discrete-time model of the target protocol based on the formal description result and protocol model of the target protocol; performing formal verification of the target protocol based on the protocol model and the discrete-time model to obtain the verification result of the target protocol. By establishing a discrete-time model, the time dimension is incorporated into the verification system, solving the problem of existing technologies ignoring the time factor, which leads to a disconnect between verification results and reality. By combining the protocol model and the discrete-time model for verification, effective verification of non-time-limited security properties such as authentication and confidentiality, as well as time-limited security properties such as freshness, can be achieved. This overcomes the limitation of existing technologies that can only verify non-time-limited properties, meets the verification needs of more types of security protocols, and expands the applicability of protocol verification.

The present disclosure relates to a method for verifying SSD disk reliability based on out-of-band testing and a storage device, and belongs to the field of testing of NVMe solid-state storage devices. The method comprises: counting a command set supported by an SSD disk and determining a to-be-tested state thereof, the command set at least including a command set supported by the SSD out of band; based on the to-be-tested state thereof, determining corresponding verification units respectively and determining an out-of-band testing scenario, the verification units including one or more of three dimensions of a protocol verification unit, a timing command verification unit and an influence verification unit, each verification unit being associated with a plurality of test commands in the command set; and according to the determined testing scenario matching the corresponding verification units, switching the SSD disk to the to-be-tested state and executing test commands associated with the corresponding verification units. The embodiments of the present disclosure verify the behavior, response and reliability of the SSD in various operating modes by traversing the testing scenario and the verification units, so as to improve the coverage of the out-of-band testing.

The invention discloses a function test method, device and equipment of a dynamic host configuration protocol and a storage medium, relates to the technical field of network testing, and discloses the function test method of the dynamic host configuration protocol, which comprises the following steps: obtaining a first port and a second port, the first port is used for verifying the dynamic host configuration protocol, and the second port is used for verifying the dynamic host configuration protocol; the second port is used as a mirror image port for analyzing the uplink message of the first port; according to the first port and the second port, respectively executing an IP allocation test, a lease term management test, an abnormal scene test and an address resolution protocol broadcast automatic test to respectively obtain an IP allocation test result, a lease term management test result, an abnormal scene test result and an address resolution protocol test result; and obtaining a target test result according to the IP allocation test result, the lease term management test result, the abnormal scene test result and the address resolution protocol test result. And comprehensive automatic testing of the dynamic host configuration protocol client in a plurality of functional links is realized.

The invention discloses a universal serial bus (USB) PD protocol verification system and method based on a universal virtual machine (UVM). The system comprises a parameterization test control unit, a protocol analysis verification unit, a power supply parameter monitoring unit, a role switching management unit and an abnormal scene construction unit. The parameterization test control unit generates a positive test case and a negative test case; the protocol analysis verification unit realizes protocol message deep analysis and real-time CRC verification; the power supply parameter monitoring unit obtains actual output parameters and compares the actual output parameters with protocol request parameters in a closed-loop mode; the role switching management unit supports Source, Sink and DRP role dynamic switching and maintains protocol state continuity; and the exception scene construction unit injects multiple types of exception states to verify the exception handling capability of the equipment. According to the invention, the technical problems of insufficient protocol deep analysis, disjunction of electrical parameters and protocol verification, discontinuous role switching state and the like in the existing verification technology are solved, the cooperative verification of the protocol layer and the power supply layer is realized, and the verification efficiency and coverage rate of the USB PD protocol chip are improved.

The invention relates to the technical field of industrial communication networks, in particular to a wireless communication chip prototype verification method and device, and the method comprises the steps: receiving an original data stream of industrial field wireless communication equipment, and carrying out the preprocessing and format conversion to generate a digital signal; loading a WIA-FA protocol stack model by utilizing a programmable hardware platform to carry out hardware-level protocol simulation; a dual-radio-frequency chip architecture is adopted to fix transmitting and receiving modes, and noise introduced by existing transmitting and receiving switching is avoided; time sequence deviation and signal distortion are identified by monitoring time delay, throughput and reliability indexes in real time; dynamically adjusting protocol parameters or radio frequency configuration based on the deviation analysis result; in-phase / orthogonal unbalanced self-calibration is realized by combining a coupling loop structure; and finally generating a comprehensive verification report to compare a hardware simulation result with an expected performance index. According to the WIA-FA protocol verification method, the deviation between a simulation environment and real hardware deployment is effectively reduced, and the accuracy and efficiency of WIA-FA protocol verification are improved.

This invention relates to the field of chip testing and discloses a method, device, and storage medium for generating mapping instances of a SoC chip. The method includes: reading a preset IO mapping table and parsing the IO mapping table to obtain protocol information, PAD macro definitions, and mapping information for each instance; concatenating the PAD macro definitions of each instance corresponding to a protocol to construct a verification medium connection for each protocol; generating instance information for parameterized tests corresponding to each instance based on the protocol information; receiving a configuration file for each protocol, and combining the protocol information, instance information, and mapping information corresponding to each instance in pairs according to the configuration file of each protocol to generate a test case set. In this embodiment of the invention, by fusing protocol verification and IO mapping verification of test cases, full coverage of the design space of the PAD macro definition IO mapping and protocol data for testing is achieved.

The application provides a retry mechanism verification system and method, and relates to the technical field of multi-core processor interconnection bus protocol verification. The system comprises at least one master node monitoring device, a central cooperative processor and at least one request node agent. The master node monitoring device collects the running state signals inside the master node in real time, generates a retry prediction information package containing the predicted expected retry event type and the retry prediction value, and the retry prediction value indicates the future time of the predicted retry event occurrence; the central cooperative processor calculates the request sending delay based on the retry prediction value, generates a request strategy package containing the delay, and sends it to the request node agent; and the request node agent sends a request sequence to the bound request node after the request sending delay to trigger the retry event. The application predicts the retry event occurrence time and accurately controls the excitation sending time accordingly, thereby improving the verification method efficiency and the scene coverage.

The invention belongs to the technical field of software testing, and relates to a multi-protocol self-adaptive intelligent assertion engine system and a cross-platform verification method. The system comprises a protocol sensing layer, a unified description layer, an adaptive execution layer and an intelligent analysis layer, the protocol perception layer comprises a protocol feature library, a multi-dimensional feature extractor, a confidence coefficient decision engine and a protocol version identification subunit; the unified description layer comprises a DAL grammar parser, an abstract syntax tree generator and a protocol independent verification rule converter; the adaptive execution layer comprises a verifier factory, a class loader isolation container, a protocol-verifier mapping table and an execution result aggregator; the intelligent analysis layer comprises a nested data comparison engine, a binary difference calculation unit, a multi-dimensional result correlation analyzer and a visual renderer. The protocol identification accuracy is high, and the code reuse rate is high; the maintenance cost is low; multi-dimensional verification is realized; the new protocol is short in adaptation period and high in expansion capability, and the data flow difference in the multi-protocol interaction link can be visually displayed.

This invention belongs to the field of power system automation technology and discloses an interactive matching and protocol verification system, method, equipment, and medium based on the physical model of a relay protection device and the IEC 61850 communication information model. It addresses the problems of difficulty in matching terminals with protocol objects, insufficient static verification, separation of hardware testing and communication verification, and low efficiency of human-machine collaboration. The system includes a physical electrical model management module, a terminal-information model path mapping module, an interactive matching module, a measurement and acquisition module, a communication monitoring module, a mapping verification and protocol verification module, and a report output and version management module. This invention connects the physical terminals and information model paths, realizes joint verification of hardware excitation and communication messages, and constructs a traceable closed-loop verification process.

This invention discloses a layered modeling and combined verification method for the LwM2M protocol based on UPPAAL. Its key feature is the addition of attacker automata to the functional layer model to construct a security layer model. By selectively activating attacks through global attack mode variables, the security attributes of the protocol under attacks such as man-in-the-middle, replay, and denial-of-service are verified. The method introduces probabilistic semantics, packet loss, latency, and retransmission mechanisms into the upper-layer model to construct a performance layer model. Statistical models are used to detect and evaluate the protocol's performance indicators in real-world network environments. Compared with existing technologies, this invention decomposes the complex protocol verification problem into independent and composable layers, effectively reducing modeling complexity, avoiding state space explosion, and achieving comprehensive verification of the LwM2M protocol's functionality, security, and performance. The method is simple, effective, and has promising application prospects.

The application discloses a PCIE ordering and reordering verification method, relates to the technical field of computer bus protocol verification, and discloses a PCIE ordering and reordering verification method, which generates expected data flow with sequence labels by referring to a reference model, combines dynamic comparison of a measured device output flow, and introduces a credit management module to simulate a physical layer blocking scene, solves the problems of insufficient timing accuracy of the reference model and low artificial verification efficiency in the prior art, can improve verification accuracy and efficiency, and effectively captures dynamic reordering behavior.

The invention discloses a PCIE sorting and resorting verification method, relates to the technical field of computer bus protocol verification, and discloses a PCIE sorting and resorting verification method which comprises the steps of generating an expected data stream with a sequence label through a reference model, combining dynamic comparison of output streams of tested equipment, and introducing a credit management module to simulate a physical layer blocking scene. The problems that in the prior art, reference model time sequence precision is insufficient and manual verification efficiency is low are solved, verification accuracy and efficiency can be improved, and dynamic reordering behaviors are effectively captured.

The invention relates to an out-of-band test-based SSD (Solid State Disk) reliability verification method and storage equipment, and belongs to the field of test of NVMe (Non-Volatile Memory Express) solid-state storage equipment. The method comprises the steps that a command set supported by an SSD disk is counted, the to-be-tested state of the SSD disk is determined, and the command set at least comprises a command set supported by the SSD disk out of band; on the basis of the to-be-tested states, corresponding verification units are determined respectively, an out-of-band test scene is determined, the verification units comprise one or more of a protocol verification unit, a time sequence command verification unit and an influence verification unit, and each verification unit is associated with a plurality of test commands in a command set; and matching the corresponding verification unit according to the determined test scene, switching the SSD to a to-be-tested state, and executing a test command associated with the corresponding verification unit. According to the embodiment of the invention, the behavior, response and reliability of the SSD in each operation mode are verified by traversing the test scene and the verification unit, so that the coverage of out-of-band test is improved.

This invention provides a verification system and method for a retry mechanism, relating to the field of multi-core processor interconnect bus protocol verification technology. The system includes: at least one master node monitoring device, a central coprocessor, and at least one request node agent. The master node monitoring device collects real-time operating status signals from within the master node and generates a retry prediction information packet containing the predicted retry event type and retry prediction value. The retry prediction value indicates the future time of the predicted retry event. The central coprocessor calculates the request sending delay based on the retry prediction value and generates a request policy packet containing the delay, which is sent to the request node agent. After the request sending delay, the request node agent sends a request sequence to its bound request node to trigger the retry event. This invention improves the efficiency and scenario coverage of the verification method by predicting the retry event occurrence time and precisely controlling the timing of stimulus transmission accordingly.

This invention belongs to the field of software testing technology and relates to a multi-protocol self-adaptive intelligent assertion engine system and a cross-platform verification method. The system includes a protocol awareness layer, a unified description layer, an adaptation execution layer, and an intelligent analysis layer. The protocol awareness layer includes a protocol feature library, a multi-dimensional feature extractor, a confidence decision engine, and a protocol version identification subunit. The unified description layer includes a DAL syntax parser, an abstract syntax tree generator, and a protocol-independent verification rule converter. The adaptation execution layer includes a validator factory, a class loader isolation container, a protocol-validator mapping table, and an execution result aggregator. The intelligent analysis layer includes a nested data comparison engine, a binary difference calculation unit, a multi-dimensional result correlation analyzer, and a visualization renderer. This invention features high protocol recognition accuracy, high code reusability, low maintenance costs, multi-dimensional verification, short new protocol adaptation cycle, strong scalability, and the ability to intuitively display data flow differences in multi-protocol interaction links.

The embodiment of the invention provides a verification command conversion method and device and hardware simulation equipment. The verification command conversion method is applied to the verification command conversion device, the verification command conversion device comprises an acquisition module, a first conversion module, a second conversion module and a PCIe core, and the method comprises the steps that the acquisition module acquires a protocol verification command; the first conversion module converts the protocol verification command into an instruction sequence; the second conversion module converts a first instruction used for indicating hardware behaviors in the instruction sequence into hardware behavior excitation; and the PCIe core generates a protocol data packet based on hardware behavior excitation, and sends the protocol data packet to the to-be-tested verification module. According to the verification command conversion method, the strong dependence of external real equipment can be eliminated, verification distortion caused by external equipment software driving and protocol consistency verification loss caused by external equipment compatibility are avoided, and a fragmented debugging tool chain can be opened, so that the debugging cost is reduced.

The invention relates to the technical field of electronic testing, in particular to an automatic testing method for a retiming card, which comprises the following steps of: constructing a BSI boundary scan testing system, performing coordination control through upper computer software, and forming at least one boundary scan chain by adopting the BSI boundary scan testing system; automatically executing a test sequence through the upper computer software, wherein the test sequence comprises a power supply input test, an IIC communication test, a differential signal error code test, an IO network interconnection test, a power supply on-off test and a GND connectivity test; automatically judging PASS or FAIL based on a test result, and generating a test report; wherein the test report comprises pin-level fault positioning information and test coverage rate statistics. By constructing a multi-link boundary scanning system, digital signal testing, power management and communication protocol verification are integrated, the testing precision and speed are remarkably improved, and comprehensive automatic testing of the Retimer Card is achieved.

The invention discloses a message data serialization packaging and analyzing method supporting interface protocol verification, which comprises the following steps of: 1) acquiring a message data structure, and realizing digital conversion of a message protocol; (2) controlling sub-field splicing of a word bit field; calling a packaging function, judging whether protocol verification is executed or not, and performing bit field splicing; (3) carrying out serialized packaging on the full message field; calling a packaging function, judging whether protocol verification is executed or not, and performing serialization processing; 4) deserialization unpacking of the byte stream: calling a packaging function, judging whether to execute protocol verification, and performing deserialization analysis of the byte stream; 5, the fields of the control words are split and analyzed into bit field sub-fields, a packaging function is called, whether protocol verification is executed or not is judged, and control word bit field split is carried out. According to the method, data serialization and deserialization are packaged into a standard function library, and a set of standard message data processing method is provided.

The application provides a PCIe verification IP automatic integration method supporting multiple working modes, and the method comprises the following steps: providing a configurable configuration file; rendering a template file by using a python-based template engine jinja2 of an automatic verification generation platform; automatically completing the connection relationship between a PIPE level and a SerDes interface level PCIe verification IP and a DUT; automatically generating a PCIe VIP task library; and providing a user with a basic task library for basic transmission path and PCIe protocol verification. The application greatly reduces the platform building time in the front-end verification, so that the verification engineers can pay more attention to the protocol and function verification, meanwhile, the application avoids the time waste caused by some unexpected human errors, greatly improves the simulation speed and the debugging efficiency, and is used for the initial development of the front-end verification. The Serdes level simulation adopts the behavior description level code of the PHY, is closer to the real chip, and is more suitable for the regression test in the later stage of the front-end verification.

The invention discloses an automatic password scheme verification method based on large model semantic analysis, which comprises the following steps of: S1, performing segmentation and syntactic analysis on a target password scheme document to form a protocol text fragment set; s2, splicing a task instruction with each protocol text fragment to form a structured input format; s3, performing semantic embedding processing by using an improved CAIRO algorithm model; s4, outputting an entity-relation triple set through a path modeling mechanism; s5, carrying out dynamic adjustment and weight normalization optimization, and generating an optimized entity-relation triple set; s6, converting the optimized entity-relation triple set into a communication behavior semantic graph; s7, performing protocol consistency analysis on the communication behavior semantic graph, and outputting a risk assessment report; and S8, generating a protocol verification report according to the risk assessment report. Through automatic protocol verification, entity relationship optimization and semantic analysis, the security and efficiency of a password scheme are improved.

The invention discloses an integrated circuit test method, system, platform and device, a medium and a product, and relates to the technical field of integrated circuit design. Comprising the following steps: acquiring a loopback test component, a selection component, a first protocol verification component, a first to-be-tested model and selection information of a target integrated circuit at an electronic system level, a second to-be-tested model and selection information of the target integrated circuit at a register transmission level, and a test case; furthermore, a test system of the target integrated circuit can be established based on the loopback test component, the first to-be-tested model, the second to-be-tested model, the selection component and the first protocol verification component. In the test process, a target test result of the target integrated circuit can be generated based on the selection information of the target integrated circuit at the electronic system level and the register transmission level, the test case and the test system of the target integrated circuit. In this way, the problem that verification operation between the two levels is relatively split can be solved.

The invention discloses a zero sum noise encryption data transaction method, which relates to the technical field of data processing, and comprises the following steps: a server generates an initial weight vector of a global model, and distributes the initial weight vector to each participant for initialization; each participant performs a plurality of rounds of iterative training based on the initial model parameters to obtain a local update quantity, executes a differential privacy and zero sum noise encryption process to generate joint noise, encrypts the joint noise and the local update quantity together to generate an encrypted packet, and sends the encrypted packet and a signature to a server; the protocol verification module decrypts the encrypted packet and the signature, calculates precision on a verification set by using decrypted model parameters, and judges whether an uploading result is valid or not through precision and a performance threshold value; the protocol verification module carries out aggregation updating on all the verified participants to obtain updated global parameters; and after the global aggregation is completed, the protocol verification module performs consistency verification on the signatures uploaded by the participants, and distributes the updated global parameters to the participants.

The invention relates to a debugging method and device, a server, a medium and a product, the method is applied to a server without a GPU module, the server comprises a simulation GPU module response module, the simulation GPU module response module is used for responding to request data, and the method comprises the following steps: sending interface request data to the simulation GPU module response module through a GPU module monitoring module in the server; receiving response data fed back by the simulation GPU module response module based on the interface request data; and debugging the GPU module monitoring module according to the response data. According to the method, the simulation GPU module response module is deployed in the server without the physical GPU module, the response data corresponding to the interface request data can be accurately obtained, the GPU module monitoring module is debugged based on the response data, the communication behavior of the real GPU module can be effectively simulated, the building cost and hardware dependence of the debugging environment are remarkably reduced, and the debugging efficiency is improved. And reliable support is provided for communication protocol verification and system performance optimization.