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Verification method of FPGA universal configurable UART protocol based on UVM

A verification method and protocol technology, applied in the field of FPGA logic verification, can solve problems such as low verification efficiency and achieve the effect of improving verification efficiency

Inactive Publication Date: 2016-06-29
CHINA ELECTRONIC TECH GRP CORP NO 38 RES INST
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0005] The purpose of the present invention is to solve the low defect of verification efficiency in the prior art, provide a kind of verification method based on UVM-based FPGA general configurable UART protocol to solve the above problems

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  • Verification method of FPGA universal configurable UART protocol based on UVM
  • Verification method of FPGA universal configurable UART protocol based on UVM

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Embodiment Construction

[0026] In order to have a further understanding and understanding of the structural features of the present invention and the achieved effects, the preferred embodiments and accompanying drawings are used for a detailed description, as follows:

[0027] like figure 2 Shown, a kind of verification method of FPGA general configurable UART agreement based on UVM, comprises the following steps:

[0028] Step 1. Build the UVM verification platform

[0029] The UVM verification platform is built with SystemVerilog and UVM class library; the UVM verification platform includes a UART verification environment, a scoreboard and a UART configuration module; the first agent and the second agent are encapsulated in the UART verification environment; the second agent is encapsulated in the first agent A monitor, an incentive generator, and a driver; the second monitor is encapsulated in the second agent;

[0030] Step 2. Define the UART_config class to form a URAT configuration module

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Abstract

The invention relates to a verification method of an FPGA universal configurable UART protocol based on UVM. The verification method comprises the steps of finishing an overall framework of UART protocol verification by utilizing a UVM verification platform structure and a verification idea; and setting a UART configuration type in which all the parameter information of the UART protocol is packaged, and sending the UART protocol parameter information to related parts of platforms such as a driver, a monitor and a grade recording board through a config-db mechanism provided by the UVM. During instantiation of a top layer, a universal parameter-configurable UART protocol FPGA verification platform can be realized only by setting corresponding parameter information such as a Baud rate, a data bit, a stop bit and a verification mode based on protocol requirements of a to-be-tested UART by the user. The verification method of the FPGA universal configurable UART protocol based on the UVM has the advantages of being efficient and universal. A test case meeting requirements can be generated automatically only by setting corresponding UART parameters at the top layer by an FPGA design engineer or verification engineer, and a verification environment is unnecessary to develop again, so that the verification efficiency is improved greatly.

Description

technical field [0001] The present invention relates to the field of serial asynchronous communication technology of data and FPGA logic verification technology, specifically a kind of verification method of FPGA general configurable UART protocol based on UVM. Background technique [0002] UART is an asynchronous serial interface that can support short-distance and long-distance transmission at the same time, and is widely used in data exchange between microcomputers and peripherals. UART adopts a serial asynchronous communication mode, and the receiving and sending parties do not use a common reference clock, but perform data transmission in units of characters. There is no fixed time interval requirement between characters, but the bits in each character are transmitted at a fixed time (baud rate). The method for the sending and receiving parties to achieve synchronization is to set the start bit and stop bit in the character format, that is, before a valid character is ...

Claims

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Application Information

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IPC IPC(8): G06F11/22G06F13/42
CPCG06F11/221G06F13/4291
Inventor 习建博夏际金骆传慧邓庆勇朱鹏
Owner CHINA ELECTRONIC TECH GRP CORP NO 38 RES INST
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