23 results about "Fpga design" patented technology

Systems or methods of the present disclosure may provide a design tool for adjusting designs implemented on programmable logic devices. The present disclosure includes receiving documentation and receiving a full text search. The documentation may include user guides, technical specifications, and design files such as HDL code, constraints, timing reports, and / or design assistant / rule violation (DRC) reports. The present disclosure also includes determining semantic search for embedding vectors based on the documentation and the full text search. Furthermore, the present disclosure includes providing the semantic search to a large language model (LLM).

The invention discloses an FPGA test case automatic generation system and method based on a large language model. The system comprises a demand input module, a demand structuring module, a large language model case generation module, a case confirmation module, a verification execution module and a closed-loop optimization module. The large language model can automatically analyze the unstructured demand document and extract key information such as function points, input and output, boundary conditions and the like, and manual one-by-one interpretation is not needed. A big language model is guided through Prompt Engineering to dismantle complex requirements into test key points which cannot be subdivided, and it is ensured that all logic branches are covered by tests. The large language model can dynamically generate diversified test cases based on test key points, including a normal process, an abnormal process and an edge scene. And in combination with FPGA design specifications, historical error cases and other plug-in knowledge bases, the large language model can generate test cases closer to actual hardware behaviors.

The invention relates to a trigger signal identification method and device, equipment and a storage medium. The trigger signal identification method comprises the following steps: acquiring an FPGA design code to be subjected to trigger signal identification; traversing at least one module code in the FPGA design codes, and extracting trigger signal features from block statements in the module codes and / or a target list; wherein the target list is composed of at least one field corresponding to the preset identifier, and the at least one field is used for representing the trigger signal information; performing function identification on the trigger signal features, and determining at least one trigger signal; and generating a trigger signal identification result according to the at least one trigger signal and the reference name of the at least one trigger signal in the corresponding module code. According to the method provided by the invention, the accuracy of trigger signal identification is improved, and the adaptability to complex design scenes is higher.

The application discloses a FIFO interface multi-channel DMA controller based on FPGA, which comprises an input data distribution module, an input data cache module, an output data distribution module, an output data cache module, a DMA scheduling module, a DDR output module and a DDR interface module; is used for caching multi-channel high-speed data of multiple data sources in a memory, does not occupy on-chip RAM resources of the FPGA, realizes parallel, independent and efficient storage and storage of multi-channel data, a data interaction interface is a standard FIFO interface, a user does not need to care about complex DDR3 / 4 (Double Data Rate) interface timing and multi-channel data scheduling, programming is realized by using a hardware description language, parameterization configuration is adopted, other FPGA platforms are compatible, the application can be called in FPGA design as an IP, a development cycle is shortened, and development efficiency is improved.

The invention discloses a crystal oscillator electric aging test implementation method based on FPGA (Field Programmable Gate Array) design, which belongs to the technical field of crystal oscillator electric aging tests and comprises the following steps of: inserting an electric aging test board on which an electric aging product is mounted on a metal aging rack in a high-temperature oven; the electric aging product information is recorded in the electric aging program; after the electric aging test main control program receives an instruction that the electric aging program starts to test, frequency signal inspection of all electric aging products on the electric aging test board is rapidly completed; the inspection result is transmitted to the electric burn-in program, and the electric burn-in test main control program stores the inspection result at the same time; and after three days of frequency signal inspection, checking the electric aging current situation of the electric aging product in the electric aging program. According to the electric aging test implementation method, the electric aging test main control program is embedded in the FPGA unit, and the frequency signals of all the electric aging products on the same electric aging test board can be synchronized by using the strong parallel processing capability of the FPGA.

The application relates to an FPGA design code credible generation and verification method and system based on a large language model, wherein the system comprises: a user interaction layer used for receiving input information of a user and converting the input information into standardized requirement information; an understanding and generation layer used for performing semantic analysis on the requirement information and generating a preliminary design result, the preliminary design result comprising an RTL code and a test framework; a verification analysis layer used for performing multi-stage engineering verification on the generated RTL code; a structured representation layer used for constructing a unified design intermediate representation in a system to make each stage take the same structural semantics as a benchmark; and a core control layer used for scheduling the running processes of the user interaction layer, the understanding and generation layer, the verification analysis layer and the structured representation layer. The application can improve design efficiency, reliability and engineering controllability.

The application provides a multifunctional test chip and method based on a PXI architecture, and relates to the technical field of test chips; the chip comprises a bus interface, a functional module group and an address controller; the bus interface interacts with an upper computer through a PXI bus; the functional module group comprises pulse sending, detection, analog quantity acquisition / output, serial communication, a storage controller and a temperature acquisition module, and can realize pulse signal transceiving, analog quantity processing, serial communication, data storage and temperature acquisition; the address controller divides an address space into eight subspaces, and precise control is realized. The control method comprises the steps of initializing an interface circuit, executing pulse sending and detection, analog quantity output and acquisition, EEPROM operation, UART communication and temperature acquisition and the like. The application integrates special modules, replaces traditional FPGA design, improves performance and reliability, reduces resource waste, reduces cost, shortens the development cycle, and is suitable for complex test scenes such as spaceflight measurement and control.

The invention provides a method and device for constructing an NTT accelerator based on an FPGA. The construction method comprises the steps that user input is received, the user input comprises a target algorithm selected from multiple NTT algorithms and the available resource quantity of the FPGA, and the multiple NTT algorithms comprise standard NTT, four-step NTT and ten-step NTT; determining a target architecture template corresponding to the target algorithm from a plurality of hardware architecture templates preset for the plurality of NTT algorithms; each hardware architecture template is obtained by combining multiple types of preset operator units, and at least comprises a basic NTT unit configured according to the parallelism degree of the input data. Next, executing a plurality of rounds of iteration aiming at the degree of parallelism, wherein any round of iteration comprises the following steps of: calculating the resource quantity required by the target architecture template under the current value of the degree of parallelism; under the condition that the required resource quantity does not accord with the available resource quantity, reducing a parallelism degree value; and otherwise, determining the current value of the parallelism degree as the target value. Therefore, according to the target value of the parallelism degree, a hardware architecture code used for FPGA design is generated according to the target architecture template.

The invention provides a DO-254 standard automatic inspection method, system and device for FPGA design for airworthiness certification and a storage medium. Comprising the following steps: configuring an inspection rule and a design index threshold according to a DO-254 standard; generating a TCL script for driving the FPGA design tool based on the rule; calling and executing the TCL script through a Python environment, and generating a time sequence, a utilization rate and a DRC report; a Python script is used for analyzing the report, and key design indexes of the worst negative time sequence margin, the resource utilization rate and the DRC error number are extracted; and comparing the index with a threshold value, and automatically generating a DO-254 standard conformity judgment report. Through cooperation of the TCL and the Python, full-process automation of DO-254 conformity check of FPGA design is realized, the problems of low manual check efficiency and poor consistency are solved, and the efficiency and reliability of airworthiness certification are remarkably improved.

The invention discloses a macro cell legalization method, system and device for an FPGA chip and a medium, and the method comprises the steps: carrying out the global layout of an FPGA design netlist, and determining the initial positions of a macro cell and other design units in a global layout coordinate system; acquiring coordinate positions of other design units directly connected with each macro unit in the global layout coordinate system; respectively sequencing the coordinate positions of all other design units connected with each macro unit along the X-axis direction and the Y-axis direction to obtain an X coordinate sequence and a Y coordinate sequence; determining an anchor point corresponding to the macro cell based on the X coordinate sequence and the Y coordinate sequence; minimizing the distance between the candidate placement position of each macro cell and the corresponding anchor point to determine the legal placement position of each macro cell on the FPGA chip; according to the method and the device, the limitation of determining the anchor point of the macro cell in the global layout can be avoided, the deviation between the position of the macro cell and the anchor point after legalization is reduced, and the layout time sequence performance of the FPGA chip is optimized.

The application discloses a memory conversion method, comprising the following steps: obtaining an initial netlist; traversing the initial netlist to determine a plurality of first memories and a plurality of second memories capable of being mapped as BSRAM; obtaining the number of read-write ports and address size of each first memory and each second memory; mapping each first memory as BSRAM of corresponding types and quantities according to the number of read-write ports, data width and address width of each first memory, or mapping each second memory as BSRAM of corresponding types and quantities according to the number of read-write ports, data width and address width of each second memory. The application further discloses a system, a computer device and a readable storage medium. The scheme provided by the application can be applied in chip design or FPGA design, when the design contains a logically represented memory, the memory can be replaced by 1 or several BSRAMs, and the chip area occupied by the memory can be effectively reduced.

A system and method for routing Field Programmable Gate Arrays (FPGAs) includes an input device for acquiring a netlist with defined source, sink, and intermediate nodes, and processing circuitry that features a design router. The router leverages a negotiated-congestion routing component, which promotes the shared use and negotiation for intermediate nodes. The negotiation process employs a congestion cost based on several factors, including base, historical, and present usage costs, alongside node capacity. This system is characterized by a historical cost function focused on the base cost of nodes, favoring the use of those with costs below a specified threshold. A display device incorporated within the system allows for the continuous monitoring of the routing procedure and the efficiency of resource usage. The technology aims to streamline FPGA design by optimizing signal routing for performance and area efficiency.

The application discloses a FPGA design method based on partition debugging kernel voltage, and relates to the technical field of FPGA.The method downloads the code stream corresponding to the chip hardware design including the internal circuit of the chip and a plurality of power supply regions to the FPGA chip, each power supply region is used for providing the acquired kernel voltage to the corresponding local power consumption region, when the chip cannot normally work in the state that the kernel voltage of the basic voltage value is acquired in all power supply regions, the kernel voltage acquired by at least one power supply region is adjusted through the power supply pin of the chip until the chip normally works, or until the local power consumption region with the fault is determined.The method can make the chip work normally or can be positioned to the fault region by adjusting the kernel voltage of the plurality of power supply regions, and the partition debugging method has high flexibility, is easier to debug, makes the chip work normally, or can be more accurately positioned to the fault region.

The invention discloses an FPGA routing congestion prediction method based on a heterogeneous graph neural network, and the method comprises the steps: obtaining a netlist file in an FPGA design process, extracting the topological information of the file, and constructing a netlist subgraph; fPGA architecture information is obtained, and an architecture subgraph is constructed according to the architecture information; obtaining a layout file in the FPGA design process, extracting position information of each block in the file to construct a spatial mapping edge, and projecting nodes in the netlist sub-graph to the architecture sub-graph through the spatial mapping edge to obtain an integrated heterogeneous graph; constructing a heterogeneous graph neural network matched with the heterogeneous graph, wherein the heterogeneous graph neural network comprises a feature initialization module, a message passing module and a reading module; a data set is constructed according to the heterogeneous graph to train a heterogeneous graph neural network, and a neural network structure search strategy is used to optimize a message passing module; and inputting the heterogeneous graph into the heterogeneous graph neural network to obtain routing congestion information. According to the method, the accuracy of the FPGA routing congestion prediction result can be improved, the generalization ability is higher, and the time for reasoning, training and data preprocessing is shortened.

The application discloses a high-speed parallelization FPGA design architecture based on OpenCL, and in view of the characteristics of large data volume and high real-time requirement in the field of radar signal processing, a complete CPU+FPGA heterogeneous acceleration scheme supporting multiple parallel optimization modes is provided.The scheme is optimized for common parallel optimization modes such as pipeline parallelism, multi-channel parallel optimization and loop iteration, and three memory access mechanisms, global memory, local memory and direct transmission between kernels, are provided to improve the data transmission efficiency in the parallelization calculation process.The architecture proposed in the application realizes related radar algorithms including two-dimensional FFT calculation and special point calculation, and compared with the efficiency before optimization, analysis results are given, which prove that the proposed architecture can meet the data transmission requirements of most parallel processing.

Systems or methods of the present disclosure may provide a design tool for adjusting designs implemented on programmable logic devices. The present disclosure includes receiving a request to generate or modify code. The present disclosure also includes automatically invoking an agent in response to the request and processing a draft code. Furthermore, the present disclosure includes returning results based on the draft code.

The invention relates to the technical field of SoC testing, in particular to a large SoC testing method and device based on cascade connection of multiple FPGA chips. The method comprises the following steps: evaluating the resource occupancy rate of each module on the SoC; according to the resource occupancy rate of each module, respectively mapping each module to a plurality of FPGA chips; the two adjacent FPGA chips are sequentially connected in series, so that data communication of the two adjacent FPGA chips is carried out, and cascading of all the FPGA chips is achieved; respectively carrying out integration and implementation processing on each FPGA design to generate a bit stream file, and burning the bit stream file to each FPGA chip; and after all the FPGA chips are reset according to the correct time sequence, all the FPGA chips are used as a whole to carry out SoC function testing. According to the invention, the problem of resource limitation of a single FPGA chip can be solved, and a plurality of cascaded FPGA chips are utilized to realize the function test of a complete large SoC system.

The invention discloses a network-based FPGA (Field Programmable Gate Array) software code automatic physical test method and system, a server, terminal equipment, a test card and a tested daughter card are accessed to the same network, and the method comprises the following steps: starting the two cards to execute hardware self-inspection, connectivity verification and identity recognition, and reporting a state to the server; a terminal imports a to-be-tested FPGA design project, a testbench and a test excitation file, a system analyzes the file and configures port signal attributes, a test FPGA project and adaptive excitation are automatically compiled and generated, and a third-party tool is called to generate a test FPGA bit stream file; remotely loading a bit stream file and excitation, and starting and monitoring a test process; and the test FPGA collects interface data and feeds back the interface data to the server, and analyzes the data to generate a report. A test cloud platform is constructed, the problems of complex test environment and the like are solved, the test efficiency is effectively improved, the complexity and error risk are reduced, the reliability is enhanced, and a reliable scheme is provided for FPGA design verification.

Systems or methods of the present disclosure may provide a design tool for adjusting designs implemented on programmable logic devices. The present disclosure includes receiving a query from a user and processing commands provided by the user associated with the query. The present disclosure also includes providing the query and the commands to a large language model (LLM), selecting one or more relevant file types based on the query, and executing searches scoped to the one or more relevant file types and filtering out irrelevant information via the LLM. Furthermore, the present disclosure includes receiving a set of results from the LLM and filtering and ranking the set of results based on relevance to the query.

The invention discloses an FPGA layout and wiring acceleration method and system based on RTL code features, and belongs to the technical field of FPGA design and automation, the implementation of the method comprises the following steps: RTL code feature extraction and analysis: analyzing the structural features, resource requirements and time sequence attributes of RTL codes, and providing a data basis for physical constraint generation; physical constraint automatic generation: based on code features and FPGA resource distribution, automatically generating a Pblock division and implementation strategy; incremental layout and wiring multiplexing: realizing incremental compiling and incremental layout and wiring, and improving the compiling speed; and closed-loop feedback optimization: dynamically optimizing constraint generation rules and strategy selection logic based on a historical layout result. According to the method, the problems of high manual dependence, low iteration efficiency and frequent resource conflicts in the existing FPGA layout wiring technology can be solved, manual layout experience dependence is eliminated, iteration time consumption is greatly shortened, and design maintainability is improved.

The invention discloses a Block RAM (Random Access Memory) process mapping method. In the target FPGA design, obtaining a target memory to be processed and current attribute information; if the non-standard memory template register transfer level design is determined, obtaining current random access memory layout netlist information, a current read-write port and a current layout netlist; and querying the current layout netlist through a layout netlist traversal search method to obtain target memory query description information, matching the target memory query description information with a memory splitting processing method library, and obtaining a target standard splitting processing memory according to a matched memory splitting processing mode so as to realize Block RAM process mapping. The problems that the workload is large due to RTL rewriting and the product performance is poor due to mapping to non-special physical storage resources are solved, and accurate process mapping of the split memory is improved.

The application belongs to the field of integrated circuits, and particularly relates to a FPGA layout method based on reinforcement learning. First, according to an input netlist file, logical units contained in a FPGA design circuit are extracted, and then initialization layout operation of the logical units is completed; in view of the slow convergence problem of a traditional simulated annealing method layout, multiple search region construction methods are proposed, which can effectively improve the search efficiency of the layout solution space; on this basis, an optimal search region selection method based on reinforcement learning is proposed, which can adaptively select the optimal search region to perform the exchange operation of the logical units. The layout method can greatly reduce the time required for FPGA layout while maintaining the required wire length and critical path delay.

The application discloses an automatic simulation verification method of a Block_RAM test case, and relates to the technical field of FPGA.The method analyzes an RTL level description file of the Block_RAM test case, extracts information of the types of input and output signals, signal parameters and the like, and further identifies data signals, address signals, clock signals and control signals to establish a signal dictionary.According to the signal dictionary, the construction of a test platform can be automatically completed, and according to the characteristics of various signals, control signals matched with working modes and random assignment modes of input signals can be automatically generated, so that the test under the current working mode can be quickly completed, and then the full coverage test of various working modes of the Block_RAM can be quickly completed, which is beneficial to guaranteeing the correctness of FPGA design.