43 results about "Fpga design" patented technology

Systems or methods of the present disclosure may provide a design tool for adjusting designs implemented on programmable logic devices. The present disclosure includes receiving documentation and receiving a full text search. The documentation may include user guides, technical specifications, and design files such as HDL code, constraints, timing reports, and / or design assistant / rule violation (DRC) reports. The present disclosure also includes determining semantic search for embedding vectors based on the documentation and the full text search. Furthermore, the present disclosure includes providing the semantic search to a large language model (LLM).

The invention discloses an FPGA test case automatic generation system and method based on a large language model. The system comprises a demand input module, a demand structuring module, a large language model case generation module, a case confirmation module, a verification execution module and a closed-loop optimization module. The large language model can automatically analyze the unstructured demand document and extract key information such as function points, input and output, boundary conditions and the like, and manual one-by-one interpretation is not needed. A big language model is guided through Prompt Engineering to dismantle complex requirements into test key points which cannot be subdivided, and it is ensured that all logic branches are covered by tests. The large language model can dynamically generate diversified test cases based on test key points, including a normal process, an abnormal process and an edge scene. And in combination with FPGA design specifications, historical error cases and other plug-in knowledge bases, the large language model can generate test cases closer to actual hardware behaviors.

The invention discloses an FPGA (Field Programmable Gate Array) self-excitation signal detection method and device based on a signal feedback loop, and the method comprises the steps: firstly, reading a received FPGA hardware description language code file, and integrating all modules in an FPGA code to form an overall code file from top to bottom; secondly, mapping the overall code file of the FPGA into a signal transmission network according to a transmission relationship among signals in the overall code file of the FPGA; and thirdly, searching all signal feedback loops in the signal transmission network, calculating signal feedback probabilities, selecting and recording the signal feedback loops of which the signal feedback probabilities are greater than a set threshold, and extracting signals in the signal feedback loops as self-excitation signals to be output. According to the method, the self-excitation signal in the FPGA design and the occurrence probability of the self-excitation signal can be effectively detected, the method is easy to use and low in investment cost, and the requirement for self-excitation signal detection when the triple modular redundancy design is carried out can be well met.

The invention relates to a trigger signal identification method and device, equipment and a storage medium. The trigger signal identification method comprises the following steps: acquiring an FPGA design code to be subjected to trigger signal identification; traversing at least one module code in the FPGA design codes, and extracting trigger signal features from block statements in the module codes and / or a target list; wherein the target list is composed of at least one field corresponding to the preset identifier, and the at least one field is used for representing the trigger signal information; performing function identification on the trigger signal features, and determining at least one trigger signal; and generating a trigger signal identification result according to the at least one trigger signal and the reference name of the at least one trigger signal in the corresponding module code. According to the method provided by the invention, the accuracy of trigger signal identification is improved, and the adaptability to complex design scenes is higher.

The application discloses a FIFO interface multi-channel DMA controller based on FPGA, which comprises an input data distribution module, an input data cache module, an output data distribution module, an output data cache module, a DMA scheduling module, a DDR output module and a DDR interface module; is used for caching multi-channel high-speed data of multiple data sources in a memory, does not occupy on-chip RAM resources of the FPGA, realizes parallel, independent and efficient storage and storage of multi-channel data, a data interaction interface is a standard FIFO interface, a user does not need to care about complex DDR3 / 4 (Double Data Rate) interface timing and multi-channel data scheduling, programming is realized by using a hardware description language, parameterization configuration is adopted, other FPGA platforms are compatible, the application can be called in FPGA design as an IP, a development cycle is shortened, and development efficiency is improved.

The invention discloses a crystal oscillator electric aging test implementation method based on FPGA (Field Programmable Gate Array) design, which belongs to the technical field of crystal oscillator electric aging tests and comprises the following steps of: inserting an electric aging test board on which an electric aging product is mounted on a metal aging rack in a high-temperature oven; the electric aging product information is recorded in the electric aging program; after the electric aging test main control program receives an instruction that the electric aging program starts to test, frequency signal inspection of all electric aging products on the electric aging test board is rapidly completed; the inspection result is transmitted to the electric burn-in program, and the electric burn-in test main control program stores the inspection result at the same time; and after three days of frequency signal inspection, checking the electric aging current situation of the electric aging product in the electric aging program. According to the electric aging test implementation method, the electric aging test main control program is embedded in the FPGA unit, and the frequency signals of all the electric aging products on the same electric aging test board can be synchronized by using the strong parallel processing capability of the FPGA.

The application relates to an FPGA design code credible generation and verification method and system based on a large language model, wherein the system comprises: a user interaction layer used for receiving input information of a user and converting the input information into standardized requirement information; an understanding and generation layer used for performing semantic analysis on the requirement information and generating a preliminary design result, the preliminary design result comprising an RTL code and a test framework; a verification analysis layer used for performing multi-stage engineering verification on the generated RTL code; a structured representation layer used for constructing a unified design intermediate representation in a system to make each stage take the same structural semantics as a benchmark; and a core control layer used for scheduling the running processes of the user interaction layer, the understanding and generation layer, the verification analysis layer and the structured representation layer. The application can improve design efficiency, reliability and engineering controllability.

The application provides a multifunctional test chip and method based on a PXI architecture, and relates to the technical field of test chips; the chip comprises a bus interface, a functional module group and an address controller; the bus interface interacts with an upper computer through a PXI bus; the functional module group comprises pulse sending, detection, analog quantity acquisition / output, serial communication, a storage controller and a temperature acquisition module, and can realize pulse signal transceiving, analog quantity processing, serial communication, data storage and temperature acquisition; the address controller divides an address space into eight subspaces, and precise control is realized. The control method comprises the steps of initializing an interface circuit, executing pulse sending and detection, analog quantity output and acquisition, EEPROM operation, UART communication and temperature acquisition and the like. The application integrates special modules, replaces traditional FPGA design, improves performance and reliability, reduces resource waste, reduces cost, shortens the development cycle, and is suitable for complex test scenes such as spaceflight measurement and control.

This application relates to the field of integrated circuits and discloses a method for evaluating the routing success rate of interconnect switch blocks (RSBs) in the placement and routing process of a field-programmable gate array (FPGA). This method analyzes the driver and drain nodes of the RSBs, and, combined with the placement results, counts the drain nodes that need to be connected, finds feasible routing paths, and calculates the routing success rate of the RSBs. This application also discloses a placement optimization method based on this evaluation result. By calculating the routing success rate of each RSB, the area containing RSBs below a threshold is re-placed until the routing success rate meets the requirements. This application can accurately quantify and evaluate the resource usage and routing success rate of RSBs. By evaluating the routing success rate on an RSB-by-RSB basis before routing to guide placement adjustments, it reduces the difficulty of internal routing within RSBs, reduces congestion, accelerates routing convergence, and improves FPGA design efficiency and reliability.

A system and method for hardware-accelerated determination of hybrid codebook performance using FPGA implementation. The system transforms the mathematical operations of estimating combined performance of primary and secondary codebooks into dedicated hardware circuits on field-programmable gate arrays. By implementing specialized components for primary term calculation, secondary term calculation, and mismatch probability estimation directly in hardware, the system enables wire-speed performance estimation without generating test codebooks. The FPGA design comprises parallel processing paths, dedicated bit manipulation circuits for logarithmic approximation, and specialized memory structures for occurrence tracking. This hardware implementation enables real-time hybrid codebook optimization in high-throughput environments such as network appliances, storage controllers, and data processing systems, while providing a development pathway toward eventual ASIC implementation for mass-market deployment.

Currently, complex FPGA designs typically contain multiple sub-modules below the top-level module. These modules ensure correct functional implementation, but because they are integral parts of the design, they are also subjected to gate-level behavioral simulation during simulation. If a module under test has one top-level module and nine sub-modules, seven of which are library or mature modules, and only two are newly designed modules, then only 30% of the gate-level behavioral simulation computation performed by EDA tools is truly for the part we want to verify. However, due to the existence of the top-level code and the need to verify the interface relationships between modules, the verification of sub-modules cannot replace the verification of the top-level module. If we could allow gate-level behavioral simulation to skip library and mature modules, it would significantly reduce the computational load of gate-level behavioral simulation and improve the speed of FPGA code functional simulation. This invention, for functional verification of FPGA code containing multiple sub-modules, uses a C model to replace the library IP modules or mature modules, preventing these modules from participating in the gate-level behavioral simulation during functional simulation execution, thereby significantly shortening the functional simulation execution time and accelerating the functional verification speed of FPGA code.

The application provides a self-adaptive low-energy particle detection system, comprising a low-energy ion analyzer and a low-energy electron analyzer, and both analyzers adopt a same FPGA control program; in the FPGA design, component grouping measurement is added, which is used for realizing multi-component detection in a unit measurement time; in the interface, an instrument number interface is added, which is used for reading the instrument number interface level; a number identification and control module is added, which is used for identifying a current instrument type, generating an instrument identification parameter, realizing collection of different path engineering parameters when the instrument type is the low-energy ion analyzer or the low-energy electron analyzer, controlling reception of an instruction of a device where a current FPGA configuration item is located, and further used for controlling output of a data packet of the device where the current FPGA configuration item is located. The system of the application burns and writes a same FPGA executable code on the low-energy ion analyzer and the low-energy electron analyzer, two different devices, and realizes FPGA configuration item self-adaptation.

This application provides a low-energy particle analysis system with autonomous numbering and identification capabilities, including a low-energy ion analyzer and a low-energy electron analyzer, both of which utilize the same FPGA control program. The FPGA design incorporates component grouping measurement to achieve multi-component detection within a unit measurement time. An instrument number interface is added to the interface for reading the instrument number interface level. A numbering identification and control module is added to identify the current instrument type and generate instrument identification parameters. This module is used to acquire different numbers of engineering parameters when the instrument type is either a low-energy ion analyzer or a low-energy electron analyzer. It also controls the reception of commands from the device corresponding to the current FPGA configuration and controls the output of data packets corresponding to the current FPGA configuration. This system programs the same FPGA executable code onto both the low-energy ion analyzer and the low-energy electron analyzer, achieving FPGA configuration adaptiveness.

The invention provides a method and device for constructing an NTT accelerator based on an FPGA. The construction method comprises the steps that user input is received, the user input comprises a target algorithm selected from multiple NTT algorithms and the available resource quantity of the FPGA, and the multiple NTT algorithms comprise standard NTT, four-step NTT and ten-step NTT; determining a target architecture template corresponding to the target algorithm from a plurality of hardware architecture templates preset for the plurality of NTT algorithms; each hardware architecture template is obtained by combining multiple types of preset operator units, and at least comprises a basic NTT unit configured according to the parallelism degree of the input data. Next, executing a plurality of rounds of iteration aiming at the degree of parallelism, wherein any round of iteration comprises the following steps of: calculating the resource quantity required by the target architecture template under the current value of the degree of parallelism; under the condition that the required resource quantity does not accord with the available resource quantity, reducing a parallelism degree value; and otherwise, determining the current value of the parallelism degree as the target value. Therefore, according to the target value of the parallelism degree, a hardware architecture code used for FPGA design is generated according to the target architecture template.

The invention discloses an automatic integrated debugging method for an FPGA design and simulation platform. The method comprises the following steps: automatically obtaining an HDL source code and a path thereof from an FPGA design project file to be tested; creating or updating a top file of the simulation platform and automatically obtaining a code path of the simulation platform; automatically integrating the to-be-tested HDL source code and the simulation platform; and step 4, automatically matching warning and error reporting with a solution thought database to give a solution. According to the invention, the difficulty of simulation environment debugging can be effectively reduced, and the efficiency of simulation verification can be improved.

The invention provides a DO-254 standard automatic inspection method, system and device for FPGA design for airworthiness certification and a storage medium. Comprising the following steps: configuring an inspection rule and a design index threshold according to a DO-254 standard; generating a TCL script for driving the FPGA design tool based on the rule; calling and executing the TCL script through a Python environment, and generating a time sequence, a utilization rate and a DRC report; a Python script is used for analyzing the report, and key design indexes of the worst negative time sequence margin, the resource utilization rate and the DRC error number are extracted; and comparing the index with a threshold value, and automatically generating a DO-254 standard conformity judgment report. Through cooperation of the TCL and the Python, full-process automation of DO-254 conformity check of FPGA design is realized, the problems of low manual check efficiency and poor consistency are solved, and the efficiency and reliability of airworthiness certification are remarkably improved.

The application discloses a kind of FPGA daisy chain communication structure and communication system, it is related to communication technical field, it solves the problem that interface and protocol are not standardized, development and debugging are difficult in the prior art FPGA inside star topology structure is connected each sub-function module, its technical scheme main point is: it is proposed that communication structure adopts UART interface as the physical interface between host computer and FPGA, each sub-function module in FPGA is connected in the mode of daisy chain;The communication structure used in the application can communicate directly between host computer and each sub-function module through standardized interface and protocol, each sub-function module can be independently developed, debuged, and is suitable for FPGA design in the field of electronic product testing.

An FPGA design method for real-time simulation of power electronic systems includes: in an offline environment, building a power electronic system simulation example, including m power electronic devices, reading electrical component parameters, and forming electrical system dynamic equations; in an offline environment, calculating an augmented state matrix, a constant state transfer matrix, a variable parameter matrix, and an output parameter matrix of the augmented state matrix, and storing them in an FPGA real-time simulator; setting an initial startup of the FPGA real-time simulator; judging the switch state of the power electronic device; at the same time, the FPGA real-time simulator performs control system simulation calculations to obtain power electronic switch control signals; judging whether the simulation time reaches the set simulation end time, and if so, terminating the simulation. The present invention solves the problem of time-varying system topology caused by power electronic devices and provides a new implementation method for real-time simulation of power electronic systems.

The invention discloses a macro cell legalization method, system and device for an FPGA chip and a medium, and the method comprises the steps: carrying out the global layout of an FPGA design netlist, and determining the initial positions of a macro cell and other design units in a global layout coordinate system; acquiring coordinate positions of other design units directly connected with each macro unit in the global layout coordinate system; respectively sequencing the coordinate positions of all other design units connected with each macro unit along the X-axis direction and the Y-axis direction to obtain an X coordinate sequence and a Y coordinate sequence; determining an anchor point corresponding to the macro cell based on the X coordinate sequence and the Y coordinate sequence; minimizing the distance between the candidate placement position of each macro cell and the corresponding anchor point to determine the legal placement position of each macro cell on the FPGA chip; according to the method and the device, the limitation of determining the anchor point of the macro cell in the global layout can be avoided, the deviation between the position of the macro cell and the anchor point after legalization is reduced, and the layout time sequence performance of the FPGA chip is optimized.

The application discloses a memory conversion method, comprising the following steps: obtaining an initial netlist; traversing the initial netlist to determine a plurality of first memories and a plurality of second memories capable of being mapped as BSRAM; obtaining the number of read-write ports and address size of each first memory and each second memory; mapping each first memory as BSRAM of corresponding types and quantities according to the number of read-write ports, data width and address width of each first memory, or mapping each second memory as BSRAM of corresponding types and quantities according to the number of read-write ports, data width and address width of each second memory. The application further discloses a system, a computer device and a readable storage medium. The scheme provided by the application can be applied in chip design or FPGA design, when the design contains a logically represented memory, the memory can be replaced by 1 or several BSRAMs, and the chip area occupied by the memory can be effectively reduced.

A system and method for hardware-accelerated real-time tracking of codebook compression performance using FPGA implementation. The system transforms the sliding window tracking algorithm into dedicated hardware circuits that continuously monitor compression performance as data streams through the system. By implementing parallel occurrence counters, dedicated bit manipulation circuits, and specialized memory structures on field-programmable gate arrays, the system enables wire-speed performance estimation without codebook generation. The FPGA design comprises a pipelined architecture that incrementally updates statistics with each incoming sourceblock, enabling instantaneous performance tracking with zero computational latency. This hardware implementation processes data at rates orders of magnitude faster than software solutions, making it ideal for high-throughput applications in data centers, network infrastructure, and storage systems where real-time compression optimization provides significant benefits for bandwidth utilization and storage efficiency.

The invention discloses a field programmable gate array (FPGA) daisy chain communication structure and a communication system, relates to the technical field of communication, and solves the problems that interfaces and protocols are not standardized and are difficult to develop and debug due to the fact that sub-function modules are connected by adopting a star topology structure in an existing FPGA. The key points of the technical scheme are as follows: a UART (Universal Asynchronous Receiver / Transmitter) interface is adopted as a physical interface between an upper computer and an FPGA (Field Programmable Gate Array) in a communication structure, and sub-function modules in the FPGA are connected in a daisy chain mode; according to the communication structure adopted by the invention, the upper computer can directly communicate with each sub-function module through a standardized interface and a protocol, each sub-function module can be independently developed and debugged, and the communication structure is suitable for FPGA design in the field of electronic product testing.

A system and method for routing Field Programmable Gate Arrays (FPGAs) includes an input device for acquiring a netlist with defined source, sink, and intermediate nodes, and processing circuitry that features a design router. The router leverages a negotiated-congestion routing component, which promotes the shared use and negotiation for intermediate nodes. The negotiation process employs a congestion cost based on several factors, including base, historical, and present usage costs, alongside node capacity. This system is characterized by a historical cost function focused on the base cost of nodes, favoring the use of those with costs below a specified threshold. A display device incorporated within the system allows for the continuous monitoring of the routing procedure and the efficiency of resource usage. The technology aims to streamline FPGA design by optimizing signal routing for performance and area efficiency.

The application discloses a FPGA design method based on partition debugging kernel voltage, and relates to the technical field of FPGA.The method downloads the code stream corresponding to the chip hardware design including the internal circuit of the chip and a plurality of power supply regions to the FPGA chip, each power supply region is used for providing the acquired kernel voltage to the corresponding local power consumption region, when the chip cannot normally work in the state that the kernel voltage of the basic voltage value is acquired in all power supply regions, the kernel voltage acquired by at least one power supply region is adjusted through the power supply pin of the chip until the chip normally works, or until the local power consumption region with the fault is determined.The method can make the chip work normally or can be positioned to the fault region by adjusting the kernel voltage of the plurality of power supply regions, and the partition debugging method has high flexibility, is easier to debug, makes the chip work normally, or can be more accurately positioned to the fault region.

The invention discloses an FPGA routing congestion prediction method based on a heterogeneous graph neural network, and the method comprises the steps: obtaining a netlist file in an FPGA design process, extracting the topological information of the file, and constructing a netlist subgraph; fPGA architecture information is obtained, and an architecture subgraph is constructed according to the architecture information; obtaining a layout file in the FPGA design process, extracting position information of each block in the file to construct a spatial mapping edge, and projecting nodes in the netlist sub-graph to the architecture sub-graph through the spatial mapping edge to obtain an integrated heterogeneous graph; constructing a heterogeneous graph neural network matched with the heterogeneous graph, wherein the heterogeneous graph neural network comprises a feature initialization module, a message passing module and a reading module; a data set is constructed according to the heterogeneous graph to train a heterogeneous graph neural network, and a neural network structure search strategy is used to optimize a message passing module; and inputting the heterogeneous graph into the heterogeneous graph neural network to obtain routing congestion information. According to the method, the accuracy of the FPGA routing congestion prediction result can be improved, the generalization ability is higher, and the time for reasoning, training and data preprocessing is shortened.

The application discloses a high-speed parallelization FPGA design architecture based on OpenCL, and in view of the characteristics of large data volume and high real-time requirement in the field of radar signal processing, a complete CPU+FPGA heterogeneous acceleration scheme supporting multiple parallel optimization modes is provided.The scheme is optimized for common parallel optimization modes such as pipeline parallelism, multi-channel parallel optimization and loop iteration, and three memory access mechanisms, global memory, local memory and direct transmission between kernels, are provided to improve the data transmission efficiency in the parallelization calculation process.The architecture proposed in the application realizes related radar algorithms including two-dimensional FFT calculation and special point calculation, and compared with the efficiency before optimization, analysis results are given, which prove that the proposed architecture can meet the data transmission requirements of most parallel processing.

This invention discloses a method and apparatus for detecting self-oscillation signals in FPGAs based on signal feedback loops. The method includes: first, reading the received FPGA hardware description language code file and integrating the various modules in the FPGA code to form a top-down overall code file; second, mapping the overall FPGA code file into a signal transmission network based on the transmission relationships between various signals in the overall code file; third, finding all signal feedback loops in the signal transmission network and calculating the signal feedback probability, selecting and recording signal feedback loops with a signal feedback probability greater than a set threshold, and extracting the signals in the signal feedback loops as self-oscillation signals for output. This invention can effectively detect self-oscillation signals and their occurrence probabilities in FPGA designs. It is simple to use, requires minimal investment, and can well meet the needs of self-oscillation signal detection when conducting triple-modular redundancy designs.

The application provides a target detection method and system based on FPGA, comprising: designing a target detection model according to FPGA hardware resources, wherein the target detection model comprises a hardware accelerator based on GPU and a YOLOv5 model; performing clock domain optimization configuration on an IP core of the GPU; adapting and training the YOLOv5 model based on the GPU after optimization configuration; and performing fast target detection on input images by using the target detection model based on single instruction multiple data stream technology. In this way, the synchronization and coordination between various components of the FPGA are ensured, the inference speed and the overall performance of the system are significantly improved while maintaining the algorithm accuracy, the data throughput of the target detection model is significantly improved, the target detection scheme has the advantages of high flexibility and low cost due to the characteristics of FPGA design, and therefore high-precision, high-flexibility and low-cost target detection on the basis of FPGA is realized, and the problem of poor flexibility and high cost of the hardware acceleration scheme in the existing target detection task is solved.

Systems or methods of the present disclosure may provide a design tool for adjusting designs implemented on programmable logic devices. The present disclosure includes receiving a request to generate or modify code. The present disclosure also includes automatically invoking an agent in response to the request and processing a draft code. Furthermore, the present disclosure includes returning results based on the draft code.

The invention relates to the technical field of SoC testing, in particular to a large SoC testing method and device based on cascade connection of multiple FPGA chips. The method comprises the following steps: evaluating the resource occupancy rate of each module on the SoC; according to the resource occupancy rate of each module, respectively mapping each module to a plurality of FPGA chips; the two adjacent FPGA chips are sequentially connected in series, so that data communication of the two adjacent FPGA chips is carried out, and cascading of all the FPGA chips is achieved; respectively carrying out integration and implementation processing on each FPGA design to generate a bit stream file, and burning the bit stream file to each FPGA chip; and after all the FPGA chips are reset according to the correct time sequence, all the FPGA chips are used as a whole to carry out SoC function testing. According to the invention, the problem of resource limitation of a single FPGA chip can be solved, and a plurality of cascaded FPGA chips are utilized to realize the function test of a complete large SoC system.