571 results about "Logic block" patented technology

The invention relates to the technical field of data compression, and particularly discloses a method for realizing data compression in an RAID card and an RAID control chip, and the method comprises the following steps: S1, receiving a plurality of IO writing commands issued by a host, and obtaining the logic block address and length of each IO; s2, executing a merging operation on the plurality of IOs to generate a merged IO block; s3, performing a data compression operation on the merged IO block through a data compression engine to obtain compressed data; s4, establishing a mapping relation from a logic block address to a physical block address of the compressed data, and storing the mapping relation in a logic-to-physical mapping table; s5, the compressed data are written into a solid state disk through an RAID engine, and meanwhile, logic-to-physical mapping table metadata are stored persistently; s6, sending a recovery command or a zero-writing command to the solid state disk recovery space for the address space which is not used after compression; the problem that an existing SSD compression scheme is high in power consumption is solved, reliability is better, original user data content is closer, and the obtained compression effect is better.

A method for use in a storage processor, comprising: receiving an I / O request that is associated with a logical block address; allocating a cache slot that corresponds to the logical block address, wherein allocating the cache slot includes: identifying a type of memory that is required to host the cache slot by using one or more configuration settings that are associated with the cache slot, identifying a cache slot that is both available and hosted in the identified type of memory, and assigning the identified cache slot to the logical block address; and executing the I / O request by using the allocated cache slot, wherein using the allocated cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command that is associated with the allocated cache slot.

Techniques for interfacing electronics are disclosed. A system-on-chip is accessed. The system-on-chip includes a network-on-chip (NoC) topology. The NoC sub-topologies are based on a physical location of the plurality of logic blocks. A first sub-topology is coupled to a receiving block, wherein the coupling includes inserting an interfacing block. The interfacing block includes a digital PLL (DPLL). The first sub-topology sends to the interfacing block data and a first clock. The first clock is input to the DPLL and used as a reference clock. The DPLL generates a second clock that is used to save the data that was sent. The interfacing block forwards to the receiving block the second clock and the data that was saved. The second clock is used as the internal clock in the receiving sub-topology. The NoC communications includes packets. Additional interfacing blocks are instantiated as necessary.

Methods, systems, and devices for low latency logical (L3A) unit for a memory system are described. For example, a logical unit, such as an L3Alogical unit or L3A logical unit number (LUN), may include a storage area for storing information for system swap operations, including, for example, a logical-block-address (LBA) range for one or more single-level-cells (SLCs). The logical unit may include a logical-to-physical (L2P) mapping table stored in a local memory of a memory system controller, such as in static random access memory (SRAM). In some examples, a reserved storage area may be overprovisioned, and the logical unit may be associated with a higher priority and a larger granularity than one or more other logical units. Further, one or more read-only (RO) descriptors stored to one or more registers, one or more provisioning parameters, or both, may be defined for the logical unit.

The present application discloses methods of operating a memory system, memory systems, hosts, and memory controllers. An example method includes receiving a read command, the read command including a first logical block address (LBA); based on a first attribute identifier corresponding to a first mapping table block in a compressed mapping table, determining a first physical address corresponding to the first LBA in the first mapping table block, the compressed mapping table including a plurality of attribute identifiers, the plurality of attribute identifiers corresponding to different mapping table blocks in a logical-to-physical (L2P) mapping table, an attribute identifier indicating whether physical addresses in a corresponding mapping table block are continuous, and the first mapping table block being the mapping table block in which the first LBA is located; and performing a read operation on a memory device based on the first physical address.

The invention discloses a server and a hard disk medium error processing method, and relates to the technical field of servers, the server comprises a controller and a redundant array of independent disks connected with the controller, the redundant array of independent disks comprises a plurality of hard disks, and different data in the same strip is stored in the same sector of each hard disk. If the controller detects that the at least two hard disks have medium errors in the same target sector, the controller obtains a target logic block address corresponding to the target sector in the at least two hard disks, and for any one of the at least two hard disks, a new sector is redistributed for the target logic block address corresponding to the hard disk in a standby sector preset by the hard disk, and reconstructing the new sectors allocated to the at least two hard disks so as to enable the redundant array of independent disks to work normally. According to the method and the device, the waste of storage resources in the redundant array of independent disks caused by direct replacement of a new redundant array of independent disks is reduced, and the user experience is improved.

A mechanism is provided efficient packing of network flits in a data processing network. Transaction messages for transmission across a communication link of a data processing network are analyzed to determine a group of transaction messages to be passed to a packing logic block for increased packing efficiency. The transaction messages are packed into slots of one or more network flits and transmitted across a communication link. The mechanism reduces the number of unused slots in a transmitted network.

The invention relates to the technical field of safety control of fire exit doors, in particular to an emergency unlocking device and system of an intelligent fireproof door. The analysis subsystem outputs a fire alarm confidence coefficient value and an operation intention intensity value; the arbitration subsystem sends a blocking signal to the automatic locking control system and activates a to-be-decoupled state of the execution subsystem when the intensity of the operation intention exceeds a threshold value; the execution subsystem synchronously adjusts a mechanical transmission stroke parameter and an electromagnetic latching current parameter according to the intensity value of the operation intention; the fault-tolerant subsystem switches the mechanical locking mechanism to a geometric dead point position to release automatic control connection; and the traceability subsystem records the operation data and maintains storage when the power supply is interrupted. According to the invention, a closed-loop control chain from signal sensing to physical decoupling is formed, the problem of authority conflict of automatic locking logic blocking manual operation is solved, and the timeliness and reliability of emergency unlocking are improved.

The invention relates to an SSD (Solid State Disk) heat dissipation optimization method and system based on dynamic temperature control. The method comprises the following steps: acquiring a thermal state vector of an SSD through inner and outer ring temperature monitoring; predicting a future 5S temperature track through a long short-term memory network model, and generating a temperature prediction sequence; generating a computing power distribution proportion based on the temperature prediction sequence, and determining a capacity migration proportion at the same time; according to the real-time temperature value of each logic block in the block temperature mapping table and the computing power distribution proportion and capacity migration proportion, heat-sensitive and heat-tolerant classification is carried out on the I / O queue, and an optimized scheduling sequence is generated; calculating a power supply phase parameter according to the access frequency of the heat-sensitive block of the optimized scheduling sequence, and generating a pulse type heat dissipation control signal; the SSD power supply phase is dynamically adjusted according to the pulse type heat dissipation control signal, heat dissipation optimization is conducted through the pulse width modulation technology, updated heat state data is fed back to inner and outer ring temperature monitoring, and therefore the purpose of dynamic intelligent temperature control of the SSD is achieved.

The invention discloses a command execution method and device, equipment and a medium, and relates to the field of command processing, and the method comprises the steps: determining whether to update a current aggregation command based on an original read-write command or not by judging whether the original read-write command currently issued by a host meets a preset aggregation condition or not; wherein the preset aggregation condition comprises that the original read-write command and the current aggregation command correspond to the same target disk array card and have the same identification information; and if the original read-write command does not meet a preset aggregation condition or the updated current aggregation command meets a preset end condition, determining the number of logic blocks required by a full stripe based on the target disk array card, and splitting the current aggregation command so as to execute corresponding read-write operation on the target disk array card based on the split command. According to the method, the aggregation command is subjected to full stripe splitting, and the read-write operation is executed on the disk array card based on the split command, so that the read-write frequency of the disk in the disk array card can be reduced, and the read-write performance of the disk is improved.

A network interface controller (NIC) capable of facilitating efficient data request management is provided. The NIC can be equipped with a command queue, a message chopping unit (MCU), and a traffic management logic block. During operation, the command queue can store a command issued via a host interface. The MCU can then determine a type of the command and a length of a response of the command. If the command is a data request, the traffic management logic block can determine whether the length of the response is within a threshold. If the length exceeds the threshold, the traffic management logic block can pace the command such that the response is within the threshold.

Provided is a method for writing data to a Solid State Disk (SSD), an apparatus and the SSD. According to the method, a Logical Block Address (LBA) of each of a plurality of pieces of written data stored into a target cache module is acquired to obtain a plurality of Logical Block Addresses (LBAs); the plurality of pieces of written data in the buffer is stored into a solid-state storage unit of the SSD; whether the plurality of LBAs are consecutive is determined to obtain a determination result. In a case where the determination result indicates that the plurality of LBAs are consecutive, a Physics Block Address (PBA) of each of the plurality of pieces of written data in the solid-state storage unit is acquired to obtain a plurality of PBAs and a target mapping table according to the plurality of LBAs and the plurality of PBAs is generated.

This specification provides text generation methods, apparatuses, and storage medium devices. One method includes the following operations. In an iteration of a plurality of iterations under a large language model (LLM): estimating a first text sequence following a current text sequence based on a speculative decoding method, forming a plurality of candidate sequences based on the current text sequence and subsequences of the first text sequence, allocating logical blocks to text units in the plurality of candidate sequences in a key-value cache, to store attention information of the text units, mapping the allocated logical blocks to physical blocks based on a first criterion, and determining, by the LLM, a newly generated text unit in the iteration by using attention information of each candidate sequence in the key-value cache, to form a current text sequence for a next iteration of the plurality of iterations.

Ultrasound image devices, systems, and methods are provided. An intraluminal ultrasound imaging system, comprising a patient interface module (PIM) in communication with an intraluminal imaging device comprising an ultrasound imaging component, the PIM comprising a first reconfigurable logic block including a first plurality of logic elements interconnected by first reconfigurable interconnection elements; a configuration memory coupled to the first reconfigurable logic block; and a processing component coupled to the configuration memory, the processing component configured to detect a device attribute of the intraluminal imaging device in communication with the PIM; and load at least one of a first configuration or a second configuration to the configuration memory based on the detected device attribute to configure one or more of the first reconfigurable interconnection elements such that the first plurality of logic elements are interconnected for communication with the ultrasound imaging component.

A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes a dual-mode port (“DMP”), configurable logic blocks (“LBs”), routing connections, and a configuration memory for providing configuration data to facilitate user-defined logic functions. The DMP, in one aspect, is operable to handle the configuration data during a configuration mode. Alternatively, the DMP is operable to handle the user data during a logic operation mode. In one aspect, the user configuration data contains the address of the second memory containing DCD.

Embodiments of the present invention provide a data processing method, a device, and a storage medium. The method comprises: acquiring first access log information of a block device in a first time period, wherein the block device corresponds to a plurality of logical block addresses; determining a target grouping length on the basis of the first access log information so as to group the plurality of logical block addresses on the basis of the target grouping length to obtain a plurality of groups, wherein the logical block addresses in a same group have similar access behaviors; determining access feature values respectively corresponding to the plurality of groups; and on the basis of the access feature values respectively corresponding to the plurality of groups, determining cold and hot data categories respectively corresponding to the plurality of groups.

The invention provides an automatic rendering method and system of a building block model, a medium and a product, and aims to solve the problems of low efficiency and high resource occupation in large-scale building block model rendering. The method comprises the following steps: dividing a model into logic blocks; generating a virtual camera array and a virtual light source matrix based on the blocks; performing multi-resolution rendering on each block according to the priority determined by the view angle area; and finally splicing a rendering result. According to the method, through blocking processing and differentiated multi-resolution rendering, the consumption of computing resources is effectively reduced, the rendering efficiency is remarkably improved, and meanwhile, the rendering image quality of the complex building block model is ensured.

A data access method, apparatus and device, in the application, a physical space of a storage device is mapped into a logic space, the logic space comprises a plurality of logic blocks, and the physical space comprises a plurality of physical blocks. The storage device obtains a data reading instruction, wherein the data reading instruction is used for requesting to read the first data; the storage device determines a target index entry according to the logical address of the first data, the target index entry indicates a mapping relationship between a first logical block and a first physical block, and the first logical block is a logical block to which the logical address belongs. The storage device determines the physical address of the compressed first data according to the first physical block and a first target data volume, wherein the first target data volume is the data volume of the compressed first data; the storage device obtains the compressed first data according to the physical address; and decompressing the compressed first data, and obtaining and feeding back the first data. The construction granularity of the index entry is a physical block and a logic block, and the data volume of the compressed data does not need to be recorded, so that the complexity of data indexing is effectively reduced.

Methods, systems, and devices for zoned random write operations are described. A memory system may receive a set of write commands associated with respective logical block addresses (LBAs) that may be in a sequential order, where the respective LBAs may be associated with a zone. The memory system may write first data to a first physical block address (PBA), where the first data may be associated with a first LBA of the respective LBAs. The memory system may determine whether a second LBA associated with second data is sequential relative to a write pointer associated with the zone. The memory system may write the second data to a second PBA that may be sequential to the first PBA in response to determining that the second logical block address is non-sequential relative to the write pointer and on a value of a bitmap corresponding to the second LBA.

The invention discloses a mapping table storage method and device, computer equipment and a storage medium, and relates to the technical field of data storage, and the method comprises the following steps: determining a target logic block group corresponding to a target mapping entry and a preset attribute of the target logic block group; and if the preset attribute is a first preset value, writing the target mapping entry into a first preset cache space, screening the target mapping entry and other mapping entries according to the writing sequence of the target mapping entry and the writing sequence of other mapping entries, and storing the screened mapping entries into a flash memory. The problem that in the process of brushing an L2P mapping table to a flash memory, invalid mapping entries are written into the flash memory as well, and consequently bandwidth and storage resources are wasted can be solved. According to the method, the mapping entries are screened, only the screened mapping entries are stored in the flash memory, invalid mapping entries are successfully reduced, and in the process of storing the mapping table in the flash memory, bandwidth occupation is reduced, and the space occupied by the mapping table in the flash memory is reduced.

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

Embodiments of the present disclosure include improved logic blocks with combined outputs for programmable logic devices and methods of operating and programming these logic blocks. In an exemplary aspect, a programmable logic device (PLD) is described. In some embodiments, the PLD includes a logic block. The logic block may include a first look-up table (LUT) circuit configured to generate a first output; a second LUT circuit configured to generate a second output; a ripple logic circuit configured to receive the first output and the second output and generate a third output; and a three-to-one multiplexer circuit configured to receive the first output, the second output, and the third output and selectively produce an output of the logic block.

The invention provides an address mapping method and device, a storage system, a program product and a storage medium, and relates to the technical field of storage. According to the method, a storage system receives an input initial logic block address and a disk array identifier at the same time, and can query the stripe size configured by a disk array corresponding to the disk array identifier, so that a stripe identifier is determined by utilizing the initial logic block address, the disk array identifier and the stripe size at the same time; and determining the stripe where the initial logic block address is located by combining the disk array identifiers and stripe sizes of different disk arrays. And then, the storage system can query stripe physical address information corresponding to the stripe identifier in a preset mapping table, and determine a physical block address corresponding to the initial logic block address according to the stripe physical address information. Therefore, different disk arrays can be arranged in the storage system, and the different disk arrays can correspond to scenes with different stripe sizes, so that the conversion efficiency of the initial logic block address is improved, and the data operation efficiency is improved.

The invention relates to the technical field of intelligent chips, in particular to an NAND wear leveling method based on integrated circuit ECC (error correction code) and read delay, which comprises the following steps: acquiring read delay data and error correction code usage amount of a three-layer unit page of a target block in an NAND flash memory chip; on the basis of the read delay increment and the error correction code increment of the middle-layer page, the health index of the target block is calculated by combining the read delay difference value of the middle-layer page and the lower-layer page, the target block is divided into a plurality of health levels, and logic blocks of different health levels are mapped to different physical planes of the NAND flash memory chip; synchronously executing data migration and erasure operations of the plurality of blocks to be migrated by utilizing the parallel erasure capability of the multi-plane architecture for the target block of which the health level is degraded to a preset threshold value; and monitoring the deviation degree between the current read delay and the specification read delay in real time, and selecting the error correction strength grade of the error correction code according to the deviation degree.

A system for autonomous compliance with legal regulations in smart contracts; the system includes: a regulatory data collection unit comprising a network interface controller physically connected to an external communications port, a hardware-based public key infrastructure circuit configured to validate digital certificates of regulatory servers, and a direct memory access controller configured to transfer authenticated regulatory update packets from the network interface controller to a volatile buffer memory without processor intervention; a Compliance Code Conversion Unit with a hardware lexicon scanner implemented as a finite state machine and embedded in reconfigurable FPGA logic blocks, a microcontroller executing a hardware-based lexical analysis pipeline stored in firmware registers, and a translation cache memory configured to temporarily store tokenized compliance rules before writing them to a non-volatile instruction memory; a policy evaluation and enforcement unit comprising a transaction verification processor connected to a secure enclave memory, a hardware comparator circuit configured to compare transaction parameters with compliance thresholds stored in the secure enclave memory, and a logic gate circuit configured to generate execution gate signals that selectively allow, block, or modify smart contract execution signals transmitted to a blockchain execution processor; and an audit logging unit with a cryptographic hashing circuit configured to generate block hashes of enforcement records, a timestamp oscillator configured to generate temporal signatures of compliance enforcement actions, and a Merkle tree generation circuit configured to create tamper-proof hierarchical hash structures, with the enforcement records being passed to a decentralized storage interface for anchoring in the chain or distributed ledger.

Aspects of a storage device are provided for efficient handling of logical metablock formation based on a heat distribution within the storage device. The storage device includes a plurality of memory dies each including a physical block, and a controller which forms a logical metablock from the physical blocks based on a location of each of the memory dies with respect to the controller. The controller stores a mapping of heat credit points to each of the physical blocks, where each of the heat credit points are associated with a respective heat level. The controller forms logical metablocks from the physical blocks based on the mapping. For instance, the controller forms different logical metablocks from physical blocks based on respective heat levels associated with memory dies including those blocks. As a result, efficient logical block formation may be achieved without significant complexity in firmware implementation.

A storage device provides thin provisioning by presenting more logical capacity than available physical capacity. The storage device uses a dynamic random-access memory (DRAM) having a size that is proportional to the available physical capacity of the storage device. The storage device includes a memory device with a physical capacity and the DRAM. A controller on the storage device creates segments including logical block address (LBA) sets in an LBA space. The LBA sets include an LBA from each segment that are linked to enable the LBAs in a LBA set to share a mapping space in the DRAM. The controller also creates an L2P table including a LBA set entry per LBA set, with each LBA set entry including sub-entries to store physical locations on the memory device that are associated with the LBAs in the LBA set. The controller also stores the L2P table in the DRAM.

A method for data transmission is provided. The method includes, at an initiator computing device, receiving a data payload to be transmitted to a target computing device for storage using the nonvolatile memory express over fabric (NVMe-oF) protocol, wherein the data payload is represented as a plurality of logical blocks. Using a compression engine, the data payload is compressed into a plurality of physical blocks having a smaller total data size than the plurality of logical blocks. A write request is transmitted to the target computing device, the write request including the plurality of physical blocks, and metadata specifying a correspondence between each logical block of the plurality of logical blocks and one or more corresponding physical blocks of the plurality of physical blocks.

Systems and methods for a new field programmable gate array (FPGA) architecture that is optimized for machine learning (ML) applications are provided. Such ML applications can specifically include, for example, artificial neural networks and deep neural networks. Various embodiments enable the design of faster and more power efficient hardware accelerators for machine learning algorithms, compared to existing FPGAs in the market. This is made possible by hard systolic matrix multiplier blocks, hard activation blocks and soft ML-centric configurable logic blocks. The matrix multiplier blocks are connected to field programmable interconnect resources to enable creation of larger matrix multipliers. The hard matrix multipliers and the hard activation blocks have programmable interconnects between them and neighboring memory or compute blocks on the device.

Circuits and methods that enable a “break-before-make” process for an electronic switch that avoids the relatively large time delays of fixed time delay circuitry. Logic gates, rather than a time delay, are used to lock out an input switch through-path from turning ON before another input switch through-path is fully turned OFF. An embodiment includes a first and second monitor logic blocks, configured such that (1) a first through-path is turned OFF before a first shunt-path is allowed to turn ON and before a second shunt-path is allowed to turn OFF, and the second shunt-path is turned OFF before a second through-path is allowed to turn ON; and (2) the second through-path is turned OFF before the second shunt-path is allowed to turn ON and before the first shunt-path is allowed to turn OFF, and the first shunt-path is turned OFF before the first through-path is allowed to turn ON.