1014 results about "Logic block" patented technology

The invention relates to a PDF extraction method and system based on deep learning and layout analysis, and the method comprises the steps: obtaining a PDF file, carrying out the element recognition of a scanning version file and a text version file through an OCR technology and a deep learning model, and enabling the elements to comprise a text, a picture, a table and a formula; dividing a page of the PDF file into a plurality of logic blocks according to the identified elements, and determining a hierarchical relationship and a sequence; deleting elements without substantial help from the identified elements, and extracting the content of the document; performing page layout analysis according to the document content, and reordering and organizing each logic block to obtain a layout; document contents are classified and analyzed, and then classified storage is carried out; and according to user requirements, splicing the classified and stored document contents in a corresponding layout to generate a document in a target format. Compared with the prior art, efficient and accurate PDF extraction is achieved, and meanwhile the important structure and content of an original document are reserved.

Ultrasound imaging devices, systems and methods are provided. An intraluminal ultrasound imaging system includes a patient interface module (PIM) that communicates with an intraluminal imaging device, the intraluminal imaging device including an ultrasound imaging component, the PIM including a first reconfigurable logic block, a configuration memory and a processing component, the first reconfigurable logic block including a first plurality of logic elements interconnected by a first reconfigurable interconnect element, the configuration memory being coupled to the first reconfigurable logic block, the processing component being coupled to the configuration memory, the processing component being configured to: detect device properties of the intraluminal imaging device communicating with the PIM; and load at least one of a first configuration or a second configuration into the configuration memory based on the detected device properties to configure one or more first reconfigurable interconnect elements in the first reconfigurable interconnect element so that the first plurality of logic elements are interconnected to communicate with the ultrasound imaging component.

The invention discloses a data processing method and device based on a large model, a storage medium and electronic equipment. The method relates to the technical field of artificial intelligence, and comprises the following steps: processing description information through a first reasoning model in a first graphics processor corresponding to a pre-filling node to obtain key value information and a first reply character output by the first reasoning model in the first graphics processor, and obtaining a second reply character based on a key value logic block identifier corresponding to the key value information; storing the key value information belonging to the same key value logic block identifier to a target video memory area in the first graphics processor, and processing the key value information and the first reply character in the target video memory area through a second reasoning model in a second graphics processor corresponding to the decoding node, and obtaining target reply information corresponding to the description information. The problem that the data processing efficiency is low is solved.

Disclosed embodiments provide techniques for a networking with a network-on-chip (NoC) interface with subtopologies. A system-on-chip (SoC) is accessed. The SoC includes a plurality of logic blocks. A NoC topology is created. The NoC topology includes one or more subtopologies. The one or more subtopologies are based on a physical location of the plurality of logic blocks. Each subtopology includes at least one router. A location of the one or more subtopologies is optimized. The one or more subtopologies are coupled based on one or more communications protocols. A protocol running on the plurality of logic blocks is translated to the one or more communications protocols. Data is sent from a sending subtopology within the one or more subtopologies to a receiving subtopology within the one or more subtopologies.

The invention discloses a hard disk pre-reading method and device, electronic equipment and a storage medium, and relates to the technical field of storage, and the method comprises the steps: under the condition that a data reading request is captured, analyzing the data reading request to obtain a logic block address corresponding to the data reading request, and according to the logic block address corresponding to the data reading request, obtaining a pre-reading result of the hard disk; according to the method, the access mode corresponding to the data reading request is determined, so that the pre-reading amount is adjusted, the pre-reading amount is dynamically adjusted through the access mode of the data reading request, and the data pre-reading operation is executed by using the adjusted pre-reading amount; according to the method and the device, the problem of low reading efficiency caused by cache pollution due to fixed pre-reading quantity in the related art is solved, and the technical effect of improving the cache efficiency and hit rate is achieved.

A distributed storage management system comprising nodes that form a cluster, a distributed block layer that spans the nodes in the cluster, and file system instances deployed on the nodes. Each file system instance comprises a data management subsystem and a storage management subsystem disaggregated from the data management subsystem. The storage management subsystem comprises a node block store that forms a portion of the distributed block layer and a storage manager that manages a key-value store and virtualized storage supporting the node block store. A file system volume hosted by the data management subsystem maps to a logical block device hosted by the virtualized storage in the storage management subsystem. The key-value store includes, for a data block of the logical block device, a key that comprises a block identifier for the logical block device and a value that comprises the data block.

A method for reducing write latency in a distributed file system. A write request that includes a volume identifier is received at a data management subsystem deployed on a node within a distributed storage system. The data management subsystem maps the volume identifier to a file system volume and maps the file system volume to a set of logical block addresses in a logical block device in a storage management subsystem deployed on the node. The storage management subsystem maps the logical block device to a metadata object for the logical block device on the node that is used to process the write request. The mapping of the file system volume to the set of logical block addresses in the logical block device enables co-locating the metadata object with the file system volume on the node, which reduces the write latency associated with processing the write request.

The invention relates to the technical field of data compression, and particularly discloses a method for realizing data compression in an RAID card and an RAID control chip, and the method comprises the following steps: S1, receiving a plurality of IO writing commands issued by a host, and obtaining the logic block address and length of each IO; s2, executing a merging operation on the plurality of IOs to generate a merged IO block; s3, performing a data compression operation on the merged IO block through a data compression engine to obtain compressed data; s4, establishing a mapping relation from a logic block address to a physical block address of the compressed data, and storing the mapping relation in a logic-to-physical mapping table; s5, the compressed data are written into a solid state disk through an RAID engine, and meanwhile, logic-to-physical mapping table metadata are stored persistently; s6, sending a recovery command or a zero-writing command to the solid state disk recovery space for the address space which is not used after compression; the problem that an existing SSD compression scheme is high in power consumption is solved, reliability is better, original user data content is closer, and the obtained compression effect is better.

The invention discloses an edge end large language model inference system. The system comprises a main computing chip, an LPDDR interconnection resource and a vertically stacked and packaged storage chip stack, the storage chip stack comprises an NAND flash memory chip and a DRAM (Dynamic Random Access Memory) chip, and the NAND flash memory chip and the DRAM chip are paired and share an LPDDR interconnection resource; the NAND flash memory chip comprises a flash memory chip bare chip and a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) chip bare chip which are three-dimensionally interconnected based on hybrid bonding; a flash memory array is arranged on the flash memory chip bare chip; a logic block is arranged on the CMOS chip bare chip; the main calculation chip reads a parameter matrix of a model full connection layer from the NAND flash memory chip and reads other parameters from the DRAM chip for calculation in a pre-filling stage of large language model reasoning; and the NAND flash memory chip performs full connection layer calculation in a decoding stage. The system provided by the invention can improve the external transmission and internal reading bandwidth.

The invention provides a big language model reasoning method and device, electronic equipment and a medium. The method comprises the steps that a reasoning request is received, an input sequence of the reasoning request is divided into one or more logic blocks according to the fixed lexical element number, and the input sequence is a lexical element sequence of cue words of the reasoning request; for each logic block: calculating a digest value of the logic block as a first digest value based on a digest value calculation sequence of the logic block, the digest value calculation sequence being a lexical sequence from a start lexical element of the input sequence to an end lexical element of the logic block; whether a second digest value identical to the first digest value exists or not is judged, the second digest value is a digest value of an inferred logic block with KV cache stored in a physical block, and the physical block is a storage space used for the KV cache; and allocating a physical block to the logic block according to the judgment result, and enabling the large language model to perform reasoning for the reasoning request.

The invention discloses a code reconstruction method and system based on data stream slicing and large language model driving, and belongs to the field of software engineering. The method comprises five parts of code preprocessing, data stream analysis, construction of cue words of a large language model, function testing and code review. According to the method, firstly, codes needing to be reconstructed are preprocessed and converted into a unified format; secondly, performing data stream analysis on the preprocessed codes, and dividing independent logic blocks; generating cue words according to a data flow analysis result and historical behaviors, and inputting the cue words into a large language model to obtain reconstructed codes; and finally, the codes before and after reconstruction are tested, and whether re-reconstruction is needed is detected, so that reconstruction of the long method codes is realized, and the accuracy and efficiency of code function division and method extraction are optimized.

The invention discloses a blockchain-based bidding and tendering data security processing method, which belongs to the technical field of data encryption, and specifically comprises the following steps of: segmenting original data into logic blocks according to a time axis, and generating a dynamic feature code containing a hierarchical relationship by using a current data hash value and a last feature segment of a preorder block through nonlinear fusion; and constructing a three-dimensional verification topology network containing a timestamp longitudinal chain, a content association transverse tree and an environment parameter space matrix. And establishing a dynamic verification channel, activating three-anchor-point association path cross verification when data is called, and generating an integrity proof. A self-destruction mechanism is implanted in verification, and data blocks are subjected to gradient erasure when abnormal conditions occur. And finally, generating a traceability map, dispersing encryption key parameters in multiple domains, and recording a storage domain coordinate hash abstract through a block chain. The method is suitable for high-security electronic bidding and tendering scenes.

A storage node maintains storage objects that contain decoy datasets that are used to detect cyber-attacks. The decoy datasets may be deployed at logical block addresses (LBAs) including the first and last LBAs of the LBA range of the storage object. Real active data may be stored on the storage object with the decoy datasets. A cyber-attack is detected based on receipt of a suspicious IO command that accesses decoy data. Access to the decoy data may be detected by maintaining an IO access bitmap, calculating digital signatures of decoy datasets, or monitoring for decoy data that is marked for remote replication.

In various examples, data storage is managed using a distributed storage management system that is resilient. Data blocks of a logical block device may be distributed across multiple nodes in a cluster. The logical block device may correspond to a file system volume associated with a file system instance deployed on a selected node within a distributed block layer of a distributed file system. Each data block may have a location in the cluster identified by a block identifier associated with each data block. Each data block may be replicated on at least one other node in the cluster. A metadata object corresponding to a logical block device that maps to the file system volume may be replicated on at least another node in the cluster. Each data block and the metadata object may be hosted on virtualized storage that is protected using redundant array independent disks (RAID).

The embodiment of the invention provides a communication method and device based on graphic modeling, the historical protocol features are analyzed through a deep learning model, the protocol template data set is generated, and the intelligence of protocol design is realized. A graphical protocol design interface is innovatively designed, a communication protocol general block and a logic block are integrated, and a compatibility parameter matrix is introduced to realize intelligent connection correction. The system automatically generates a protocol analyzer, and network data streams are processed through a serialization function library and an algorithm function library, so that the accuracy and reliability of data transmission are ensured. According to the method, the limitation of traditional manual coding is broken through, and an efficient and intuitive visual solution is provided for communication protocol development.

Systems and methods for secure booting of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in a PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in a non-volatile memory (NVM) of the secure PLD and / or coupled through a configuration input / output (I / O) of the secure PLD to the configuration engine. The secure PLD is configured to retrieve a pre-authentication status associated with the configuration image from the NVM, determine or verify the retrieved pre-authentication status associated with the configuration image includes a valid status, and boot the PLD fabric of the secure PLD using the configuration image.

A method for use in a storage processor, comprising: receiving an I / O request that is associated with a logical block address; allocating a cache slot that corresponds to the logical block address, wherein allocating the cache slot includes: identifying a type of memory that is required to host the cache slot by using one or more configuration settings that are associated with the cache slot, identifying a cache slot that is both available and hosted in the identified type of memory, and assigning the identified cache slot to the logical block address; and executing the I / O request by using the allocated cache slot, wherein using the allocated cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command that is associated with the allocated cache slot.

The invention provides a data prefetching method and device. The data prefetching method comprises the steps that parameters of a read request for a storage device in a prefetching time window are obtained, and the parameters of the read request comprise features of the read request and logic block address information of the read request; according to the characteristics of the read requests, determining the prefetch number of subsequent read requests for the storage device; according to the logic block address information of the read request, determining the prefetch heap block addresses of the prefetch quantity of the subsequent read request; and pre-fetching the data of the pre-fetching heap block addresses of the storage device according to the pre-fetching number.

A field programmable gate array includes a configurable interconnect structure connecting logic blocks that implement circuitry to: receive input data including data values organized into rows and columns, each row having N data values; selecting R [i] unmasked data values of a row of the input data according to the mask and the index i of the row; selecting N-R [i] unmasked data values of the other line of the input data according to the mask and the index of the other line; merging R [i] unmasked data values of the row and N-R [i] data values of the other row into a combined data vector of N data values; and calculating R [i] normalized values based on the R [i] unmasked data values of the combined data vector and calculating N-R [i] normalized values based on the N-R [i] data values of the combined data vector to generate N normalized data values.

Techniques for interfacing electronics are disclosed. A system-on-chip is accessed. The system-on-chip includes a network-on-chip (NoC) topology. The NoC sub-topologies are based on a physical location of the plurality of logic blocks. A first sub-topology is coupled to a receiving block, wherein the coupling includes inserting an interfacing block. The interfacing block includes a digital PLL (DPLL). The first sub-topology sends to the interfacing block data and a first clock. The first clock is input to the DPLL and used as a reference clock. The DPLL generates a second clock that is used to save the data that was sent. The interfacing block forwards to the receiving block the second clock and the data that was saved. The second clock is used as the internal clock in the receiving sub-topology. The NoC communications includes packets. Additional interfacing blocks are instantiated as necessary.

Disclosed in the present disclosure are a resource allocation method and apparatus, an electronic device, and a storage medium, which relates to the field of computer technology. The method includes: determining one or more unallocated compute express link (CXL) memory logical blocks in a CXL memory resource pool in response to determining that a remaining memory capacity of a first host is less than a remaining memory capacity threshold of the first host; selecting a target CXL memory logical block from among the one or more unallocated CXL memory logical blocks in the CXL memory resource pool; and allocating a memory resource corresponding to the target CXL memory logical block to the first host via a CXL switch. This solves the problem of complex management of the CXL memory resource pool.

Methods, systems, and devices for low latency logical (L3A) unit for a memory system are described. For example, a logical unit, such as an L3Alogical unit or L3A logical unit number (LUN), may include a storage area for storing information for system swap operations, including, for example, a logical-block-address (LBA) range for one or more single-level-cells (SLCs). The logical unit may include a logical-to-physical (L2P) mapping table stored in a local memory of a memory system controller, such as in static random access memory (SRAM). In some examples, a reserved storage area may be overprovisioned, and the logical unit may be associated with a higher priority and a larger granularity than one or more other logical units. Further, one or more read-only (RO) descriptors stored to one or more registers, one or more provisioning parameters, or both, may be defined for the logical unit.

The present application discloses methods of operating a memory system, memory systems, hosts, and memory controllers. An example method includes receiving a read command, the read command including a first logical block address (LBA); based on a first attribute identifier corresponding to a first mapping table block in a compressed mapping table, determining a first physical address corresponding to the first LBA in the first mapping table block, the compressed mapping table including a plurality of attribute identifiers, the plurality of attribute identifiers corresponding to different mapping table blocks in a logical-to-physical (L2P) mapping table, an attribute identifier indicating whether physical addresses in a corresponding mapping table block are continuous, and the first mapping table block being the mapping table block in which the first LBA is located; and performing a read operation on a memory device based on the first physical address.

Parallel instruction demarcators and methods for parallel instruction demarcation are included, wherein an instruction syllable sequence comprising a plurality of instruction syllables is received and stored at an instruction buffer. It is determined, using one or more logic blocks arranged in a sequence, a size of an instruction and at least one boundary at which the instruction is demarcated. Additionally, using a controlling logic block a restart point is determined from where the sequence of instruction syllables is examined and demarcated into individual instructions.

The invention discloses a server and a hard disk medium error processing method, and relates to the technical field of servers, the server comprises a controller and a redundant array of independent disks connected with the controller, the redundant array of independent disks comprises a plurality of hard disks, and different data in the same strip is stored in the same sector of each hard disk. If the controller detects that the at least two hard disks have medium errors in the same target sector, the controller obtains a target logic block address corresponding to the target sector in the at least two hard disks, and for any one of the at least two hard disks, a new sector is redistributed for the target logic block address corresponding to the hard disk in a standby sector preset by the hard disk, and reconstructing the new sectors allocated to the at least two hard disks so as to enable the redundant array of independent disks to work normally. According to the method and the device, the waste of storage resources in the redundant array of independent disks caused by direct replacement of a new redundant array of independent disks is reduced, and the user experience is improved.

A configuration may identify an IC chip component the IC chip component comprising one of a logic block, a memory block, and a power grid. A configuration may train a machine learning model based on one or more features and one or more labels corresponding to the identified IC chip component. A configuration may generate an artificial intelligence model having characteristics comprising the trained machine learning model, the one or more features, and the one or more labels. A configuration may generate a prediction for the one or more labels based on past, present and projected one or more features. A configuration may monitor future label prediction versus a failure threshold. A configuration may generate a notification in response to the failure threshold being reached.

The invention discloses a cache management method and a storage medium thereof. The cache management method comprises the steps that when a target data write-in request is responded, page information of a current target block is obtained, and the page information represents a page, needing to be subjected to data read-write operation, of the current target block; according to page information, corresponding block operation is executed, the page information comprises the last page of the current target block, the first page of the current target block and the middle page of the current target block, the page information comprises block operation logic corresponding to the page information, and the block operation logic is used for indicating execution of the corresponding block operation. According to the cache management method disclosed by the invention, the page information is obtained to perform the corresponding block operation on the current target block, so that the block management of the NAND Flash memory can be dynamically realized in real time, the loss of the storage unit is considered, and the erasing and random reading and writing of the storage unit are reasonably arranged, thereby improving the durability and performance of the NAND Flash memory, and improving the user experience. And the overall efficiency of data read-write operation is improved.

A mechanism is provided efficient packing of network flits in a data processing network. Transaction messages for transmission across a communication link of a data processing network are analyzed to determine a group of transaction messages to be passed to a packing logic block for increased packing efficiency. The transaction messages are packed into slots of one or more network flits and transmitted across a communication link. The mechanism reduces the number of unused slots in a transmitted network.

The disclosed protocol analyser (100) decodes and analyse PCIe signals between a host node (102) and a device node (104), the signals being routed through an interposer (106). The analyser comprises at least a pair of high data rate 1:3 fanout buffers (108). The signals from the interposer are fed to the buffers (108) to obtain three copies of the signals. Three transceivers (110a, 110b, 110c) receive the signals from the fanout buffers and each of them samples one of the three copies of the signals. A link training and status state machine decoder (112) detects a speed or a change in speed in the PCIe signals. Based on the detected speed it selects one of the tapped signals, for protocol decoding and analysis. A protocol analyser logic block (114) analyses one of the copies of the signals conforming to the relevant PCIe protocols, from Gen1 to Gen6.

A streaming platform reader includes: a reader thread configured to retrieve messages from a plurality of partitions of a streaming platform, wherein each message in the plurality of partitions is associated with a unique identifier; a plurality of queues coupled to the reader thread configured to store messages or an end of partition signal from the reader thread, wherein each queue includes a first position that stores the earliest message stored by a queue; an extraction thread controlled by gate control logic that: compares the identifiers of all of the messages in the first positions of the queues of the plurality of queues, and forwards, to a pool of queues associated with a pool of processing threads, the message content of the message associated with the earliest identifier; and wherein the gate control logic blocks the extraction thread unless each of the queues contains a message or an end of partition signal.