711 results about "Logic block" patented technology

The invention discloses a hard disk pre-reading method and device, electronic equipment and a storage medium, and relates to the technical field of storage, and the method comprises the steps: under the condition that a data reading request is captured, analyzing the data reading request to obtain a logic block address corresponding to the data reading request, and according to the logic block address corresponding to the data reading request, obtaining a pre-reading result of the hard disk; according to the method, the access mode corresponding to the data reading request is determined, so that the pre-reading amount is adjusted, the pre-reading amount is dynamically adjusted through the access mode of the data reading request, and the data pre-reading operation is executed by using the adjusted pre-reading amount; according to the method and the device, the problem of low reading efficiency caused by cache pollution due to fixed pre-reading quantity in the related art is solved, and the technical effect of improving the cache efficiency and hit rate is achieved.

The invention relates to the technical field of data compression, and particularly discloses a method for realizing data compression in an RAID card and an RAID control chip, and the method comprises the following steps: S1, receiving a plurality of IO writing commands issued by a host, and obtaining the logic block address and length of each IO; s2, executing a merging operation on the plurality of IOs to generate a merged IO block; s3, performing a data compression operation on the merged IO block through a data compression engine to obtain compressed data; s4, establishing a mapping relation from a logic block address to a physical block address of the compressed data, and storing the mapping relation in a logic-to-physical mapping table; s5, the compressed data are written into a solid state disk through an RAID engine, and meanwhile, logic-to-physical mapping table metadata are stored persistently; s6, sending a recovery command or a zero-writing command to the solid state disk recovery space for the address space which is not used after compression; the problem that an existing SSD compression scheme is high in power consumption is solved, reliability is better, original user data content is closer, and the obtained compression effect is better.

The invention discloses an edge end large language model inference system. The system comprises a main computing chip, an LPDDR interconnection resource and a vertically stacked and packaged storage chip stack, the storage chip stack comprises an NAND flash memory chip and a DRAM (Dynamic Random Access Memory) chip, and the NAND flash memory chip and the DRAM chip are paired and share an LPDDR interconnection resource; the NAND flash memory chip comprises a flash memory chip bare chip and a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) chip bare chip which are three-dimensionally interconnected based on hybrid bonding; a flash memory array is arranged on the flash memory chip bare chip; a logic block is arranged on the CMOS chip bare chip; the main calculation chip reads a parameter matrix of a model full connection layer from the NAND flash memory chip and reads other parameters from the DRAM chip for calculation in a pre-filling stage of large language model reasoning; and the NAND flash memory chip performs full connection layer calculation in a decoding stage. The system provided by the invention can improve the external transmission and internal reading bandwidth.

The invention provides a big language model reasoning method and device, electronic equipment and a medium. The method comprises the steps that a reasoning request is received, an input sequence of the reasoning request is divided into one or more logic blocks according to the fixed lexical element number, and the input sequence is a lexical element sequence of cue words of the reasoning request; for each logic block: calculating a digest value of the logic block as a first digest value based on a digest value calculation sequence of the logic block, the digest value calculation sequence being a lexical sequence from a start lexical element of the input sequence to an end lexical element of the logic block; whether a second digest value identical to the first digest value exists or not is judged, the second digest value is a digest value of an inferred logic block with KV cache stored in a physical block, and the physical block is a storage space used for the KV cache; and allocating a physical block to the logic block according to the judgment result, and enabling the large language model to perform reasoning for the reasoning request.

The invention discloses a blockchain-based bidding and tendering data security processing method, which belongs to the technical field of data encryption, and specifically comprises the following steps of: segmenting original data into logic blocks according to a time axis, and generating a dynamic feature code containing a hierarchical relationship by using a current data hash value and a last feature segment of a preorder block through nonlinear fusion; and constructing a three-dimensional verification topology network containing a timestamp longitudinal chain, a content association transverse tree and an environment parameter space matrix. And establishing a dynamic verification channel, activating three-anchor-point association path cross verification when data is called, and generating an integrity proof. A self-destruction mechanism is implanted in verification, and data blocks are subjected to gradient erasure when abnormal conditions occur. And finally, generating a traceability map, dispersing encryption key parameters in multiple domains, and recording a storage domain coordinate hash abstract through a block chain. The method is suitable for high-security electronic bidding and tendering scenes.

In various examples, data storage is managed using a distributed storage management system that is resilient. Data blocks of a logical block device may be distributed across multiple nodes in a cluster. The logical block device may correspond to a file system volume associated with a file system instance deployed on a selected node within a distributed block layer of a distributed file system. Each data block may have a location in the cluster identified by a block identifier associated with each data block. Each data block may be replicated on at least one other node in the cluster. A metadata object corresponding to a logical block device that maps to the file system volume may be replicated on at least another node in the cluster. Each data block and the metadata object may be hosted on virtualized storage that is protected using redundant array independent disks (RAID).

A method for use in a storage processor, comprising: receiving an I / O request that is associated with a logical block address; allocating a cache slot that corresponds to the logical block address, wherein allocating the cache slot includes: identifying a type of memory that is required to host the cache slot by using one or more configuration settings that are associated with the cache slot, identifying a cache slot that is both available and hosted in the identified type of memory, and assigning the identified cache slot to the logical block address; and executing the I / O request by using the allocated cache slot, wherein using the allocated cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command that is associated with the allocated cache slot.

Techniques for interfacing electronics are disclosed. A system-on-chip is accessed. The system-on-chip includes a network-on-chip (NoC) topology. The NoC sub-topologies are based on a physical location of the plurality of logic blocks. A first sub-topology is coupled to a receiving block, wherein the coupling includes inserting an interfacing block. The interfacing block includes a digital PLL (DPLL). The first sub-topology sends to the interfacing block data and a first clock. The first clock is input to the DPLL and used as a reference clock. The DPLL generates a second clock that is used to save the data that was sent. The interfacing block forwards to the receiving block the second clock and the data that was saved. The second clock is used as the internal clock in the receiving sub-topology. The NoC communications includes packets. Additional interfacing blocks are instantiated as necessary.

Disclosed in the present disclosure are a resource allocation method and apparatus, an electronic device, and a storage medium, which relates to the field of computer technology. The method includes: determining one or more unallocated compute express link (CXL) memory logical blocks in a CXL memory resource pool in response to determining that a remaining memory capacity of a first host is less than a remaining memory capacity threshold of the first host; selecting a target CXL memory logical block from among the one or more unallocated CXL memory logical blocks in the CXL memory resource pool; and allocating a memory resource corresponding to the target CXL memory logical block to the first host via a CXL switch. This solves the problem of complex management of the CXL memory resource pool.

Methods, systems, and devices for low latency logical (L3A) unit for a memory system are described. For example, a logical unit, such as an L3Alogical unit or L3A logical unit number (LUN), may include a storage area for storing information for system swap operations, including, for example, a logical-block-address (LBA) range for one or more single-level-cells (SLCs). The logical unit may include a logical-to-physical (L2P) mapping table stored in a local memory of a memory system controller, such as in static random access memory (SRAM). In some examples, a reserved storage area may be overprovisioned, and the logical unit may be associated with a higher priority and a larger granularity than one or more other logical units. Further, one or more read-only (RO) descriptors stored to one or more registers, one or more provisioning parameters, or both, may be defined for the logical unit.

The present application discloses methods of operating a memory system, memory systems, hosts, and memory controllers. An example method includes receiving a read command, the read command including a first logical block address (LBA); based on a first attribute identifier corresponding to a first mapping table block in a compressed mapping table, determining a first physical address corresponding to the first LBA in the first mapping table block, the compressed mapping table including a plurality of attribute identifiers, the plurality of attribute identifiers corresponding to different mapping table blocks in a logical-to-physical (L2P) mapping table, an attribute identifier indicating whether physical addresses in a corresponding mapping table block are continuous, and the first mapping table block being the mapping table block in which the first LBA is located; and performing a read operation on a memory device based on the first physical address.

The invention discloses a server and a hard disk medium error processing method, and relates to the technical field of servers, the server comprises a controller and a redundant array of independent disks connected with the controller, the redundant array of independent disks comprises a plurality of hard disks, and different data in the same strip is stored in the same sector of each hard disk. If the controller detects that the at least two hard disks have medium errors in the same target sector, the controller obtains a target logic block address corresponding to the target sector in the at least two hard disks, and for any one of the at least two hard disks, a new sector is redistributed for the target logic block address corresponding to the hard disk in a standby sector preset by the hard disk, and reconstructing the new sectors allocated to the at least two hard disks so as to enable the redundant array of independent disks to work normally. According to the method and the device, the waste of storage resources in the redundant array of independent disks caused by direct replacement of a new redundant array of independent disks is reduced, and the user experience is improved.

A configuration may identify an IC chip component the IC chip component comprising one of a logic block, a memory block, and a power grid. A configuration may train a machine learning model based on one or more features and one or more labels corresponding to the identified IC chip component. A configuration may generate an artificial intelligence model having characteristics comprising the trained machine learning model, the one or more features, and the one or more labels. A configuration may generate a prediction for the one or more labels based on past, present and projected one or more features. A configuration may monitor future label prediction versus a failure threshold. A configuration may generate a notification in response to the failure threshold being reached.

A mechanism is provided efficient packing of network flits in a data processing network. Transaction messages for transmission across a communication link of a data processing network are analyzed to determine a group of transaction messages to be passed to a packing logic block for increased packing efficiency. The transaction messages are packed into slots of one or more network flits and transmitted across a communication link. The mechanism reduces the number of unused slots in a transmitted network.

A storage device includes a memory storage region and a controller having a processor. The processor retrieves user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command. The retrieved user data includes a first hash received through a host interface in a prior host data transmission. The processor further performs error correction on the user data to generate error-corrected user data. The processor further causes a cryptographic engine to produce a second hash of the error-corrected user data. The first hash is compared to the second hash associated with the error-corrected user data to determine a match result. A notification is generated in response to the match result.

The invention relates to the technical field of safety control of fire exit doors, in particular to an emergency unlocking device and system of an intelligent fireproof door. The analysis subsystem outputs a fire alarm confidence coefficient value and an operation intention intensity value; the arbitration subsystem sends a blocking signal to the automatic locking control system and activates a to-be-decoupled state of the execution subsystem when the intensity of the operation intention exceeds a threshold value; the execution subsystem synchronously adjusts a mechanical transmission stroke parameter and an electromagnetic latching current parameter according to the intensity value of the operation intention; the fault-tolerant subsystem switches the mechanical locking mechanism to a geometric dead point position to release automatic control connection; and the traceability subsystem records the operation data and maintains storage when the power supply is interrupted. According to the invention, a closed-loop control chain from signal sensing to physical decoupling is formed, the problem of authority conflict of automatic locking logic blocking manual operation is solved, and the timeliness and reliability of emergency unlocking are improved.

Embodiments of the present application provide a method, an apparatus, and a system for processing access to object storage, where the method includes: establishing, by a user host, a first mapping relationship between first attribute information and second attribute information in advance; in response to reception of a first data read request, determining a data management unit corresponding to an object to be read by the first data read request according to the first mapping relationship; determining a logical block address of the data management unit; and accessing the server-side cache or the local cache of the user host to acquire data of the logical block address based on an access protocol of block storage and the logical block address.

The present invention discloses a method for secure processing of bidding data based on blockchain, belonging to the field of data encryption technology. Specifically, it includes: dividing the original data into logical blocks along the time axis, and generating a dynamic feature code with a hierarchical relationship by non-linearly fusing the current data hash value with the last feature segment of the previous block. Constructing a three-dimensional verification topology network including a time-stamped vertical chain, a content-associated horizontal tree, and an environmental parameter space matrix. Establishing a dynamic verification channel, activating the cross-verification of the three-anchor point association path when retrieving data, and generating an integrity proof. A self-destruction mechanism is implanted during verification, and the data block is gradually erased in case of anomalies. Finally, a traceability map is generated, the key parameters are encrypted and stored dispersedly in multiple domains, and the hash digest of the storage domain coordinates is recorded through the blockchain; the present invention is applicable to high-security electronic bidding scenarios.

A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.

The invention relates to an SSD (Solid State Disk) heat dissipation optimization method and system based on dynamic temperature control. The method comprises the following steps: acquiring a thermal state vector of an SSD through inner and outer ring temperature monitoring; predicting a future 5S temperature track through a long short-term memory network model, and generating a temperature prediction sequence; generating a computing power distribution proportion based on the temperature prediction sequence, and determining a capacity migration proportion at the same time; according to the real-time temperature value of each logic block in the block temperature mapping table and the computing power distribution proportion and capacity migration proportion, heat-sensitive and heat-tolerant classification is carried out on the I / O queue, and an optimized scheduling sequence is generated; calculating a power supply phase parameter according to the access frequency of the heat-sensitive block of the optimized scheduling sequence, and generating a pulse type heat dissipation control signal; the SSD power supply phase is dynamically adjusted according to the pulse type heat dissipation control signal, heat dissipation optimization is conducted through the pulse width modulation technology, updated heat state data is fed back to inner and outer ring temperature monitoring, and therefore the purpose of dynamic intelligent temperature control of the SSD is achieved.

The invention discloses a command execution method and device, equipment and a medium, and relates to the field of command processing, and the method comprises the steps: determining whether to update a current aggregation command based on an original read-write command or not by judging whether the original read-write command currently issued by a host meets a preset aggregation condition or not; wherein the preset aggregation condition comprises that the original read-write command and the current aggregation command correspond to the same target disk array card and have the same identification information; and if the original read-write command does not meet a preset aggregation condition or the updated current aggregation command meets a preset end condition, determining the number of logic blocks required by a full stripe based on the target disk array card, and splitting the current aggregation command so as to execute corresponding read-write operation on the target disk array card based on the split command. According to the method, the aggregation command is subjected to full stripe splitting, and the read-write operation is executed on the disk array card based on the split command, so that the read-write frequency of the disk in the disk array card can be reduced, and the read-write performance of the disk is improved.

There is provided a field-programmable gate array, FPGA, device (100) comprising a configurable logic block, CLB, (110) comprising a logic inverter (120) comprising a high-electron-mobility transistor, HEMT, (130), wherein the HEMT comprises: a Si substrate (384); an AlyGay-1N layer structure (380), wherein 0<y≤1; a GaN layer structure (382); and a crystal transition layer structure (386) arranged on the Si substrate. The crystal transition layer comprises: a plurality of vertical nanowire structures (388) perpendicularly arranged on the Si substrate, and an AlxGax-1N layer structure (389), wherein 0≤x<1, wherein the AlxGax-1N layer structure is arranged to vertically and laterally enclose the vertical nanowire structures. There is also provided an AI processing system comprising said FPGA device (100).

A network interface controller (NIC) capable of facilitating efficient data request management is provided. The NIC can be equipped with a command queue, a message chopping unit (MCU), and a traffic management logic block. During operation, the command queue can store a command issued via a host interface. The MCU can then determine a type of the command and a length of a response of the command. If the command is a data request, the traffic management logic block can determine whether the length of the response is within a threshold. If the length exceeds the threshold, the traffic management logic block can pace the command such that the response is within the threshold.

Provided is a method for writing data to a Solid State Disk (SSD), an apparatus and the SSD. According to the method, a Logical Block Address (LBA) of each of a plurality of pieces of written data stored into a target cache module is acquired to obtain a plurality of Logical Block Addresses (LBAs); the plurality of pieces of written data in the buffer is stored into a solid-state storage unit of the SSD; whether the plurality of LBAs are consecutive is determined to obtain a determination result. In a case where the determination result indicates that the plurality of LBAs are consecutive, a Physics Block Address (PBA) of each of the plurality of pieces of written data in the solid-state storage unit is acquired to obtain a plurality of PBAs and a target mapping table according to the plurality of LBAs and the plurality of PBAs is generated.

This specification provides text generation methods, apparatuses, and storage medium devices. One method includes the following operations. In an iteration of a plurality of iterations under a large language model (LLM): estimating a first text sequence following a current text sequence based on a speculative decoding method, forming a plurality of candidate sequences based on the current text sequence and subsequences of the first text sequence, allocating logical blocks to text units in the plurality of candidate sequences in a key-value cache, to store attention information of the text units, mapping the allocated logical blocks to physical blocks based on a first criterion, and determining, by the LLM, a newly generated text unit in the iteration by using attention information of each candidate sequence in the key-value cache, to form a current text sequence for a next iteration of the plurality of iterations.

Ultrasound image devices, systems, and methods are provided. An intraluminal ultrasound imaging system, comprising a patient interface module (PIM) in communication with an intraluminal imaging device comprising an ultrasound imaging component, the PIM comprising a first reconfigurable logic block including a first plurality of logic elements interconnected by first reconfigurable interconnection elements; a configuration memory coupled to the first reconfigurable logic block; and a processing component coupled to the configuration memory, the processing component configured to detect a device attribute of the intraluminal imaging device in communication with the PIM; and load at least one of a first configuration or a second configuration to the configuration memory based on the detected device attribute to configure one or more of the first reconfigurable interconnection elements such that the first plurality of logic elements are interconnected for communication with the ultrasound imaging component.

The invention relates to the technical field of space optical communication and distance measurement, in particular to a distance measurement method and device based on a non-equal sampling digital phase discriminator and a storage medium. A non-equal sampling method is used for carrying out sampling and phase discrimination on data bit clocks on two asynchronous clock domains for sending and receiving GTX, and hardware resources required for processing all use an FPGA internal digital logic block; the clock processing rate and the GTX sending and receiving clock rate are kept in a non-integer multiple relationship, so that the measurement precision of the phase difference between the two clock rates is improved, and the purpose of improving the laser ranging precision on the basis of simplifying the hardware design of a ranging system is achieved.

A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes a dual-mode port (“DMP”), configurable logic blocks (“LBs”), routing connections, and a configuration memory for providing configuration data to facilitate user-defined logic functions. The DMP, in one aspect, is operable to handle the configuration data during a configuration mode. Alternatively, the DMP is operable to handle the user data during a logic operation mode. In one aspect, the user configuration data contains the address of the second memory containing DCD.

Embodiments of the present invention provide a data processing method, a device, and a storage medium. The method comprises: acquiring first access log information of a block device in a first time period, wherein the block device corresponds to a plurality of logical block addresses; determining a target grouping length on the basis of the first access log information so as to group the plurality of logical block addresses on the basis of the target grouping length to obtain a plurality of groups, wherein the logical block addresses in a same group have similar access behaviors; determining access feature values respectively corresponding to the plurality of groups; and on the basis of the access feature values respectively corresponding to the plurality of groups, determining cold and hot data categories respectively corresponding to the plurality of groups.

The invention provides an automatic rendering method and system of a building block model, a medium and a product, and aims to solve the problems of low efficiency and high resource occupation in large-scale building block model rendering. The method comprises the following steps: dividing a model into logic blocks; generating a virtual camera array and a virtual light source matrix based on the blocks; performing multi-resolution rendering on each block according to the priority determined by the view angle area; and finally splicing a rendering result. According to the method, through blocking processing and differentiated multi-resolution rendering, the consumption of computing resources is effectively reduced, the rendering efficiency is remarkably improved, and meanwhile, the rendering image quality of the complex building block model is ensured.