72 results about "Logic block" patented technology

This invention discloses a security chip based on a configurable lookup table. The security chip includes: at least one configurable logic block, each containing at least one configurable lookup table unit; a dynamic mask generator connected to the configurable lookup table unit, dynamically generating a mask sequence according to the current processing clock cycle; a reconfiguration controller connected to the dynamic mask generator, changing the configuration values ​​of the configurable lookup table units in real time according to a security policy; and a security execution engine, whose input is connected to the output of the configurable lookup table unit, performing secure operations based on the masked lookup results; wherein the configurable lookup table unit presents different truth table mappings for the same logic input in at least two different clock cycles. This invention enables the lookup table unit to present different truth table mappings in different clock cycles, breaking the deterministic correlation between power consumption characteristics and data, and effectively resisting side-channel attacks such as differential power analysis.

Disclosed are predecoders and structures including the predecoders. Each predecoder includes, among other components, first and second latches controlled by write and read clock signals, respectively, and a multiplexer-enabled write logic bypass path. During a write, an address signal is latched by the first latch and propagated through logic downstream of the first latch (including through a write logic block) to the second latch (which is transparent). During a read, the write logic bypass path is activated so the address signal bypasses the first latch and the write logic block and is instead propagated only through logic downstream of the write logic block to the second latch (which periodically latches the received signal). In both operations, a predecoded address signal is output but, due to activation of the write logic bypass path during the read, the time between receiving the address signal and outputting the predecoded address signal is reduced.

A memory control unit of a memory device includes at least one hardware processor; and memory storing instructions that cause the at least one hardware processor to perform operations comprising: generating a scrambler seed and a logical block address (LBA) for a block of write data received by the memory control unit from a host device; generating a flash translation layer (FTL) to map the LBA to a physical address (PA); scrambling the block of data using the scrambler seed; encrypting the scrambler seed, the LBA, and the PA in the FTL using an encryption key; initiating writing a scrambled block of data and encrypted LBA and scrambler seed to a memory array; and decrypting the FTL using an incorrect encryption key in response to an erase command received by the memory control unit from the host device.

A data compression method and a related device, used for reducing I / O overhead. The data compression method comprises: acquiring attribute information of a logic block, wherein the logic block comprises a plurality of data pages, and the attribute information indicates data sizes of data contained in the plurality of data pages across a plurality of time periods; if the attribute information indicates that the total data size of the data contained in the plurality of data pages during a target time period is greater than or equal to a first threshold, compressing the data contained in the logic block, and storing the result obtained by compression, wherein the target time period includes at least time period among the plurality of time periods, and the time interval between the target time period and the current moment is greater than or equal to a time threshold; and if the attribute information indicates that the total data size of the data contained in the plurality of data pages during the target time period is less than the first threshold, determining not to compress the data contained in the logic block.

Various techniques are provided to efficiently synchronize clock and data signals in programmable logic devices (PLDs). A method includes configuring a programmable logic device (PLD) having a fabric of programmable logic blocks arranged in a plurality of regions; routing data carry chains in a first direction across the fabric to each of the plurality of regions; placing global clock circuitry at a first edge of the PLD; and routing the global clock to a corresponding first edge of each region via a global clock trunk and a plurality of clock branches, the global clock trunk propagating the global clock signal across the fabric and in each region, in the same direction as the data carry chains.

The present technology enhances workload management of data storage systems by using an internal copy function and / or a zone-append technology. The internal copy function is used, e.g., in merge operations to move data between locations on a disk without using off-disk resources (e.g., processing or memory of a CPU). Zone-append technology uses nameless writes (e.g., write instruction without an assigned destination address on the disk) to combine IO units from different threads to be written to a common zone of a disk (e.g., a shingled magnetic recording (SMR) disk). Sequential addresses are assigned to IO units from different threads based on their order in the write queue, reducing the latency and seek time typically associated with random writes. The zone-append technology, e.g., uses sequential write operations within specified zones, allowing the disk to determine the actual write location and to report post-write logical block addresses (LBAs).

Methods, systems, and devices for physical prefetch are described. A memory system may prefetch data from physical addresses that are sequential to a physical address that has recently been read by the memory system. For example, the memory system may determine that a rate of access for a virtual block exceeds a threshold, and the memory system may prefetch the physically sequential data in response to the rate of access exceeding the threshold. In some examples, the memory system may receive a command to read a logical block address corresponding to a first physical address. The memory system may determine that the rate of access to the virtual block exceeds the threshold. The memory system may identify one or more second physical addresses that are sequential to the first physical address, and the memory system may transfer data from the one or more second physical addresses to a buffer.

This invention discloses a data storage method and device based on a block storage engine. The data storage method includes: dividing a logical block of the block storage engine into multiple first logical units; dividing a second logical unit according to the capacity of the first logical units; dividing the physical disk space into physical mapping units with fixed capacities according to the capacity of the logical blocks; allocating corresponding physical mapping units according to the capacity of the logical blocks and storing physical data in the physical mapping units; forming the physical storage address of the physical data and the metadata corresponding to the physical storage address based on the first address mapping relationship between the logical blocks and the physical mapping units, the second address mapping relationship between the first logical units and the physical mapping units, and the physical address of each physical mapping unit. The data storage method based on the block storage engine provided by this invention effectively reduces the amount of metadata in address mapping in a distributed block storage engine.

Embodiments can relate to a field-programmable gate array having a platform including an interconnect network of configuration blocks. The configuration blocks can include one or more configurable logic blocks (CLBs), one or more connection blocks (CBs), and one or more switch blocks (SBs). Each CLB can include a look-up table (LUT) cell configured to perform a logic operation. Each CB can be configured to connect one or more CLBs to the interconnection network. Each SB can be configured to connect routes between the configuration blocks. One or more or the CBs can include a 1FeFET for a single configuration, one or more of the CBs can include a 2T-2FeFET for a multiple configuration, one or more of the CLBs can include a 1FeFET LUT cell for a single configuration, or one or more of the CLBs can include two 1FeFET LUT cells for a multiple configuration.

A floating reference generation circuit for a SMPS includes core biasing, driver logic, and transient biasing blocks. The core biasing block generates temperature and process-tracking reference voltages. The driver logic block uses these references to generate a floating reference voltage through level-shifting and output circuits, with compensation capacitors improving settling time and stability. The transient biasing block employs a diode-transistor cascade and feedback loops to control transitions between voltage levels while maintaining voltage stress limits. The circuit can be configured as either a floating ground generator or floating supply generator through polarity adaptation of the components. Coordination between floating ground and supply reference signals enables precise timing control of voltage transitions. The open-loop architecture enables stable high-speed operation across varying load and line conditions, while eliminating separate reference generation circuits. Implementation provides improved efficiency and noise isolation for analog components while reducing settling time and maintaining high-voltage tolerance.

Provided is a method for writing data to a Solid State Disk (SSD), an apparatus and the SSD. According to the method, a Logical Block Address (LBA) of each of a plurality of pieces of written data stored into a target cache module is acquired to obtain a plurality of Logical Block Addresses (LBAs); the plurality of pieces of written data in the buffer is stored into a solid-state storage unit of the SSD; whether the plurality of LBAs are consecutive is determined to obtain a determination result. In a case where the determination result indicates that the plurality of LBAs are consecutive, a Physics Block Address (PBA) of each of the plurality of pieces of written data in the solid-state storage unit is acquired to obtain a plurality of PBAs and a target mapping table according to the plurality of LBAs and the plurality of PBAs is generated.

A method for managing virtual machines (VMs) obtaining, by a metadata file manager, an instant access request for instant access to a backup of a VM to execute in a production host, wherein the backup is stored in a backup storage system, in response to the instant access request: obtaining a configuration selection for the instant access of the backup, obtaining backup metadata associated with the backup, generating, at the production host, a temporary virtual disk based on the configuration selection and the backup metadata, generating, in the metadata file manager, a second virtual disk comprising logical blocks, mapping VM data stored in the backup storage system to the logical blocks in the second virtual disk, configuring the VM to read from the temporary virtual disk, and servicing a write request of the temporary virtual disk using the mapping of the VM data in the second virtual disk.

The invention provides an intelligent teaching method and system, electronic equipment, a computer storage medium and a computer program product, and the method is applied to the technical field of computers, and comprises the steps: obtaining a binocular image containing a hand of a user, and determining a fingertip position of the hand of the user based on the binocular image; obtaining a to-be-detected text area in a set range of the fingertip position, and determining a target algorithm type corresponding to the to-be-detected text area; all logic blocks related to the target algorithm type are extracted from a logic block library, and when parameter setting trigger operation for the target logic block in all the logic blocks is detected, the target logic block subjected to parameter setting is obtained; and fusing the target logic block after parameter setting and the logic block without parameter setting to obtain a fusion result, and displaying the fusion result.

A memory sub-system having: a host interface operable on a connection from the host interface to a host system outside of the memory sub-system; random access memory cells configured to provide a memory space accessible to the host system over the connection via a memory access protocol; non-volatile memory cells configured to provide a storage space accessible to the host system over the connection via a storage access protocol; and a controller configured to execute a storage access request, received from the host system over the connection according to the storage access protocol, to read data into the memory space from a logical block address in the storage space. The controller can also execute a storage access request, received over the connection according to the storage access protocol, to write data available in the memory space to a logical block address in the storage space.

The embodiment of the invention provides a data processing method and device, electronic equipment and a storage medium. The method comprises the following steps: receiving a data read-write request carrying logic block index information, wherein the logic block index information is used for indicating a target logic block to which target data belongs; according to the logic block index information, obtaining the physical address offset of the target logic block in the physical storage space through the data index interface; on the basis of the physical address offset, reading or writing of target data is executed in a physical storage space, the physical storage space is used for storing data in at least one logic block, and multiple logic blocks with continuous indexes are mapped to discontinuous physical address areas in the physical storage space; the data index interface is constructed based on a logic block data arrangement mode. According to the method, a uniform data index interface is provided, so that a logic block physical address corresponding to a logic block index identifier is supported to be accurately obtained, and the method is adaptive to the situation that physical and logic arrangement sequences are inconsistent under a specific storage architecture.

Aspects relate to a divide by 3 prescaler for an integrated circuit. An apparatus includes a first logic block configured to generate a first input pulse at a rising edge of a clock signal, and a second logic block configured to generate a second input pulse after the first input pulse that ends at a falling edge of the clock signal. The falling edge is for a clock cycle subsequent to the rising edge. A third logic block is coupled to the first input pulse and the second input pulse and configured to generate a divide by 3 clock output.

This invention discloses an adaptive segmentation method and system for system logs based on block counting, belonging to the field of data processing technology for rail transit signaling systems. Addressing the problems of easily corrupted logic, uneven segmentation sizes, low processing efficiency, and poor encoding compatibility caused by the special structure of CTC system logs ("text lines + hexadecimal lines"), this invention first defines and identifies the smallest logical block unit in the log; then, it performs adaptive parameter calculation based on block counting to determine the theoretical number of blocks each segmented file can hold; finally, it controls the writing process through dynamic threshold judgment, precisely controlling the size of individual files while ensuring the absolute integrity of logical blocks. This method and system effectively solve the core defects such as the splitting of logical units, excessive file size deviation, and excessive processing time, achieving high-fidelity and high-efficiency segmentation of logs at the 100GB level, providing a high-quality data foundation for subsequent fault tracing and intelligent operation and maintenance.

Embodiments of this disclosure provide a storage controller, a storage system, and a method of operating the storage controller. The storage system includes a non-volatile memory device. The non-volatile memory device includes a plurality of memory blocks and a storage controller, the storage controller being configured to access the non-volatile memory device using block addresses of the memory blocks. The storage controller is configured to: receive a plurality of first reliability levels mapped to logical block addresses from the non-volatile memory device; map access frequency information included in dataset management information received from a host to a plurality of second reliability levels; update the plurality of first reliability levels to a plurality of second reliability levels based on logical block address range information in the dataset management information; and access the non-volatile memory device by using a block address corresponding to one of the plurality of second reliability levels, allocated based on the access address, based on an access command and an access address received from the host.

A system having a processing device, a memory sub-system having a memory space accessible via a memory access protocol and a storage space accessible via a storage access protocol, and a computer bus connecting the memory sub-system and the host system. The processing device is to configure a storage access request to identify a logical block address in the storage space and a first memory address in the memory space in the memory sub-system. The memory sub-system is to identify, based on the first memory address during execution of the storage access request, a plurality of memory addresses consecutive in the memory space, and execute the storage access request to: read data from the logical block address to the plurality of memory addresses in the memory space; or write, to the logical block address, data at the plurality of memory addresses in the memory space.

A hardware random number generator (HW-RNG) and related method are disclosed. The HW- RNG comprises a sample generation stage, adapted to produce primary samples from a plurality of primitive probability distributions, a sample processing stage and a control unit. The sample generation stage includes sets of programmable p-bit devices, a programming unit to adjust the mean values for each set of p-bit devices, and a distinct sampling circuit for each set of p-bit devices. The sample processing stage comprises function logic blocks and selection circuitry configured to route at least one subset of the primary samples to a corresponding function logic block. The control unit is configured to obtain information relating to a composition of basis distributions representative of a target distribution, instruct the function logic block to perform at least arithmetic operation identified by the information, instruct the programming unit to program the sets of p-bit devices according to the composition of basis distributions, and generate the select signal to operatively couple the function logic block to sampling circuits that produce primary samples of random variables defined by the composition of basis distributions.

A system and method for status reporting for a storage device. In some embodiments, the method includes: receiving, by a persistent storage device, a command, the command requesting a status associated with a first logical block address; determining the status; and sending a response to the command, the response including the status.

Embodiments of the present application provide a shift logic circuit optimization method, a computer device and a storage medium. The method comprises: obtaining a first shift logic circuit, the first shift logic circuit comprising a first shift sub-circuit; determining a minimum input signal set corresponding to the first shift logic circuit, the minimum input signal set comprising the least input signals driving all logic outputs of the first shift logic circuit; constructing a second shift sub-circuit based on the minimum input signal set; and replacing the first shift sub-circuit in the first shift logic circuit with the second shift sub-circuit to obtain a second shift logic circuit. The technical solution provided by the embodiments of the present application has the advantages that the number of combination logic blocks included in the second shift logic circuit is also less than the number of combination logic blocks included in the first shift logic circuit, the number of logic levels included in the second shift logic circuit is generally shallower, the circuit complexity is lower, and it is easier to implement further optimization of the second shift logic circuit by a subsequent synthesis tool.

This invention relates to the field of data storage, and discloses a data repair method, device, and medium for an embedded storage system. In this invention, the storage space of the embedded storage system includes multiple logical blocks and reference check values ​​corresponding to the multiple logical blocks. The method includes: determining the target logical block to be checked, and calculating the current check value of the data within the target logical block; comparing the current check value with the reference check value corresponding to the target logical block; if the current check value and the reference check value do not match, obtaining the corresponding backup data segment according to the logical block index of the target logical block, and overwriting the backup data segment into the target logical block. This addresses the problems of low efficiency in locating data corruption and the need for manual intervention or system restart during the repair process, which affects the continuous availability of the device in related technologies.

This invention discloses a method, device, and medium for implementing high-performance NVMe CAW commands in SSDs, relating to the field of SSD technology. The method includes: a controller receiving a CAW command, wherein the command portion for comparison operations in the CAW command does not carry user data to be compared, and the CAW command contains a target logical block address; the controller searching for a corresponding mapping table entry from a logical address to a physical address mapping table based on the target logical block address to obtain the physical address status recorded in the mapping table entry; the controller determining the success or failure of the comparison operation based on the physical address status; and the controller determining whether to execute the write operation carried in the CAW command based on the success or failure of the comparison operation. This invention can effectively eliminate PCIe transmission overhead for comparison data and avoid NAND media read access latency while confirming that the target location is not occupied before writing.

An embodiment of an electronic apparatus may include one or more substrates; and a controller coupled to the one or more substrates, the controller including logic to control access to a NAND-based storage media that includes a first cell region with a first number of levels and a second region with a second number of levels that is different from the first number of levels, determine logical block address locations that correspond to a user configurable capacity placeholder, and adjust respective sizes of the first cell region and the second cell region at runtime based on the logical block address locations. Other embodiments are disclosed and claimed.

A system and method for debugging logic elements in a configurable logic block using only one pin. A synchronization pulse is generated, and each logic element is connected, in turn, using a digital selector switch. The synchronization pulse and a logic state of each logic element are received, in turn, by an output buffer. First, second, and third digital outputs levels are enabled on a single output line using a voltage divider configuration of resistors connected to the output line of the output buffer. The output levels include the synchronization pulse, a low logic state, and a high logic state. The synchronization pulse and the logic state of each logic element are outputted as the different output levels, in turn, via a single debug pin connected to an oscilloscope or other display device for visualization. The debug pin may be shared with other functions when not being used for debugging.

This invention provides a method for optimizing the area of ​​a double-precision multiply-accumulator based on pipelined pause technology. Considering the application scenarios of double-precision floating-point data, while meeting the performance requirements of most double-precision floating-point computation scenarios, the method improves the multiply-accumulator algorithm by changing the dual data path to a single data path during the double-precision floating-point multiply-accumulator computation process. By combining this with real-world application scenarios, it ensures that performance loss due to pipelined pauses is not incurred in common situations. For special low-probability events, performance is sacrificed by reducing the area of ​​the multiply-accumulator. The bit width is reduced based on the actual statistical situation of the operator, and pipelined pause multiplexing logic blocks are used to improve the area of ​​the adder, shifter, and leading zero statistics module, thereby improving the area of ​​the multiply-accumulator module.

In an example, a memory controller is configured to: check whether a logical block address corresponding to a host read command is maintained in a write buffer; determine a level of an amount of drift corresponding to the logical block address if the logical block address is not maintained in the write buffer, where different levels of the amount of drift correspond to different read voltages; and send a read command to a non-volatile memory device according to the level of the amount of drift corresponding to the logical block address. At least two of the processes of checking whether the logical block address is maintained, determining the level of the amount of drift, or sending the read command are performed in parallel.