432 results about "Logic block" patented technology

The invention relates to the technical field of data compression, and particularly discloses a method for realizing data compression in an RAID card and an RAID control chip, and the method comprises the following steps: S1, receiving a plurality of IO writing commands issued by a host, and obtaining the logic block address and length of each IO; s2, executing a merging operation on the plurality of IOs to generate a merged IO block; s3, performing a data compression operation on the merged IO block through a data compression engine to obtain compressed data; s4, establishing a mapping relation from a logic block address to a physical block address of the compressed data, and storing the mapping relation in a logic-to-physical mapping table; s5, the compressed data are written into a solid state disk through an RAID engine, and meanwhile, logic-to-physical mapping table metadata are stored persistently; s6, sending a recovery command or a zero-writing command to the solid state disk recovery space for the address space which is not used after compression; the problem that an existing SSD compression scheme is high in power consumption is solved, reliability is better, original user data content is closer, and the obtained compression effect is better.

Techniques for interfacing electronics are disclosed. A system-on-chip is accessed. The system-on-chip includes a network-on-chip (NoC) topology. The NoC sub-topologies are based on a physical location of the plurality of logic blocks. A first sub-topology is coupled to a receiving block, wherein the coupling includes inserting an interfacing block. The interfacing block includes a digital PLL (DPLL). The first sub-topology sends to the interfacing block data and a first clock. The first clock is input to the DPLL and used as a reference clock. The DPLL generates a second clock that is used to save the data that was sent. The interfacing block forwards to the receiving block the second clock and the data that was saved. The second clock is used as the internal clock in the receiving sub-topology. The NoC communications includes packets. Additional interfacing blocks are instantiated as necessary.

Methods, systems, and devices for low latency logical (L3A) unit for a memory system are described. For example, a logical unit, such as an L3Alogical unit or L3A logical unit number (LUN), may include a storage area for storing information for system swap operations, including, for example, a logical-block-address (LBA) range for one or more single-level-cells (SLCs). The logical unit may include a logical-to-physical (L2P) mapping table stored in a local memory of a memory system controller, such as in static random access memory (SRAM). In some examples, a reserved storage area may be overprovisioned, and the logical unit may be associated with a higher priority and a larger granularity than one or more other logical units. Further, one or more read-only (RO) descriptors stored to one or more registers, one or more provisioning parameters, or both, may be defined for the logical unit.

A network interface controller (NIC) capable of facilitating efficient data request management is provided. The NIC can be equipped with a command queue, a message chopping unit (MCU), and a traffic management logic block. During operation, the command queue can store a command issued via a host interface. The MCU can then determine a type of the command and a length of a response of the command. If the command is a data request, the traffic management logic block can determine whether the length of the response is within a threshold. If the length exceeds the threshold, the traffic management logic block can pace the command such that the response is within the threshold.

Provided is a method for writing data to a Solid State Disk (SSD), an apparatus and the SSD. According to the method, a Logical Block Address (LBA) of each of a plurality of pieces of written data stored into a target cache module is acquired to obtain a plurality of Logical Block Addresses (LBAs); the plurality of pieces of written data in the buffer is stored into a solid-state storage unit of the SSD; whether the plurality of LBAs are consecutive is determined to obtain a determination result. In a case where the determination result indicates that the plurality of LBAs are consecutive, a Physics Block Address (PBA) of each of the plurality of pieces of written data in the solid-state storage unit is acquired to obtain a plurality of PBAs and a target mapping table according to the plurality of LBAs and the plurality of PBAs is generated.

This specification provides text generation methods, apparatuses, and storage medium devices. One method includes the following operations. In an iteration of a plurality of iterations under a large language model (LLM): estimating a first text sequence following a current text sequence based on a speculative decoding method, forming a plurality of candidate sequences based on the current text sequence and subsequences of the first text sequence, allocating logical blocks to text units in the plurality of candidate sequences in a key-value cache, to store attention information of the text units, mapping the allocated logical blocks to physical blocks based on a first criterion, and determining, by the LLM, a newly generated text unit in the iteration by using attention information of each candidate sequence in the key-value cache, to form a current text sequence for a next iteration of the plurality of iterations.

A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes a dual-mode port (“DMP”), configurable logic blocks (“LBs”), routing connections, and a configuration memory for providing configuration data to facilitate user-defined logic functions. The DMP, in one aspect, is operable to handle the configuration data during a configuration mode. Alternatively, the DMP is operable to handle the user data during a logic operation mode. In one aspect, the user configuration data contains the address of the second memory containing DCD.

A data access method, apparatus and device, in the application, a physical space of a storage device is mapped into a logic space, the logic space comprises a plurality of logic blocks, and the physical space comprises a plurality of physical blocks. The storage device obtains a data reading instruction, wherein the data reading instruction is used for requesting to read the first data; the storage device determines a target index entry according to the logical address of the first data, the target index entry indicates a mapping relationship between a first logical block and a first physical block, and the first logical block is a logical block to which the logical address belongs. The storage device determines the physical address of the compressed first data according to the first physical block and a first target data volume, wherein the first target data volume is the data volume of the compressed first data; the storage device obtains the compressed first data according to the physical address; and decompressing the compressed first data, and obtaining and feeding back the first data. The construction granularity of the index entry is a physical block and a logic block, and the data volume of the compressed data does not need to be recorded, so that the complexity of data indexing is effectively reduced.

Methods, systems, and devices for zoned random write operations are described. A memory system may receive a set of write commands associated with respective logical block addresses (LBAs) that may be in a sequential order, where the respective LBAs may be associated with a zone. The memory system may write first data to a first physical block address (PBA), where the first data may be associated with a first LBA of the respective LBAs. The memory system may determine whether a second LBA associated with second data is sequential relative to a write pointer associated with the zone. The memory system may write the second data to a second PBA that may be sequential to the first PBA in response to determining that the second logical block address is non-sequential relative to the write pointer and on a value of a bitmap corresponding to the second LBA.

The invention discloses a mapping table storage method and device, computer equipment and a storage medium, and relates to the technical field of data storage, and the method comprises the following steps: determining a target logic block group corresponding to a target mapping entry and a preset attribute of the target logic block group; and if the preset attribute is a first preset value, writing the target mapping entry into a first preset cache space, screening the target mapping entry and other mapping entries according to the writing sequence of the target mapping entry and the writing sequence of other mapping entries, and storing the screened mapping entries into a flash memory. The problem that in the process of brushing an L2P mapping table to a flash memory, invalid mapping entries are written into the flash memory as well, and consequently bandwidth and storage resources are wasted can be solved. According to the method, the mapping entries are screened, only the screened mapping entries are stored in the flash memory, invalid mapping entries are successfully reduced, and in the process of storing the mapping table in the flash memory, bandwidth occupation is reduced, and the space occupied by the mapping table in the flash memory is reduced.

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

The invention relates to the technical field of intelligent chips, in particular to an NAND wear leveling method based on integrated circuit ECC (error correction code) and read delay, which comprises the following steps: acquiring read delay data and error correction code usage amount of a three-layer unit page of a target block in an NAND flash memory chip; on the basis of the read delay increment and the error correction code increment of the middle-layer page, the health index of the target block is calculated by combining the read delay difference value of the middle-layer page and the lower-layer page, the target block is divided into a plurality of health levels, and logic blocks of different health levels are mapped to different physical planes of the NAND flash memory chip; synchronously executing data migration and erasure operations of the plurality of blocks to be migrated by utilizing the parallel erasure capability of the multi-plane architecture for the target block of which the health level is degraded to a preset threshold value; and monitoring the deviation degree between the current read delay and the specification read delay in real time, and selecting the error correction strength grade of the error correction code according to the deviation degree.

A system for autonomous compliance with legal regulations in smart contracts; the system includes: a regulatory data collection unit comprising a network interface controller physically connected to an external communications port, a hardware-based public key infrastructure circuit configured to validate digital certificates of regulatory servers, and a direct memory access controller configured to transfer authenticated regulatory update packets from the network interface controller to a volatile buffer memory without processor intervention; a Compliance Code Conversion Unit with a hardware lexicon scanner implemented as a finite state machine and embedded in reconfigurable FPGA logic blocks, a microcontroller executing a hardware-based lexical analysis pipeline stored in firmware registers, and a translation cache memory configured to temporarily store tokenized compliance rules before writing them to a non-volatile instruction memory; a policy evaluation and enforcement unit comprising a transaction verification processor connected to a secure enclave memory, a hardware comparator circuit configured to compare transaction parameters with compliance thresholds stored in the secure enclave memory, and a logic gate circuit configured to generate execution gate signals that selectively allow, block, or modify smart contract execution signals transmitted to a blockchain execution processor; and an audit logging unit with a cryptographic hashing circuit configured to generate block hashes of enforcement records, a timestamp oscillator configured to generate temporal signatures of compliance enforcement actions, and a Merkle tree generation circuit configured to create tamper-proof hierarchical hash structures, with the enforcement records being passed to a decentralized storage interface for anchoring in the chain or distributed ledger.

A method for data transmission is provided. The method includes, at an initiator computing device, receiving a data payload to be transmitted to a target computing device for storage using the nonvolatile memory express over fabric (NVMe-oF) protocol, wherein the data payload is represented as a plurality of logical blocks. Using a compression engine, the data payload is compressed into a plurality of physical blocks having a smaller total data size than the plurality of logical blocks. A write request is transmitted to the target computing device, the write request including the plurality of physical blocks, and metadata specifying a correspondence between each logical block of the plurality of logical blocks and one or more corresponding physical blocks of the plurality of physical blocks.

Systems and methods for a new field programmable gate array (FPGA) architecture that is optimized for machine learning (ML) applications are provided. Such ML applications can specifically include, for example, artificial neural networks and deep neural networks. Various embodiments enable the design of faster and more power efficient hardware accelerators for machine learning algorithms, compared to existing FPGAs in the market. This is made possible by hard systolic matrix multiplier blocks, hard activation blocks and soft ML-centric configurable logic blocks. The matrix multiplier blocks are connected to field programmable interconnect resources to enable creation of larger matrix multipliers. The hard matrix multipliers and the hard activation blocks have programmable interconnects between them and neighboring memory or compute blocks on the device.

Providing adaptive and dynamic redundancy for functional safety in processor devices is disclosed herein. In some aspects, a processor device comprises a central configurable redundancy logic block (CRLB) controller circuit, a redundancy map matrix switch circuit, a plurality of safety-critical block circuits, and a plurality of CRLB clusters. The central CRLB controller circuit receives redundancy mapping data for each safety-critical block circuit, and receives an indication of one or more active block circuits among the safety-critical block circuits. The central CRLB controller circuit transmits the redundancy mapping data corresponding to the active block circuits to the redundancy map matrix switch circuit, which configures one or more CRLB clusters to duplicate functionality of the respective active block circuits based on the redundancy mapping data. The redundancy map matrix switch circuit then provides logic redundancy for the one or more active block circuits using the one or more CRLB clusters.

The invention relates to the technical field of automatic generation of low-code components, and discloses an automatic component generation method for a low-code platform. The method comprises the following steps: acquiring and standardizing an original interaction event stream of a user on a canvas to form a user operation chain; and scanning and marking a composite operation unit conforming to a predefined structure on the operation chain, and carrying out dynamic weight distribution according to the spatial layout and the time decay attribute of the composite operation unit. And combining the similar units with similar weights to form candidate component logic blocks. And extracting an interface element dependency relationship of the logic block to construct a dependency graph, and calculating cohesiveness measurement of the logic block based on graph node characteristics. Bridging operations connecting different logic blocks are identified and analyzed, and coupling metrics therebetween are calculated. And fusing cohesiveness and coupling measurement to generate a componentized evaluation matrix. And analyzing the matrix and driving a code template engine, and automatically synthesizing a final visual component. According to the invention, intelligent generation from user interaction to high-quality, high-cohesion and low-coupling components is realized.

The invention relates to the technical field of integrated circuits, and discloses a programmable logic block test method, system and device and a field programmable gate array. The programmable logic block is a composition unit of the field programmable gate array. Firstly, based on a constraint file, each programmable logic block in a plurality of programmable logic blocks is configured as a vector generation module, a to-be-detected module or a result detection and comparison module, and at least one module combination is obtained. Then, for each module combination, generating an excitation signal through at least one vector generation module, and sending the excitation signal to at least two to-be-tested modules; then, at least two to-be-tested modules execute test operation according to the received excitation signals to generate at least two to-be-tested results, and the to-be-tested results are sent to at least one result detection and comparison module; and finally, comparing the at least two to-be-tested results through at least one result detection and comparison module to obtain a function test result of the programmable logic block.

A method is described. The method includes constructing a bitmap having a first dimension organized into bins of logical block addresses (LBA bins) and a second dimension organized into bins of physical block addresses (PBA bins). Coordinates of the bitmap indicate whether respective physical blocks of non volatile memory within one or more SSDs that fall within a particular PBA bin are being mapped to by an LBA that falls within a particular one of the LBA bins. The method includes using the bitmap during a rebuild of an LBA bin of an LBA / PBA table to avoid reading meta data for physical blocks that are not mapped to by an LBA that falls within the LBA bin.

The invention discloses a storage control method and storage equipment, relates to the technical field of storage, and aims to solve the problem of how to improve data processing efficiency. The storage control method comprises the steps that in response to a control instruction, a source physical block address corresponding to a source logic block address contained in the control instruction is obtained by querying a mapping table; the mapping table stores a mapping relationship between each logical block address and each physical block address. And modifying a target physical block address corresponding to the target logic block address in the mapping table into a source physical block address corresponding to the source logic block address. Therefore, on the host side, the to-be-processed data corresponding to the source physical block address is migrated to the target physical block address. The to-be-processed data is not transmitted between the host and the storage device, so that the data processing efficiency is improved.

In some implementations, a memory apparatus may receive a command indicating a logical block address (LBA) that is associated with a logical-to-physical (L2P) table. The memory apparatus may perform a lookup operation associated with a compressed version of an address range of the L2P table to identify a physical address in non-volatile memory associated with the LBA, wherein the compressed version is stored in a volatile memory of the memory apparatus, wherein the compressed version is associated with an exception list that indicates physical addresses for respective LBAs, included in the address range, that are associated with non-sequential physical addresses, and wherein the compressed version is associated with a binary tree that indicates locations in the exception list associated with the respective LBAs. The memory apparatus may perform, based on the command, an action associated with the physical address.

This invention discloses a security chip based on a configurable lookup table. The security chip includes: at least one configurable logic block, each containing at least one configurable lookup table unit; a dynamic mask generator connected to the configurable lookup table unit, dynamically generating a mask sequence according to the current processing clock cycle; a reconfiguration controller connected to the dynamic mask generator, changing the configuration values ​​of the configurable lookup table units in real time according to a security policy; and a security execution engine, whose input is connected to the output of the configurable lookup table unit, performing secure operations based on the masked lookup results; wherein the configurable lookup table unit presents different truth table mappings for the same logic input in at least two different clock cycles. This invention enables the lookup table unit to present different truth table mappings in different clock cycles, breaking the deterministic correlation between power consumption characteristics and data, and effectively resisting side-channel attacks such as differential power analysis.

The invention provides a visual logic execution system and method based on logic block nesting and JSON (JavaScript Object Notation) dynamic configuration, and the system comprises a front-end visual editing module which is used for providing a logic block library and a nested canvas editor, receiving the dragging and nesting operation of a user based on a logic block, and storing the dragging and nesting operation in the front-end visual editing module; serializing the finally edited nested logic tree structure into JSON (JavaScript Object Notation) configuration data; the back-end dynamic analysis execution module is used for receiving and persisting the JSON configuration data, constructing an executable object tree isomorphic to the nested logic tree structure by dynamically analyzing the JSON configuration data, and executing the executable object tree to run logic edited by a user; and the front-end visual editing module communicates with the rear-end dynamic analysis execution module through a data transmission interface. The front end and the rear end are coupled through the JSON interface, and the front end and the rear end can be independently upgraded and expanded.

Disclosed are predecoders and structures including the predecoders. Each predecoder includes, among other components, first and second latches controlled by write and read clock signals, respectively, and a multiplexer-enabled write logic bypass path. During a write, an address signal is latched by the first latch and propagated through logic downstream of the first latch (including through a write logic block) to the second latch (which is transparent). During a read, the write logic bypass path is activated so the address signal bypasses the first latch and the write logic block and is instead propagated only through logic downstream of the write logic block to the second latch (which periodically latches the received signal). In both operations, a predecoded address signal is output but, due to activation of the write logic bypass path during the read, the time between receiving the address signal and outputting the predecoded address signal is reduced.

This document describes clock monitoring for storage devices. Clock signals from those components (e.g., logic blocks) of the storage devices identified as causing failures in other components can be selectively monitored. This eliminates the need to monitor all components, which may be unnecessary if at least one section of the components is not fully utilized while the storage devices are operating in an autonomous mode.

A memory control unit of a memory device includes at least one hardware processor; and memory storing instructions that cause the at least one hardware processor to perform operations comprising: generating a scrambler seed and a logical block address (LBA) for a block of write data received by the memory control unit from a host device; generating a flash translation layer (FTL) to map the LBA to a physical address (PA); scrambling the block of data using the scrambler seed; encrypting the scrambler seed, the LBA, and the PA in the FTL using an encryption key; initiating writing a scrambled block of data and encrypted LBA and scrambler seed to a memory array; and decrypting the FTL using an incorrect encryption key in response to an erase command received by the memory control unit from the host device.

A data compression method and a related device, used for reducing I / O overhead. The data compression method comprises: acquiring attribute information of a logic block, wherein the logic block comprises a plurality of data pages, and the attribute information indicates data sizes of data contained in the plurality of data pages across a plurality of time periods; if the attribute information indicates that the total data size of the data contained in the plurality of data pages during a target time period is greater than or equal to a first threshold, compressing the data contained in the logic block, and storing the result obtained by compression, wherein the target time period includes at least time period among the plurality of time periods, and the time interval between the target time period and the current moment is greater than or equal to a time threshold; and if the attribute information indicates that the total data size of the data contained in the plurality of data pages during the target time period is less than the first threshold, determining not to compress the data contained in the logic block.

A memory sub-system, having: a host interface configured to operate on a computer bus; non-volatile memory cells; and a controller. In response to a command to identify information about the memory sub-system, the controller is to provide structured data indicating that the memory sub-system supports sub block access and specifying a sub block granularity level for the sub block access. In response to an access command with a sub block descriptor embedded within the access command, the controller is to determine, based on the sub block descriptor provided within the access command, a portion of a logical block identified by the access command and implemented using a subset of the non-volatile memory cells. An operation is performed on the portion of the logical block according to an opcode specified by the access command.

An input / output (I / O) erase request directed at memory devices is received by a processing device. The erase request includes logical block address that is associated with a data object. The memory devices include groups of zones corresponding to sequential logical addresses. The plurality of zones are associated with a compound data object that includes a plurality of data objects, including the data object. One or more zones associated with the data object are identified. A data set counter associated with each of the one or more zones is decremented. The data set counter represents a number of sets of data associated with the zone. Responsive to determining that the data set counter associated with one of the one or more ones satisfies a criterion, the one of the one or more zones is a caused to be erased.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a logic block and a p-bit block. The logic block includes a plurality of plurality of logic elements. The p-bit block includes a transistor, a first bit cell with a magnetic structure and at least one second bit cell with a resistance structure. The first bit cell with the magnetic structure is connected to one end of the transistor. The at least one second bit cell with the resistance structure is connected to another end of the transistor.