221 results about "Nand flash memory" patented technology

The invention discloses a large language model accelerator architecture based on a three-dimensional NAND flash memory, and belongs to the technical field of calculation, reckoning or counting. The architecture comprises a three-dimensional NAND flash memory used for executing feedforward neural network calculation; the auxiliary calculation unit is used for executing attention mechanism calculation; the DRAM chip is used for storing attention mechanism related weights and KV cache; and the interconnection resource is used for realizing data interaction among the components. Wherein the three-dimensional NAND flash memory comprises a logic chip and an NAND array chip, the logic chip is used for controlling and executing calculation, and the NAND array chip is used for storing weights and participating in calculation. The invention further provides a scheduling method based on KV cache awareness. The scheduling method comprises decomposition and dynamic allocation of calculation tasks. Through collaborative design of the hardware architecture and the scheduling method, the memory wall bottleneck in large language model calculation can be relieved, the energy consumption is reduced, and the overall calculation performance is improved.

Disclosed are a memory device and a control method thereof. The memory device may be a high-capacity and high-performance three-dimensional NAND flash memory. The control method includes the following steps. Data for performing a programming operation on a specific memory cell area is obtained. A number of memory cells in a predetermined potential state in the data are counted as a first number value. The programming operation is performed on the specific memory cell area based on the data. A read operation is performed based on a reference voltage corresponding to the predetermined potential state. A number of memory cells in the predetermined potential state in the specific memory cell area after the programming operation are counted as a second number value. Whether the specific memory cell area has program disturbances is determined based on the first number value and the second number value.

The invention discloses a dormancy and awakening system and method of an enterprise-level solid state disk, and belongs to the technical field of power consumption management of the enterprise-level solid state disk. According to the system, a nonvolatile cache unit, an independent hardware state machine and an ultra-low power consumption wake-up detection circuit are integrated in a main controller. When entering the dormancy state, key data such as an FTL mapping table are stored in a nonvolatile cache, then the power management module cuts off power supply to the NAND flash memory and the main control core, and only the operation of the minimum circuit is maintained, so that the dormancy power consumption is reduced to be below 100mW; and during wakeup, the detection circuit identifies a physical layer signal to trigger rapid power-on, and the hardware state machine directly recovers the system state from the cache and bypasses the software initialization process, so that wakeup is completed and the NAND access capability is reconstructed within 1ms, and the industrial problem that ultra-low power consumption and rapid wakeup cannot be considered at the same time is effectively solved.

The invention discloses an NAND block health degree prediction method and system based on read interference perception. The method comprises the steps that read interference event counts of an NAND flash memory block are collected in real time; dynamically triggering multi-dimensional parameter acquisition to generate multi-dimensional parameter data with timestamps; extracting a dynamic change rate, a distribution entropy value and a growth slope feature based on the multi-dimensional parameters, and generating a compression feature matrix; inputting the compressed feature matrix into a pre-trained graph neural network-Hamiltonian Monte Carlo hybrid model, outputting a health degree score and recording a low-confidence sample; based on the health degree score and the historical health degree attenuation trajectory, generating an early warning level signal through a dynamic threshold engine; executing a corresponding block maintenance strategy according to the early warning level, and recording strategy execution effect data; and model parameters are updated through knowledge distillation by utilizing a low-confidence sample and strategy execution effect data, so that level-by-level and cross-level health risks of the NAND flash memory based on read interference perception are truly and accurately reflected.

The invention provides a QLC NAND interference compensation control method and system, and the method comprises the steps: collecting adjacent unit voltage offset data of a target storage unit through an on-chip reference unit array integrated on a QLC NAND flash memory chip; performing feature extraction on the data to obtain interference feature parameters including at least one of voltage drift amplitude, drift rate and drift fluctuation frequency, and inputting the interference feature parameters into a pre-trained lightweight decision tree model to output an interference trend prediction result, a programming parameter optimization strategy is generated based on the result, the pulse width and the step voltage increment are optimized, meanwhile, fine adjustment of model parameters is triggered by collecting programming verification data after each time of optimization, dynamic accurate compensation of memory cell interference under the high write-in load of the QLC NAND flash memory is achieved, programming voltage drift is effectively restrained, and the reliability of the QLC NAND flash memory is improved. The adaptive capacity of the writing algorithm is improved, and the overall service life of the flash memory is prolonged.

The invention discloses a fast data protection method and device for SSD abnormal power failure, equipment and a medium, and relates to the field of SSDs, and the method comprises the steps: monitoring a power supply voltage, and generating an interrupt signal when the power supply voltage is lower than a preset threshold value; in response to the interrupt signal, turning off a power supply of a preset non-data path hardware module through the SSD controller; stopping scheduling all operation commands for the NAND flash memory through the SSD firmware, and emptying a data path in an NAND flash memory controller; writing the user data in the host write cache and the command information corresponding to the user data into a special physical address block reserved in the SSD in advance; after the SSD is powered on again, the address mapping table is recovered by scanning the write-in point in the NAND flash memory, the backup data and the command information in the special physical address block are read, and the backup data are written into the user data area according to the command information. According to the method, the key data backup time during abnormal power failure is shortened, the capacity requirement for the standby capacitor is reduced, and the problem that the cost is increased due to the fact that the backup time is too long is effectively solved.

The invention provides an NAND flash memory write-in distribution method of a solid state disk, which is used for dynamically determining an optimal block for data write-in by analyzing content characteristics and update frequency of data to be written in, evaluating health state of each block of a flash memory and establishing data repetition and update frequency indexes. According to the method, static or repetitive data can be assigned to blocks with low or medium health degree according to data characteristics, data with high updating frequency is preferentially written into the healthy blocks, and the health state and statistical information of the blocks are updated in each writing period, so that the service life of the non-volatile flash memory is prolonged, the non-uniform service life distribution of the blocks is improved, and the service life of the non-volatile flash memory is prolonged. And the balance of writing efficiency is maintained. In addition, through feature abstract comparison and hash value check, data characteristics can be accurately identified, and a reliable, dynamic and efficiency-optimized flash memory management effect is achieved.

The invention discloses a flash memory and near memory acceleration system of an end-side large language model, and belongs to the technical field of calculation, reckoning or counting. According to the system, a 3D NAND flash memory chip with near memory computing capability is adopted, and model weights and key value caches are uniformly stored in the flash memory. Storage-intensive operations involved in the big language model inference decoding stage are all completed in a logic layer of a flash memory, and an NPU only executes non-linear operations such as normalization and activation and residual connection; in the pre-filling stage, the NPU obtains weight and key value cache data from the flash memory and is used for completing all calculations. Redundant read-write is reduced through a flash memory page-level key value cache mapping mechanism; and meanwhile, attention head group parallel data stream optimization is provided, so that the parallelism of a decoding stage is improved. A discrete framework and a compact framework are further provided, and optimal configuration is automatically selected in combination with a design space exploration strategy. According to the method, the requirement of edge end large language model reasoning on the DRAM can be omitted, delay is reduced, throughput is improved, and system cost and power consumption are remarkably reduced.

The invention relates to the technical field of intelligent chips, and discloses an NAND flash memory reading threshold adjusting method and device based on temperature compensation. The method comprises the following steps: acquiring real-time temperature of a flash memory, and aligning the real-time temperature with corresponding read threshold data and timestamps to obtain an initial associated data set; segmenting according to a fixed window, and calculating a temperature change rate and a threshold value change amplitude; different threshold offset modes are divided through clustering and are stored in an associated manner; constructing a prediction model in combination with an error rate index; if the monitored temperature fluctuation exceeds a threshold value, the threshold value offset is predicted, and a correction parameter is calculated; correcting the initial threshold value to obtain a reading standard; generating a threshold set by fusing risk assessment and an offset mode; and verifying and screening reading thresholds with low error rates in batches to obtain optimized threshold configuration. According to the method, the reading threshold of the NAND flash memory can be dynamically and accurately adjusted under temperature fluctuation, and the use requirement of high reliability of storage equipment in a complex environment is met.

The present disclosure includes apparatuses, methods, and systems for a radiation sensor suite. In an example, a method can include calibrating a plurality of sensors of a sensor suite located on a non-volatile memory die and monitoring for a plurality of radiation events at each one of the plurality of sensors. In response to none of the plurality of sensors detecting a radiation event, the method can include the sensor suite continuing to monitor for the plurality of radiation events. In response to at least one of the plurality of radiation sensors detecting a radiation event, the method can include notifying a host of the radiation event and identifying a NAND flash memory array region affected and correcting the radiation event based on the radiation event and the NAND flash memory array region affected.

The invention discloses an SSD (Solid State Disk) garbage collection method and device with RAID (Redundant Array of Independent Disk) redundancy and a medium, and relates to the technical field of garbage collection, and the method comprises the following steps: in a garbage collection process, selecting a target NAND flash memory physical block of which the effective data volume meets a collection condition, copying the effective data to a new position, and updating address mapping; querying a first RAID block to which the target block belongs and all member block identifiers thereof according to a first mapping table and a second mapping table which record a mapping relationship between the NAND flash memory physical block and the RAID blocks; and recombining other blocks except the target block in the first RAID block into a second RAID block, recalculating and storing verification data for the second RAID block, synchronously updating the two mapping tables to reflect a new composition relationship, and finally erasing the target block. The physical block of the NAND flash memory is used as the minimum recovery unit to replace the traditional recovery mode taking the whole RAID block as the unit, and the block with the minimum effective data can be preferentially recovered, so that the effective data migration amount is remarkably reduced, the write amplification coefficient is reduced, the abrasion is reduced, and the service life of a hard disk is prolonged.

The invention discloses a flash memory error injection test method and electronic equipment, and relates to the technical field of error injection test.The flash memory error injection test method comprises the steps that by means of the inherent physical characteristic, namely, the write-in characteristic, of an NAND flash memory, different data are written in the same position of a target block in the flash memory at least twice, the number of free electrons of a floating gate of the flash memory is interfered from the physical level, and the number of the free electrons is increased; according to the method, the internal data error of the flash memory is caused, and a physical abnormal scene of the flash memory is constructed, so that the read-write error test of the flash memory is realized, a technician can conveniently and timely find out the problem exposed in the test process of the flash memory, and the fault risk after mass production is reduced.

Disclosed are a device for encryption and decryption and a method for processing data. The device may be implemented by a memory device with a three-dimensional NAND flash memory with high capacity and high performance. The device includes a memory array, a data-sensing circuit, and a memory controller. A memory block in the memory array includes a first memory string with a first bit-line and a second memory string with a second bit-line. The memory controller is configured to: obtain a codec key, wherein memory cells in a first memory sub-area are set according to the codec key, and memory cells in a second memory sub-area are programed according to a complementary codec key; generate bit-line voltages of the first and the second bit-lines according to an input data; bias the memory cells in the first and the second memory sub-areas; and, obtain an output data according to the data-sensing circuit.

The invention provides an operating method of a memory device and a memory device thereof. The memory device can be a three-dimensional NAND flash memory with high capacity and high performance. The operating method includes performing a program operation on the plurality of memory cells based on the i-th potential state. The programming operation based on the ith potential state comprises the following steps: in a programming pulse stage, applying a programming pulse corresponding to the ith potential state to a plurality of first storage units corresponding to the ith potential state; and, in a verification stage after the program pulse stage, performing a first sensing operation on the plurality of second memory cells in the (i-1)-th potential state to verify a threshold voltage distribution situation of the plurality of second memory cells, and performing a second sensing operation on the plurality of first memory cells to implement a program verification operation in the i-th potential state.

The present invention relates to an apparatus and method for generating a parameter page library for a NAND flash memory, and more particularly to an apparatus and method for generating a parameter page library for each memory chip by reading the parameter pages of the NAND flash memory in an environment where the internal controller of the NAND flash memory device is unavailable.

This invention relates to the field of smart chip technology, and discloses a method and apparatus for adjusting the read threshold of NAND flash memory based on temperature compensation. The method includes: acquiring real-time flash memory temperature and corresponding read threshold data, aligning timestamps to obtain an initial associated dataset; segmenting the dataset into fixed windows and calculating the temperature change rate and threshold change amplitude; dividing different threshold offset patterns through clustering and associating them with storage; constructing a prediction model based on an error rate index; monitoring temperature fluctuations and predicting the threshold offset if it exceeds the threshold, and calculating correction parameters; correcting the initial threshold to obtain the read standard; generating a threshold set by fusing risk assessment and offset patterns; and batch verifying and filtering read thresholds with low error rates to obtain an optimized threshold configuration. This method can achieve dynamic and precise adjustment of the NAND flash memory read threshold under temperature fluctuations, meeting the high reliability requirements of storage devices in complex environments.

The present invention relates to a method for recommending an optimal applied voltage for data extraction of a NAND flash memory. The method for recommending an optimal applied voltage for data extraction of a NAND flash memory according to one aspect of the present invention comprises: an initial data extraction step of applying a preset initial applied voltage to an input pin of a NAND flash memory, extracting data included in the NAND flash memory, and storing a logical address of the data; a per-voltage data extraction step of applying a plurality of voltages, obtained by repeatedly increasing or decreasing the initial applied voltage by a predetermined voltage, to the input pin of the NAND flash memory, each at different time points, and extracting, for each voltage, data having the same logical address as the logical address of the data extracted in the initial data extraction step; and a step of recommending an optimal applied voltage on the basis of binary data generated by performing an XOR operation between data having the same logical address extracted according to different applied voltages.

A card controller (22) observes the access history of accessing an SD card (20) by a host device (10). The card controller (22) uses a pattern selector (41) to determine which of a plurality of patterns the observed access history corresponds to. The card controller (22) reads, from a register (31a), a control parameter associated with the determined pattern. The card controller (22) controls writing to and reading from a NAND flash memory (23) in accordance with the control parameter read from the register (31a). The access history includes at least a data size and an address.

An in-memory bitwise operation circuit and method thereof are provided. The circuit includes a memory array, storing page data each having strings; a page buffer, storing the strings and selecting a portion of the strings as operands; a pop-count counter, receiving the operands and an operator flag, counting the number of bit 1 at corresponding bit positions of the operands, and generating a bitwise operation result corresponding to the operator; a bitwise operation processing unit, receiving and temporally storing the bitwise operation result, and outputting a final bitwise operation result when receiving a final result flag. In case that the operator is a last operator, the bitwise operation result is output as the final bitwise operation result. The circuit and method are suitable for 3D NAND flash memory that has high capacity and high performance.

An in-memory bitwise operation circuit and method thereof are provided. The circuit includes a memory array, storing page data each having strings; a page buffer, storing the strings and selecting a portion of the strings as operands; a pop-count counter, receiving the operands and an operator flag, counting the number of bit 1 at corresponding bit positions of the operands, and generating a bitwise operation result corresponding to the operator; a bitwise operation processing unit, receiving and temporally storing the bitwise operation result, and outputting a final bitwise operation result when receiving a final result flag. In case that the operator is a last operator, the bitwise operation result is output as the final bitwise operation result. The circuit and method are suitable for 3D NAND flash memory that has high capacity and high performance.

A method of operating a NAND flash memory of a host device includes: detecting a temporary failure of a first NAND block of a plurality of NAND blocks; in response to the detected temporary fault of the first NAND block, determining a fault verification parameter of the first NAND block; assigning the first NAND block to a temporary bad block (TBB) list based on a fault verification parameter and a number of sets of the plurality of NAND blocks assigned to the TBB list; and determining that the NAND flash memory fails when the number of the sets allocated to the TBB list in the plurality of NAND blocks is greater than or equal to a threshold number of NAND blocks.

The application discloses a NAND flash memory block screening method and device, equipment and a storage medium, and relates to the technical field of disc testing. The method comprises the following steps: obtaining operation feedback parameters corresponding to blocks in which write-read operations are successful in a NAND flash memory by performing RDT testing on the NAND flash memory; obtaining block screening conditions containing block screening indexes; and screening target blocks with high performance from the blocks in which the write-read operations are successful according to the operation feedback parameters and the block screening conditions. It can be seen that, based on the operation feedback parameters fed back after the blocks are executed write-read operations, the target blocks with high performance are screened from the blocks in which the write-read operations are successful by using the block screening conditions, that is, the blocks with high performance are screened from the blocks in which the write-read operations are successful based on the blocks in which the write-read operations are successful, and the target blocks with high performance are provided for users to use, so that the requirement of the users for high performance and high reliability of the disc can be met under the premise of guaranteeing the reliability of the disc.

The application provides a channel parameter management method and device, electronic equipment and storage medium, belonging to the technical field of solid state disks, comprising: monitoring the bit error rate of a NAND flash memory; adjusting the step size of frequency scanning according to the bit error rate; writing first data to the NAND flash memory at a first frequency and reading the first data from the NAND flash memory at a second frequency; if the first data is written incorrectly, determining that the write data path of the NAND flash memory is faulty; adjusting the drive strength of the NAND flash memory, the terminal resistance of the NAND flash memory and the write delay clock of the controller of the solid state disk in sequence based on the bit error rate; writing second data to the NAND flash memory at the second frequency and reading the second data from the NAND flash memory at the first frequency; if the second data is read incorrectly, determining that the read data path of the NAND flash memory is faulty; adjusting the terminal resistance of the NAND flash memory, the reference voltage of the controller of the solid state disk and the sampling delay of the controller of the solid state disk in sequence based on the bit error rate. The read and write data path faults can be automatically distinguished and parameter collaborative management can be performed.

A 3D memory device including a stacked structure, a first group of channel structures and a second group of channel structures, a partition structure and at least one support structure is provided. The stacked structure includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A top surface of the stacked structure is parallel to a plane defined by a first direction and a second direction. The first group of channel structures and the second group of channel structures penetrate the stacked structure and are arranged along a first direction. The partition structure includes a plurality of discrete partition structures and is disposed between the first group of channel structures and the second group of channel structures. The plurality of discrete partition structures are arranged along the second direction and penetrate the stacked structure. At least one support structure is disposed between the adjacent discrete partition structures. The 3D memory device is a 3D NAND flash memory device with high capacity and performance.

The application discloses a three-dimensional ferroelectric memory array and a preparation method and an operating method thereof, and belongs to the technical field of microelectronics and integrated circuits. The three-dimensional ferroelectric memory array comprises memory cells which are arranged in a vertical direction and a horizontal direction on a substrate, and each memory cell comprises, from left to right or from right to left in the horizontal direction, a gate metal layer, a first isolation layer, a ferroelectric material layer, a floating gate metal layer, a second isolation layer and a channel layer. The application adds the floating gate metal layer in the ferroelectric NAND Flash memory, can homogenize the electric field distribution between the ferroelectric material layer and the channel layer, reduces the local electric field change caused by the non-ferroelectric phase, effectively shields the influence of the non-ferroelectric phase in the ferroelectric material layer on the threshold voltage, reduces the fluctuation of the threshold voltage, and increases the stored logic states.

Systems, methods, and apparatus related to controlling media scan in memory devices. In one approach, a controller manages a media scanning process for a memory (e.g., NAND flash memory) as a function of temperature. The controller collects temperature data from one or more sensors of the memory. Using the collected temperature data, the controller determines a moving average temperature. Based on the moving average temperature, the controller updates a frequency of the media scanning process.

The invention relates to the technical field of 3D NAND flash memories, and discloses a pre-reading processing method, device and equipment of a 3D NAND flash memory and a medium, and the method comprises the following steps: monitoring vertical stacking structure characteristics of the 3D NAND flash memory in real time, and analyzing a data access mode of the 3D NAND flash memory to obtain structure access data; acquiring a plane number field of a physical address in the access demand, and detecting whether data access is in the same plane according to the plane number field; if the data access is not in the same plane, predicting a cross-layer conflict according to the activation state of the adjacent plane and historical load data to obtain a conflict prediction result; and processing a pre-reading task according to the structure access data and the conflict prediction result. According to the invention, the pre-reading efficiency of the 3D NAND is effectively improved.

The invention provides an automatic test method and device for an NAND flash memory, equipment and a medium, and relates to the technical field of flash memory testing, and the method comprises the steps: obtaining a target test script of the NAND flash memory to be tested; if the structure of the root node of the target test script is an ordered command chain, extracting a first command from the root node as a target command; detecting whether the structure of the target command is a dictionary; when the structure of the target command is a dictionary, analyzing the target command to obtain target configuration information; matching a target processing function corresponding to the target configuration information from a comparison table of different configured target configuration information and different processing functions; generating a test instruction corresponding to the target command based on the target processing function; and obtaining a test result of the NAND flash memory to be tested until test instructions corresponding to all commands in the root node are generated. The test efficiency can be improved, and the test compiling difficulty can be reduced.

In one aspect, a transistor structure for a vertical NAND flash memory device is provided. The transistor structure includes a semiconductor channel layer, a first auxiliary layer and a second auxiliary layer arranged on opposite sides of the semiconductor channel layer along a first axis, and each of the first auxiliary layer and the second auxiliary layer comprises a first material having a first relative permittivity greater than 1 and less than 3.9. The transistor structure further includes a first dielectric layer arranged above the semiconductor channel layer, the first auxiliary layer and the first auxiliary layer along a second axis that is perpendicular to the first axis; a charge storage layer arranged on the first dielectric layer; a second dielectric layer arranged on the charge storage layer; and a gate layer arranged on the second dielectric layer.

The present invention provides a NAND flash memory remapping device and a NAND flash memory remapping method that maximize the utilization of internal memory bandwidth, reduce power consumption, and shorten processing delay time. [Solution] An access frequency-based NAND flash memory remapping device 100 according to one embodiment of the present invention includes: a data access frequency analysis unit that analyzes the access frequency to a memory area in which at least one target piece of information is stored; a data remapping unit that constructs a page containing the target information based on the analyzed access frequency; and a page buffer that stores the constructed page and loads it when an access request is made.