306 results about "Nand flash memory" patented technology

The invention discloses a large language model accelerator architecture based on a three-dimensional NAND flash memory, and belongs to the technical field of calculation, reckoning or counting. The architecture comprises a three-dimensional NAND flash memory used for executing feedforward neural network calculation; the auxiliary calculation unit is used for executing attention mechanism calculation; the DRAM chip is used for storing attention mechanism related weights and KV cache; and the interconnection resource is used for realizing data interaction among the components. Wherein the three-dimensional NAND flash memory comprises a logic chip and an NAND array chip, the logic chip is used for controlling and executing calculation, and the NAND array chip is used for storing weights and participating in calculation. The invention further provides a scheduling method based on KV cache awareness. The scheduling method comprises decomposition and dynamic allocation of calculation tasks. Through collaborative design of the hardware architecture and the scheduling method, the memory wall bottleneck in large language model calculation can be relieved, the energy consumption is reduced, and the overall calculation performance is improved.

Disclosed are a memory device and a control method thereof. The memory device may be a high-capacity and high-performance three-dimensional NAND flash memory. The control method includes the following steps. Data for performing a programming operation on a specific memory cell area is obtained. A number of memory cells in a predetermined potential state in the data are counted as a first number value. The programming operation is performed on the specific memory cell area based on the data. A read operation is performed based on a reference voltage corresponding to the predetermined potential state. A number of memory cells in the predetermined potential state in the specific memory cell area after the programming operation are counted as a second number value. Whether the specific memory cell area has program disturbances is determined based on the first number value and the second number value.

The invention provides a method and system for optimizing reading reference voltage of a three-dimensional NAND flash memory, and relates to the technical field of semiconductor memorizes.The method comprises the steps that the erasing frequency and the data retention time of the three-dimensional NAND flash memory are obtained; if the data retention time is not clear, inversely deducing the time through a sampling adjustment method, inputting the inversely deduced data retention time and erasing times into an optimal read reference voltage prediction model, and outputting an average optimal offset value of each read reference voltage; if so, substituting the two parameters into an optimal read reference voltage prediction model to output an average optimal offset value of each read reference voltage; and finally, compensating the average optimal offset value of each read reference voltage by using the interlayer difference table, and outputting all optimal read reference voltages of each layer. According to the method and the device, the accuracy of reading reference voltage optimization strategy prediction can be improved, the time overhead is reduced, and the reading performance is improved.

The invention discloses a dormancy and awakening system and method of an enterprise-level solid state disk, and belongs to the technical field of power consumption management of the enterprise-level solid state disk. According to the system, a nonvolatile cache unit, an independent hardware state machine and an ultra-low power consumption wake-up detection circuit are integrated in a main controller. When entering the dormancy state, key data such as an FTL mapping table are stored in a nonvolatile cache, then the power management module cuts off power supply to the NAND flash memory and the main control core, and only the operation of the minimum circuit is maintained, so that the dormancy power consumption is reduced to be below 100mW; and during wakeup, the detection circuit identifies a physical layer signal to trigger rapid power-on, and the hardware state machine directly recovers the system state from the cache and bypasses the software initialization process, so that wakeup is completed and the NAND access capability is reconstructed within 1ms, and the industrial problem that ultra-low power consumption and rapid wakeup cannot be considered at the same time is effectively solved.

The invention discloses an NAND flash memory reading voltage axis dynamic prediction method and device and a storage medium, and the method comprises the steps: selecting sample data covering different types of NAND flash memories, and carrying out the training, and obtaining a GRUM model; taking PE times, RET time and VTH distribution in the sample data as the input of a GRUM model, and taking the output of the GRUM model as an optimal reading voltage axis prediction value; maintaining a weight matrix of the trained GRUM model as a base weight; taking the normalized PE times and VTH distribution as input features, taking the dimensionality-reduced weight adjustment amount as output, and constructing and training a polynomial regression model; and loading the target weight to the GRUM model to predict the optimal reading voltage of the NAND flash memory to be processed. According to the method, the output dimension of a subsequent polynomial regression model is reduced, calculation and storage burdens are reduced, meanwhile, invalid weight files are removed, and the resource utilization efficiency is further improved.

The invention discloses an NAND block health degree prediction method and system based on read interference perception. The method comprises the steps that read interference event counts of an NAND flash memory block are collected in real time; dynamically triggering multi-dimensional parameter acquisition to generate multi-dimensional parameter data with timestamps; extracting a dynamic change rate, a distribution entropy value and a growth slope feature based on the multi-dimensional parameters, and generating a compression feature matrix; inputting the compressed feature matrix into a pre-trained graph neural network-Hamiltonian Monte Carlo hybrid model, outputting a health degree score and recording a low-confidence sample; based on the health degree score and the historical health degree attenuation trajectory, generating an early warning level signal through a dynamic threshold engine; executing a corresponding block maintenance strategy according to the early warning level, and recording strategy execution effect data; and model parameters are updated through knowledge distillation by utilizing a low-confidence sample and strategy execution effect data, so that level-by-level and cross-level health risks of the NAND flash memory based on read interference perception are truly and accurately reflected.

The invention provides a QLC NAND interference compensation control method and system, and the method comprises the steps: collecting adjacent unit voltage offset data of a target storage unit through an on-chip reference unit array integrated on a QLC NAND flash memory chip; performing feature extraction on the data to obtain interference feature parameters including at least one of voltage drift amplitude, drift rate and drift fluctuation frequency, and inputting the interference feature parameters into a pre-trained lightweight decision tree model to output an interference trend prediction result, a programming parameter optimization strategy is generated based on the result, the pulse width and the step voltage increment are optimized, meanwhile, fine adjustment of model parameters is triggered by collecting programming verification data after each time of optimization, dynamic accurate compensation of memory cell interference under the high write-in load of the QLC NAND flash memory is achieved, programming voltage drift is effectively restrained, and the reliability of the QLC NAND flash memory is improved. The adaptive capacity of the writing algorithm is improved, and the overall service life of the flash memory is prolonged.

The invention relates to the technical field of data backup, and discloses an iOS device data backup and recovery method and system, and the method comprises the steps: carrying out the SSL certificate verification and EscrowBag key authentication of an iOS device, and obtaining a data path list; according to the data path list, parallel scanning of APFS file system B-Tree traversal, NAND flash memory page reading and SQLite WAL log analysis is carried out on the iOS device storage partition, and an original data set is obtained; performing integrity evaluation based on the original data set to obtain an effective data set and constructing a virtual file index; the data selection list of the user is confirmed based on the virtual file index, safety recovery is executed, and a data recovery result is returned. The SQLite page Cell reconstruction and fragment file signature matching technology is combined, intelligent repair and quality prediction can be conducted on damaged data, the user experience and operation efficiency are improved, and the user experience is improved. And the security and the reliability in the data recovery process are ensured.

The invention discloses a fast data protection method and device for SSD abnormal power failure, equipment and a medium, and relates to the field of SSDs, and the method comprises the steps: monitoring a power supply voltage, and generating an interrupt signal when the power supply voltage is lower than a preset threshold value; in response to the interrupt signal, turning off a power supply of a preset non-data path hardware module through the SSD controller; stopping scheduling all operation commands for the NAND flash memory through the SSD firmware, and emptying a data path in an NAND flash memory controller; writing the user data in the host write cache and the command information corresponding to the user data into a special physical address block reserved in the SSD in advance; after the SSD is powered on again, the address mapping table is recovered by scanning the write-in point in the NAND flash memory, the backup data and the command information in the special physical address block are read, and the backup data are written into the user data area according to the command information. According to the method, the key data backup time during abnormal power failure is shortened, the capacity requirement for the standby capacitor is reduced, and the problem that the cost is increased due to the fact that the backup time is too long is effectively solved.

The invention provides an NAND flash memory write-in distribution method of a solid state disk, which is used for dynamically determining an optimal block for data write-in by analyzing content characteristics and update frequency of data to be written in, evaluating health state of each block of a flash memory and establishing data repetition and update frequency indexes. According to the method, static or repetitive data can be assigned to blocks with low or medium health degree according to data characteristics, data with high updating frequency is preferentially written into the healthy blocks, and the health state and statistical information of the blocks are updated in each writing period, so that the service life of the non-volatile flash memory is prolonged, the non-uniform service life distribution of the blocks is improved, and the service life of the non-volatile flash memory is prolonged. And the balance of writing efficiency is maintained. In addition, through feature abstract comparison and hash value check, data characteristics can be accurately identified, and a reliable, dynamic and efficiency-optimized flash memory management effect is achieved.

The invention provides an LDPC (Low Density Parity Check) correction method and system for an error interval of an NAND flash memory, and the method comprises the steps: recognizing an abnormal interval expansion trend of the NAND flash memory, recognizing an error code interval according to a data writing task of the flash memory, and judging whether an error code occurs in an interval, in which data is stored, in the flash memory or not; adjusting the LDPC correction of the flash memory according to the error code interval and the reading quality of data received by the flash memory, and adjusting the return state of a data reading result according to the execution state of the LDPC correction to ensure that the read return data is correct; according to information that LDPC correction is not completed in the power-on process of the flash memory, an LDPC correction guide is generated, and the LDPC correction operation on the flash memory is adjusted according to a task instruction received after the flash memory is powered on again, so that all error code intervals in the flash memory are effectively corrected, the intervals with data errors in the flash memory are prevented from being continuously increased and accumulated, and the error correction efficiency of the flash memory is improved. The overall data storage reliability of the NAND flash memory is improved, and the data reading / writing correctness of the NAND flash memory is ensured.

The invention discloses a method for optimizing ECC (Error Correction Code) protection strength of an NAND FLASH in-memory computing system for an LLM inference chip, and belongs to the technical field of computing, reckoning or counting. Based on an NAND FLASH in-memory computing architecture, the invention provides a self-adaptive sub-plane protection strategy based on a Hamming code, and an error sensitivity grading model of sign bits, index bits and mantissa bits is established by analyzing BF16 numerical value distribution characteristics of large language model weight data; in combination with a residual connection structure of a Transform decoding layer, inter-layer cosine similarity is calculated to evaluate layer importance; and dynamically adjusting the Hamming code protection granularity by adopting a greedy algorithm, and carrying out iterative optimization according to a simulation error injection result until the model confusion degree and the accuracy meet threshold values. And performing ECC software and hardware collaborative design according to an iteration result of the greedy algorithm to obtain an ECC circuit required to be configured by each plane of the NAND flash memory. According to the method, the circuit area power consumption is remarkably reduced while the model reasoning precision is ensured, the ECC bandwidth requirement is reduced, and the large model reasoning efficiency and reliability are remarkably improved.

Disclosed are a memory device and a control method thereof. The memory device may be a high-capacity and high-performance three-dimensional NAND flash memory. The control method includes the following steps. Data for performing a programming operation on a specific memory cell area is obtained. A number of memory cells in a predetermined potential state in the data are counted as a first number value. The programming operation is performed on the specific memory cell area based on the data. A read operation is performed based on a reference voltage corresponding to the predetermined potential state. A number of memory cells in the predetermined potential state in the specific memory cell area after the programming operation are counted as a second number value. Whether the specific memory cell area has program disturbances is determined based on the first number value and the second number value.

A flash memory device includes a cell array and a control circuit. The cell array includes a first NAND string having first flash memory cells having control gates respectively connected to word lines, and a first bit line selection switch connecting the first flash memory cells to a first bit line according to a control of a first string selection line. The control circuit controls a first erase operation for erasing a selected flash memory cell. The control circuit controls a voltage difference between the first bit line and the first string selection line to have a first value for generating gate induced drain leakage (GIDL) at the first bit line selection switch, and controls a voltage of a control gate of the selected flash memory cell and a voltage of a control gate of an unselected flash memory cell to be different from each other.

The invention discloses a flash memory and near memory acceleration system of an end-side large language model, and belongs to the technical field of calculation, reckoning or counting. According to the system, a 3D NAND flash memory chip with near memory computing capability is adopted, and model weights and key value caches are uniformly stored in the flash memory. Storage-intensive operations involved in the big language model inference decoding stage are all completed in a logic layer of a flash memory, and an NPU only executes non-linear operations such as normalization and activation and residual connection; in the pre-filling stage, the NPU obtains weight and key value cache data from the flash memory and is used for completing all calculations. Redundant read-write is reduced through a flash memory page-level key value cache mapping mechanism; and meanwhile, attention head group parallel data stream optimization is provided, so that the parallelism of a decoding stage is improved. A discrete framework and a compact framework are further provided, and optimal configuration is automatically selected in combination with a design space exploration strategy. According to the method, the requirement of edge end large language model reasoning on the DRAM can be omitted, delay is reduced, throughput is improved, and system cost and power consumption are remarkably reduced.

The invention relates to the technical field of intelligent chips, and discloses an NAND flash memory reading threshold adjusting method and device based on temperature compensation. The method comprises the following steps: acquiring real-time temperature of a flash memory, and aligning the real-time temperature with corresponding read threshold data and timestamps to obtain an initial associated data set; segmenting according to a fixed window, and calculating a temperature change rate and a threshold value change amplitude; different threshold offset modes are divided through clustering and are stored in an associated manner; constructing a prediction model in combination with an error rate index; if the monitored temperature fluctuation exceeds a threshold value, the threshold value offset is predicted, and a correction parameter is calculated; correcting the initial threshold value to obtain a reading standard; generating a threshold set by fusing risk assessment and an offset mode; and verifying and screening reading thresholds with low error rates in batches to obtain optimized threshold configuration. According to the method, the reading threshold of the NAND flash memory can be dynamically and accurately adjusted under temperature fluctuation, and the use requirement of high reliability of storage equipment in a complex environment is met.

The present disclosure includes apparatuses, methods, and systems for a radiation sensor suite. In an example, a method can include calibrating a plurality of sensors of a sensor suite located on a non-volatile memory die and monitoring for a plurality of radiation events at each one of the plurality of sensors. In response to none of the plurality of sensors detecting a radiation event, the method can include the sensor suite continuing to monitor for the plurality of radiation events. In response to at least one of the plurality of radiation sensors detecting a radiation event, the method can include notifying a host of the radiation event and identifying a NAND flash memory array region affected and correcting the radiation event based on the radiation event and the NAND flash memory array region affected.

The invention discloses an SSD (Solid State Disk) garbage collection method and device with RAID (Redundant Array of Independent Disk) redundancy and a medium, and relates to the technical field of garbage collection, and the method comprises the following steps: in a garbage collection process, selecting a target NAND flash memory physical block of which the effective data volume meets a collection condition, copying the effective data to a new position, and updating address mapping; querying a first RAID block to which the target block belongs and all member block identifiers thereof according to a first mapping table and a second mapping table which record a mapping relationship between the NAND flash memory physical block and the RAID blocks; and recombining other blocks except the target block in the first RAID block into a second RAID block, recalculating and storing verification data for the second RAID block, synchronously updating the two mapping tables to reflect a new composition relationship, and finally erasing the target block. The physical block of the NAND flash memory is used as the minimum recovery unit to replace the traditional recovery mode taking the whole RAID block as the unit, and the block with the minimum effective data can be preferentially recovered, so that the effective data migration amount is remarkably reduced, the write amplification coefficient is reduced, the abrasion is reduced, and the service life of a hard disk is prolonged.

The invention discloses a QC-LDPC check matrix construction method and device for NAND, equipment and a medium, and relates to the technical field of channel coding, and the method comprises the steps: firstly generating an initial check matrix without a four-ring structure; based on the row weight distribution characteristics of the initial matrix, adjusting non-zero item arrangement to generate a middle check matrix with uniform row weight; and finally, traversing non-zero items of the intermediate matrix column by column and row by row, and minimizing the number of six rings by adjusting a shift value to obtain a target check matrix. According to the method, by optimizing the ring structure and row redistribution of the check matrix in stages, the influence of four rings and six rings on the decoding performance is remarkably reduced, so that the data error correction capability of the NAND flash memory is improved, and the decoding time delay is reduced.

This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage. The disclosed techniques are especially useful for direct-attached and / or network-attached storage.

The invention provides a test method and device based on an FRT table, equipment and a storage medium, and relates to the technical field of computers. The method comprises: generating a test sequence; the test sequence can cover the voltage combination in the FRT table; determining a test mode based on the test sequence; the test mode is an index mode or a global mode; reading a corresponding voltage offset in an FRT table based on the test mode and the test sequence; based on the voltage offset, reading the target data from an NAND flash memory of a solid state disk SSD; determining a test result based on the reading state of the target data; the reading state comprises the number of rereading times of the FRT table, the number of hard decoding times of the target data, the number of soft decoding times of the target data and the data recovery time delay. The test efficiency can be improved, the dependence on the environment is reduced, and the fault mode coverage rate is improved.

The invention discloses a flash memory error injection test method and electronic equipment, and relates to the technical field of error injection test.The flash memory error injection test method comprises the steps that by means of the inherent physical characteristic, namely, the write-in characteristic, of an NAND flash memory, different data are written in the same position of a target block in the flash memory at least twice, the number of free electrons of a floating gate of the flash memory is interfered from the physical level, and the number of the free electrons is increased; according to the method, the internal data error of the flash memory is caused, and a physical abnormal scene of the flash memory is constructed, so that the read-write error test of the flash memory is realized, a technician can conveniently and timely find out the problem exposed in the test process of the flash memory, and the fault risk after mass production is reduced.

Disclosed are a device for encryption and decryption and a method for processing data. The device may be implemented by a memory device with a three-dimensional NAND flash memory with high capacity and high performance. The device includes a memory array, a data-sensing circuit, and a memory controller. A memory block in the memory array includes a first memory string with a first bit-line and a second memory string with a second bit-line. The memory controller is configured to: obtain a codec key, wherein memory cells in a first memory sub-area are set according to the codec key, and memory cells in a second memory sub-area are programed according to a complementary codec key; generate bit-line voltages of the first and the second bit-lines according to an input data; bias the memory cells in the first and the second memory sub-areas; and, obtain an output data according to the data-sensing circuit.

The invention provides an operating method of a memory device and a memory device thereof. The memory device can be a three-dimensional NAND flash memory with high capacity and high performance. The operating method includes performing a program operation on the plurality of memory cells based on the i-th potential state. The programming operation based on the ith potential state comprises the following steps: in a programming pulse stage, applying a programming pulse corresponding to the ith potential state to a plurality of first storage units corresponding to the ith potential state; and, in a verification stage after the program pulse stage, performing a first sensing operation on the plurality of second memory cells in the (i-1)-th potential state to verify a threshold voltage distribution situation of the plurality of second memory cells, and performing a second sensing operation on the plurality of first memory cells to implement a program verification operation in the i-th potential state.

The present invention relates to an apparatus and method for generating a parameter page library for a NAND flash memory, and more particularly to an apparatus and method for generating a parameter page library for each memory chip by reading the parameter pages of the NAND flash memory in an environment where the internal controller of the NAND flash memory device is unavailable.

This invention relates to the field of smart chip technology, and discloses a method and apparatus for adjusting the read threshold of NAND flash memory based on temperature compensation. The method includes: acquiring real-time flash memory temperature and corresponding read threshold data, aligning timestamps to obtain an initial associated dataset; segmenting the dataset into fixed windows and calculating the temperature change rate and threshold change amplitude; dividing different threshold offset patterns through clustering and associating them with storage; constructing a prediction model based on an error rate index; monitoring temperature fluctuations and predicting the threshold offset if it exceeds the threshold, and calculating correction parameters; correcting the initial threshold to obtain the read standard; generating a threshold set by fusing risk assessment and offset patterns; and batch verifying and filtering read thresholds with low error rates to obtain an optimized threshold configuration. This method can achieve dynamic and precise adjustment of the NAND flash memory read threshold under temperature fluctuations, meeting the high reliability requirements of storage devices in complex environments.

The present invention relates to a method for recommending an optimal applied voltage for data extraction of a NAND flash memory. The method for recommending an optimal applied voltage for data extraction of a NAND flash memory according to one aspect of the present invention comprises: an initial data extraction step of applying a preset initial applied voltage to an input pin of a NAND flash memory, extracting data included in the NAND flash memory, and storing a logical address of the data; a per-voltage data extraction step of applying a plurality of voltages, obtained by repeatedly increasing or decreasing the initial applied voltage by a predetermined voltage, to the input pin of the NAND flash memory, each at different time points, and extracting, for each voltage, data having the same logical address as the logical address of the data extracted in the initial data extraction step; and a step of recommending an optimal applied voltage on the basis of binary data generated by performing an XOR operation between data having the same logical address extracted according to different applied voltages.

A card controller (22) observes the access history of accessing an SD card (20) by a host device (10). The card controller (22) uses a pattern selector (41) to determine which of a plurality of patterns the observed access history corresponds to. The card controller (22) reads, from a register (31a), a control parameter associated with the determined pattern. The card controller (22) controls writing to and reading from a NAND flash memory (23) in accordance with the control parameter read from the register (31a). The access history includes at least a data size and an address.

A memory device includes a stacked structure, a channel pillar, a charge storage structure, and a separation wall. The stacked structure is located above a substrate and includes conductive layers and insulating layers arranged alternately with each other. The channel pillar passes through the stacked structure. The charge storage structure is located between the channel pillar and the conductive layer. The separation wall passes through the stacked structure, the separation wall including sub-walls stacked on each other. Of two adjacent sub-walls among the sub-walls, an upper width of a lower sub-wall is greater than a lower width of an upper sub-wall. The memory device can be applied to 3D NAND flash memory to create memory devices with high capacity and performance.

The invention discloses a performance optimization method for a high-density 3D NAND flash memory. The method comprises the following steps of: obtaining a writing request of a plurality of to-be-written data in a cache block and an old placement flash memory block; classifying the to-be-written data according to the writing request and the old placement position of each to-be-written data to obtain the type of each to-be-written data; and writing the to-be-written data into a new flash memory block according to the type of each to-be-written data. The performance optimization method has the advantages of being short in response time, long in service life and high in performance.