488 results about "Nand flash memory" patented technology

The invention discloses a large language model accelerator architecture based on a three-dimensional NAND flash memory, and belongs to the technical field of calculation, reckoning or counting. The architecture comprises a three-dimensional NAND flash memory used for executing feedforward neural network calculation; the auxiliary calculation unit is used for executing attention mechanism calculation; the DRAM chip is used for storing attention mechanism related weights and KV cache; and the interconnection resource is used for realizing data interaction among the components. Wherein the three-dimensional NAND flash memory comprises a logic chip and an NAND array chip, the logic chip is used for controlling and executing calculation, and the NAND array chip is used for storing weights and participating in calculation. The invention further provides a scheduling method based on KV cache awareness. The scheduling method comprises decomposition and dynamic allocation of calculation tasks. Through collaborative design of the hardware architecture and the scheduling method, the memory wall bottleneck in large language model calculation can be relieved, the energy consumption is reduced, and the overall calculation performance is improved.

The invention discloses an edge end large language model inference system. The system comprises a main computing chip, an LPDDR interconnection resource and a vertically stacked and packaged storage chip stack, the storage chip stack comprises an NAND flash memory chip and a DRAM (Dynamic Random Access Memory) chip, and the NAND flash memory chip and the DRAM chip are paired and share an LPDDR interconnection resource; the NAND flash memory chip comprises a flash memory chip bare chip and a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) chip bare chip which are three-dimensionally interconnected based on hybrid bonding; a flash memory array is arranged on the flash memory chip bare chip; a logic block is arranged on the CMOS chip bare chip; the main calculation chip reads a parameter matrix of a model full connection layer from the NAND flash memory chip and reads other parameters from the DRAM chip for calculation in a pre-filling stage of large language model reasoning; and the NAND flash memory chip performs full connection layer calculation in a decoding stage. The system provided by the invention can improve the external transmission and internal reading bandwidth.

Disclosed are a memory device and a control method thereof. The memory device may be a high-capacity and high-performance three-dimensional NAND flash memory. The control method includes the following steps. Data for performing a programming operation on a specific memory cell area is obtained. A number of memory cells in a predetermined potential state in the data are counted as a first number value. The programming operation is performed on the specific memory cell area based on the data. A read operation is performed based on a reference voltage corresponding to the predetermined potential state. A number of memory cells in the predetermined potential state in the specific memory cell area after the programming operation are counted as a second number value. Whether the specific memory cell area has program disturbances is determined based on the first number value and the second number value.

A system in package platform includes a processor chip having a runtime processor core, an accelerator core and a processor-memory interface exposed on a chip-to-chip bonding surface, a first memory chip such as 3D NAND flash memory storing a collection of executable models of inference engines, and a second memory chip storing weights of a selected executable model. The second memory chip can comprise a nonvolatile, random access memory, such as phase change memory. Direct vertical connections such as via-to-via connections, are provided between the processor chip and the second memory chip.

The invention provides a method and system for optimizing reading reference voltage of a three-dimensional NAND flash memory, and relates to the technical field of semiconductor memorizes.The method comprises the steps that the erasing frequency and the data retention time of the three-dimensional NAND flash memory are obtained; if the data retention time is not clear, inversely deducing the time through a sampling adjustment method, inputting the inversely deduced data retention time and erasing times into an optimal read reference voltage prediction model, and outputting an average optimal offset value of each read reference voltage; if so, substituting the two parameters into an optimal read reference voltage prediction model to output an average optimal offset value of each read reference voltage; and finally, compensating the average optimal offset value of each read reference voltage by using the interlayer difference table, and outputting all optimal read reference voltages of each layer. According to the method and the device, the accuracy of reading reference voltage optimization strategy prediction can be improved, the time overhead is reduced, and the reading performance is improved.

The invention discloses a dormancy and awakening system and method of an enterprise-level solid state disk, and belongs to the technical field of power consumption management of the enterprise-level solid state disk. According to the system, a nonvolatile cache unit, an independent hardware state machine and an ultra-low power consumption wake-up detection circuit are integrated in a main controller. When entering the dormancy state, key data such as an FTL mapping table are stored in a nonvolatile cache, then the power management module cuts off power supply to the NAND flash memory and the main control core, and only the operation of the minimum circuit is maintained, so that the dormancy power consumption is reduced to be below 100mW; and during wakeup, the detection circuit identifies a physical layer signal to trigger rapid power-on, and the hardware state machine directly recovers the system state from the cache and bypasses the software initialization process, so that wakeup is completed and the NAND access capability is reconstructed within 1ms, and the industrial problem that ultra-low power consumption and rapid wakeup cannot be considered at the same time is effectively solved.

The invention provides a polarization code optimization method for a TLC flash memory, which belongs to the technical field of polarization code optimization of an NAND flash memory, and comprises the following steps of: firstly, constructing a polarization code based on a Monte Carlo method: randomly generating code words in each simulation, coding after setting frozen bits, transmitting and reading data through a flash memory channel, counting and accumulating sub-channel error times by using SC decoding, and calculating an error probability; the information bit determination process is optimized according to P / E cycle times for flash memory characteristics; data to be stored in a flash memory are coded based on PC-CASCL, an original binary bit sequence is averagely segmented, PC codes of all sub-segments are added with check bits, after the sub-segments are combined, CRC coding is carried out through a preset polynomial, polar code coding is carried out on a result, and the result is stored in the flash memory. After the coded data is read from the flash memory, decoding is carried out through PC-CASCL, a decoder is initialized, the maximum path number is set, a path list is created, whether the bits are odd-even check bits or not is judged and checked bit by bit, and after all the bits are decoded, an optimal path is selected as output through CRC code check.

The invention discloses an NAND flash memory reading voltage axis dynamic prediction method and device and a storage medium, and the method comprises the steps: selecting sample data covering different types of NAND flash memories, and carrying out the training, and obtaining a GRUM model; taking PE times, RET time and VTH distribution in the sample data as the input of a GRUM model, and taking the output of the GRUM model as an optimal reading voltage axis prediction value; maintaining a weight matrix of the trained GRUM model as a base weight; taking the normalized PE times and VTH distribution as input features, taking the dimensionality-reduced weight adjustment amount as output, and constructing and training a polynomial regression model; and loading the target weight to the GRUM model to predict the optimal reading voltage of the NAND flash memory to be processed. According to the method, the output dimension of a subsequent polynomial regression model is reduced, calculation and storage burdens are reduced, meanwhile, invalid weight files are removed, and the resource utilization efficiency is further improved.

The invention discloses an NAND block health degree prediction method and system based on read interference perception. The method comprises the steps that read interference event counts of an NAND flash memory block are collected in real time; dynamically triggering multi-dimensional parameter acquisition to generate multi-dimensional parameter data with timestamps; extracting a dynamic change rate, a distribution entropy value and a growth slope feature based on the multi-dimensional parameters, and generating a compression feature matrix; inputting the compressed feature matrix into a pre-trained graph neural network-Hamiltonian Monte Carlo hybrid model, outputting a health degree score and recording a low-confidence sample; based on the health degree score and the historical health degree attenuation trajectory, generating an early warning level signal through a dynamic threshold engine; executing a corresponding block maintenance strategy according to the early warning level, and recording strategy execution effect data; and model parameters are updated through knowledge distillation by utilizing a low-confidence sample and strategy execution effect data, so that level-by-level and cross-level health risks of the NAND flash memory based on read interference perception are truly and accurately reflected.

The invention provides a QLC NAND interference compensation control method and system, and the method comprises the steps: collecting adjacent unit voltage offset data of a target storage unit through an on-chip reference unit array integrated on a QLC NAND flash memory chip; performing feature extraction on the data to obtain interference feature parameters including at least one of voltage drift amplitude, drift rate and drift fluctuation frequency, and inputting the interference feature parameters into a pre-trained lightweight decision tree model to output an interference trend prediction result, a programming parameter optimization strategy is generated based on the result, the pulse width and the step voltage increment are optimized, meanwhile, fine adjustment of model parameters is triggered by collecting programming verification data after each time of optimization, dynamic accurate compensation of memory cell interference under the high write-in load of the QLC NAND flash memory is achieved, programming voltage drift is effectively restrained, and the reliability of the QLC NAND flash memory is improved. The adaptive capacity of the writing algorithm is improved, and the overall service life of the flash memory is prolonged.

The invention discloses a distributed acceleration method and system for a RocksDB storage system based on CSD master control. The method comprises the steps that CSD is deployed in the RocksDB storage system to serve as a computing node, a computing cluster is constructed, a Compaction process is stripped and migrated into the CSD, and an RPC channel is constructed based on the CSD; the compact instruction is directly written into a CSD memory, file meta-information is obtained through analysis, and a corresponding file is read; data needing to be calculated and a calculation instruction are sent to a calculation cluster of the CSD for calculation analysis, and calculation results of the far end are aggregated to the local; and migrating the data to the nand flash memory according to a storage instruction sent by the host side. According to the technical scheme, the CPU load of the host side is effectively reduced, the file data interaction efficiency is greatly improved, and the energy overhead and the time overhead of data migration interaction are greatly reduced.

A technique for writing data to pages in a QLC block of a QLC NAND flash memory device, where the device comprises a plurality of SLC pages organized in SLC blocks and a plurality of QLC pages organized in QLC blocks. The technique comprises storing received data in SLC pages, dividing equally a QLC block in a predefined number of sub-blocks according to a corresponding QLC page health status of the pages of the QLC block. Upon determining that SLC pages are to be copied from SLC pages to QLC pages, copying device-internal the respective SLC pages to the sub-blocks of the QLC block using device-internal cache registers, where the copying is based on an error-count aware scheme.

The embodiment of the invention provides a data processing method, a chip, a storage medium and a computer program product, and relates to the technical field of data processing. The method is applied to a file system for managing an NAND flash memory, and comprises the following steps: acquiring a write-in instruction; dynamically determining a current working mode based on the real-time task scene and / or the data characteristics of the to-be-stored data; the current working mode comprises one of a high-performance mode and a long-life mode; dynamically determining a compression ratio adopted when the to-be-stored data is stored based on the current working mode and / or the compression strategy; the compression ratio corresponding to the long-life mode is greater than the compression ratio corresponding to the high-performance mode; determining a target storage block used for storing the to-be-stored data in the NAND flash memory; and based on the capacity of the storage page, compressing the to-be-stored data according to the determined compression ratio, and storing the compressed to-be-stored data into the target storage block. By adopting the scheme, the storage efficiency and the storage performance are improved, and the service life of the NAND flash memory is prolonged.

The invention discloses a cache management method and a storage medium thereof. The cache management method comprises the steps that when a target data write-in request is responded, page information of a current target block is obtained, and the page information represents a page, needing to be subjected to data read-write operation, of the current target block; according to page information, corresponding block operation is executed, the page information comprises the last page of the current target block, the first page of the current target block and the middle page of the current target block, the page information comprises block operation logic corresponding to the page information, and the block operation logic is used for indicating execution of the corresponding block operation. According to the cache management method disclosed by the invention, the page information is obtained to perform the corresponding block operation on the current target block, so that the block management of the NAND Flash memory can be dynamically realized in real time, the loss of the storage unit is considered, and the erasing and random reading and writing of the storage unit are reasonably arranged, thereby improving the durability and performance of the NAND Flash memory, and improving the user experience. And the overall efficiency of data read-write operation is improved.

The invention relates to the technical field of data backup, and discloses an iOS device data backup and recovery method and system, and the method comprises the steps: carrying out the SSL certificate verification and EscrowBag key authentication of an iOS device, and obtaining a data path list; according to the data path list, parallel scanning of APFS file system B-Tree traversal, NAND flash memory page reading and SQLite WAL log analysis is carried out on the iOS device storage partition, and an original data set is obtained; performing integrity evaluation based on the original data set to obtain an effective data set and constructing a virtual file index; the data selection list of the user is confirmed based on the virtual file index, safety recovery is executed, and a data recovery result is returned. The SQLite page Cell reconstruction and fragment file signature matching technology is combined, intelligent repair and quality prediction can be conducted on damaged data, the user experience and operation efficiency are improved, and the user experience is improved. And the security and the reliability in the data recovery process are ensured.

A vertical NAND flash memory device and an electronic apparatus including the same are provided. The vertical NAND flash memory device includes a plurality of cell arrays. Each of the plurality of cell arrays includes a channel layer, a charge trap layer, and a plurality of gate electrodes provided on the charge trap layer. The charge trap layer includes a matrix including amorphous metal oxynitride and nanocrystals dispersed in the matrix and including nitride having semiconductor characteristics.

The invention discloses an NAND flash memory, a memory and electronic equipment. Data of a plurality of pages can be read at the same time under the same face in the NAND, the saturation current of each page can be different, and / or the time for reading the data of each page can be different, so that the data recorded by each page is different, the total current of a reading circuit is different, and the voltage drop speed of a discharge capacitor CSO is different. When the NAND flash memory reads data of a plurality of pages, the voltage comparison unit can be used for detecting the relation between the voltage of the discharge capacitor CSO and the comparison voltage so as to accurately read data recorded in each page, and confusion between the read data and the pages is avoided.

The invention discloses a fast data protection method and device for SSD abnormal power failure, equipment and a medium, and relates to the field of SSDs, and the method comprises the steps: monitoring a power supply voltage, and generating an interrupt signal when the power supply voltage is lower than a preset threshold value; in response to the interrupt signal, turning off a power supply of a preset non-data path hardware module through the SSD controller; stopping scheduling all operation commands for the NAND flash memory through the SSD firmware, and emptying a data path in an NAND flash memory controller; writing the user data in the host write cache and the command information corresponding to the user data into a special physical address block reserved in the SSD in advance; after the SSD is powered on again, the address mapping table is recovered by scanning the write-in point in the NAND flash memory, the backup data and the command information in the special physical address block are read, and the backup data are written into the user data area according to the command information. According to the method, the key data backup time during abnormal power failure is shortened, the capacity requirement for the standby capacitor is reduced, and the problem that the cost is increased due to the fact that the backup time is too long is effectively solved.

The invention provides an NAND flash memory write-in distribution method of a solid state disk, which is used for dynamically determining an optimal block for data write-in by analyzing content characteristics and update frequency of data to be written in, evaluating health state of each block of a flash memory and establishing data repetition and update frequency indexes. According to the method, static or repetitive data can be assigned to blocks with low or medium health degree according to data characteristics, data with high updating frequency is preferentially written into the healthy blocks, and the health state and statistical information of the blocks are updated in each writing period, so that the service life of the non-volatile flash memory is prolonged, the non-uniform service life distribution of the blocks is improved, and the service life of the non-volatile flash memory is prolonged. And the balance of writing efficiency is maintained. In addition, through feature abstract comparison and hash value check, data characteristics can be accurately identified, and a reliable, dynamic and efficiency-optimized flash memory management effect is achieved.

Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method is provided for programming a memory device having a plurality of memory chips that comprise multiple-level-cells. The method includes loading first data in a first chip, programming the first data into selected cells of the first chip using a single-level-cell (SLC) programming mode, and reprogramming the first data stored in the selected cells of the first chip to other cells of the first chip using a multiple-level-cell programming mode. The method also includes repeating the operations of loading, programming, and reprogramming for the remaining chips. The loading operations for the remaining chips begin at the completion of the loading operation for the first chip and occur in a non-overlapping sequential manner, and the loading operations for the remaining chips are performed in parallel with the programming and reprogramming operations of the first chip.

The embodiment of the invention provides a method for optimizing NAND flash memory data retention capability, electronic equipment and a computer readable storage medium. The method comprises the following steps: determining detection time under the condition that the embedded multimedia card is switched from a working state to a dormant state; under the condition that the detection time reaches a preset time threshold value, detecting an error correction code (ECC) of the firmware program; under the condition that the ECC reaches a preset detection threshold value, the detection temperature is obtained; and according to the detection temperature and the preset temperature scene division information, controlling the firmware program to carry out refreshing processing or keep the firmware program unchanged. According to the scheme of the embodiment of the invention, the firmware program can be updated in combination with the detection time and the detection temperature, and the data retention capability of the NAND flash memory is improved, so that the accuracy of subsequent data reading can be well improved.

The invention provides a garbage collection method and system for a solid state disk to quickly enter a steady state, and the method comprises the steps: in a process of writing data into an nand flash memory block, an open data block which is being written exists at the same time; after the solid state disk starts garbage collection, taking the open data block as a write-in target block for garbage collection; obtaining user data and effective data of garbage collection, and calculating a write-in proportion; alternately writing the user data and the effective data of garbage collection into a write-in target block of garbage collection according to a write-in proportion; the stability of the solid state disk performance is improved, the garbage collection efficiency is improved, the service life of the solid state disk is prolonged, and the user experience is improved.

The invention provides an LDPC (Low Density Parity Check) correction method and system for an error interval of an NAND flash memory, and the method comprises the steps: recognizing an abnormal interval expansion trend of the NAND flash memory, recognizing an error code interval according to a data writing task of the flash memory, and judging whether an error code occurs in an interval, in which data is stored, in the flash memory or not; adjusting the LDPC correction of the flash memory according to the error code interval and the reading quality of data received by the flash memory, and adjusting the return state of a data reading result according to the execution state of the LDPC correction to ensure that the read return data is correct; according to information that LDPC correction is not completed in the power-on process of the flash memory, an LDPC correction guide is generated, and the LDPC correction operation on the flash memory is adjusted according to a task instruction received after the flash memory is powered on again, so that all error code intervals in the flash memory are effectively corrected, the intervals with data errors in the flash memory are prevented from being continuously increased and accumulated, and the error correction efficiency of the flash memory is improved. The overall data storage reliability of the NAND flash memory is improved, and the data reading / writing correctness of the NAND flash memory is ensured.

The invention provides an operation method of a storage controller, the storage controller and a storage system, relates to the technical field of storage, and aims to solve the problems that the time for searching and adjusting control parameters related to the signal quality of a bus of an NAND flash memory is long and the like. The method comprises the steps that in response to a training instruction received by a processor, multiple control parameter sets are generated randomly, the control parameter sets are used for adjusting the size of an eye pattern of signal transmission between a storage controller and a memory, the fitness of the control parameter sets is determined, the multiple control parameter sets are iteratively updated through a genetic algorithm till an iteration stopping condition is met, and the iteration stopping condition is executed. And after iteration is stopped, determining the control parameter group with the maximum fitness in the plurality of control parameter groups obtained by the last iteration update as a target control parameter group.

The invention discloses a method for optimizing ECC (Error Correction Code) protection strength of an NAND FLASH in-memory computing system for an LLM inference chip, and belongs to the technical field of computing, reckoning or counting. Based on an NAND FLASH in-memory computing architecture, the invention provides a self-adaptive sub-plane protection strategy based on a Hamming code, and an error sensitivity grading model of sign bits, index bits and mantissa bits is established by analyzing BF16 numerical value distribution characteristics of large language model weight data; in combination with a residual connection structure of a Transform decoding layer, inter-layer cosine similarity is calculated to evaluate layer importance; and dynamically adjusting the Hamming code protection granularity by adopting a greedy algorithm, and carrying out iterative optimization according to a simulation error injection result until the model confusion degree and the accuracy meet threshold values. And performing ECC software and hardware collaborative design according to an iteration result of the greedy algorithm to obtain an ECC circuit required to be configured by each plane of the NAND flash memory. According to the method, the circuit area power consumption is remarkably reduced while the model reasoning precision is ensured, the ECC bandwidth requirement is reduced, and the large model reasoning efficiency and reliability are remarkably improved.

Disclosed are a memory device and a control method thereof. The memory device may be a high-capacity and high-performance three-dimensional NAND flash memory. The control method includes the following steps. Data for performing a programming operation on a specific memory cell area is obtained. A number of memory cells in a predetermined potential state in the data are counted as a first number value. The programming operation is performed on the specific memory cell area based on the data. A read operation is performed based on a reference voltage corresponding to the predetermined potential state. A number of memory cells in the predetermined potential state in the specific memory cell area after the programming operation are counted as a second number value. Whether the specific memory cell area has program disturbances is determined based on the first number value and the second number value.

A flash memory device includes a cell array and a control circuit. The cell array includes a first NAND string having first flash memory cells having control gates respectively connected to word lines, and a first bit line selection switch connecting the first flash memory cells to a first bit line according to a control of a first string selection line. The control circuit controls a first erase operation for erasing a selected flash memory cell. The control circuit controls a voltage difference between the first bit line and the first string selection line to have a first value for generating gate induced drain leakage (GIDL) at the first bit line selection switch, and controls a voltage of a control gate of the selected flash memory cell and a voltage of a control gate of an unselected flash memory cell to be different from each other.

The invention discloses a flash memory and near memory acceleration system of an end-side large language model, and belongs to the technical field of calculation, reckoning or counting. According to the system, a 3D NAND flash memory chip with near memory computing capability is adopted, and model weights and key value caches are uniformly stored in the flash memory. Storage-intensive operations involved in the big language model inference decoding stage are all completed in a logic layer of a flash memory, and an NPU only executes non-linear operations such as normalization and activation and residual connection; in the pre-filling stage, the NPU obtains weight and key value cache data from the flash memory and is used for completing all calculations. Redundant read-write is reduced through a flash memory page-level key value cache mapping mechanism; and meanwhile, attention head group parallel data stream optimization is provided, so that the parallelism of a decoding stage is improved. A discrete framework and a compact framework are further provided, and optimal configuration is automatically selected in combination with a design space exploration strategy. According to the method, the requirement of edge end large language model reasoning on the DRAM can be omitted, delay is reduced, throughput is improved, and system cost and power consumption are remarkably reduced.

The invention relates to the technical field of intelligent chips, and discloses an NAND flash memory reading threshold adjusting method and device based on temperature compensation. The method comprises the following steps: acquiring real-time temperature of a flash memory, and aligning the real-time temperature with corresponding read threshold data and timestamps to obtain an initial associated data set; segmenting according to a fixed window, and calculating a temperature change rate and a threshold value change amplitude; different threshold offset modes are divided through clustering and are stored in an associated manner; constructing a prediction model in combination with an error rate index; if the monitored temperature fluctuation exceeds a threshold value, the threshold value offset is predicted, and a correction parameter is calculated; correcting the initial threshold value to obtain a reading standard; generating a threshold set by fusing risk assessment and an offset mode; and verifying and screening reading thresholds with low error rates in batches to obtain optimized threshold configuration. According to the method, the reading threshold of the NAND flash memory can be dynamically and accurately adjusted under temperature fluctuation, and the use requirement of high reliability of storage equipment in a complex environment is met.

A method for reading data from an SSD, comprising: retrieving data from a target row of memory cells using initial threshold voltages; decoding the data using a first hard decision decoding stage; estimating a bit error rate (BER) of a target row of memory cells based on a distribution of threshold voltages of cells in a memory block containing the target row when the first hard decision decoding stage fails; classifying the BER of the target row based on a first BER threshold (BER-TH1); and executing a first read flow comprising at least one hard decision decoding stage if the BER is less than the BER-TH1, and executing a second read flow similar to the first read flow if the BER is greater than or equal to the BER-TH1, the second read flow skipping a hard decision decoding stage of the first read flow.