11 results about "Indirection" patented technology

A system and method for storing data in a memory device. The method includes transmitting, to a host, information indicative of a first allowable maximum size of a first namespace associated with a first IU and a second allowable maximum size of a second namespace associated with a second IU. The first and the second IUs may be of different sizes. The includes comprise receiving configuration information comprising one or more instructions to: generate a first L2P table associated with the first IU based on the first allowable maximum size, and generate a second L2P table associated with the second IU based on the second allowable maximum size and generating the first L2P table and the second L2P table based on the configuration information; and causing first data and second data to be stored in the first namespace and the second namespace using the first and second L2P tables respectively.

Mechanisms, including systems, methods, and media, for processing sub-indirection unit sized data in a solid-state drive (SSD) are provided, the methods including: identifying, in a first portion of storage of the SSD, a plurality of indirection units each containing sub indirection-unit-sized data and padding; combining the plurality of indirection units into a page-size data structure using a hardware processor; copying contents of the page-sized data structure to a second portion of storage of the SSD; and updating a data structure relating logical address of data to physical locations of data so that an entry corresponding to the sub-indirection-unit sized data of one of the plurality of indirection units changes from having a physical address in the first portion of storage to having a physical address in the second portion of storage.

Mechanisms, including systems, methods, and media, for processing sub-indirection unit sized data in a solid-state drive (SSD) are provided, the methods including: identifying, in a first portion of storage of the SSD, a plurality of indirection units each containing sub-indirection-unit-sized data and padding; combining the plurality of indirection units into a page-size data structure using a hardware processor; copying contents of the page-sized data structure to a second portion of storage of the SSD; and updating a data structure relating logical address of data to physical locations of data so that an entry corresponding to the sub-indirection-unit-sized data of one of the plurality of indirection units changes from having a physical address in the first portion of storage to having a physical address in the second portion of storage.

Mechanisms, including systems, methods, and media, for processing sub-indirection unit sized data in a solid-state drive (SSD) are provided, the methods including: identifying, in a first portion of storage of the SSD, a plurality of indirection units each containing sub-indirection-unit-sized data and padding; combining the plurality of indirection units into a page-size data structure using a hardware processor; copying contents of the page-sized data structure to a second portion of storage of the SSD; and updating a data structure relating logical address of data to physical locations of data so that an entry corresponding to the sub-indirection-unit-sized data of one of the plurality of indirection units changes from having a physical address in the first portion of storage to having a physical address in the second portion of storage.

This application is directed to compressing a logical-to-physical address indirection table in a memory system of an electronic device. The electronic device identifies an address block including a plurality of physical addresses that corresponds to an ordered sequence of logical addresses. Each logical address corresponds to a distinct physical address. The electronic device further determines that a first physical address is associated with a first word having a first word location in the address block, and extracts the first word from the first word location in the address block. Based on the first word location, the electronic device determines a first bit location in a supplemental word that is distinct from the first word. The electronic device extracts at least a first bit from the first bit location of the supplemental word, and generates the first physical address based on the first word and the first bit.

This application is directed to compressing a logical-to-physical (L2P) address indirection table in a memory system of an electronic device. The electronic device determines a plurality of physical addresses corresponding to an ordered sequence of logical addresses. Each logical address corresponds to a distinct physical address. The electronic device identifies a set of most significant bits (MSBs) and a set of least significant bits (LSBs) of each of the plurality of physical addresses and determines a set of data bits based on a plurality of MSB sets including the set of MSBs of each of the plurality of physical addresses. The set of LSBs of each of the plurality of physical addresses and the set of data bits are stored jointly in the L2P address indirection table.

The subject technology stores an original file master key identifier (FMKID) in metadata associated with an encrypted file, the encrypted file including data. The subject technology determines that the encrypted file is to be re-encrypted based at least on a period of time since the original FMKID was stored. The subject technology re-encrypts the data using a new encryption key associated with a new FMKID. The subject technology generates a mapping from the original FMKID to the new FMKID. The subject technology stores the mapping in a metadata database, the mapping being associated with a re-encrypted file, the re-encrypted file including the re-encrypted data.

Hardware support for light-weight instances achieve the effect of multi-level instancing without incurring associated performance or area cost, enabling a Cluster-Level AS (CLAS) to be used for a faster build speed. The same subdivision mechanism can also be used to reduce the complexity of the TLAS build by dividing instances into groups. Pseudo-Instance Nodes (PIN) allow for an indirection from a BVH node to any arbitrary location of a child complet. Multi-Parent Root Complets (MPRC) allow for any CLAS to be reused across multiple BLASs.

Techniques are provided for providing a storage abstraction layer for a composite aggregate architecture. A storage abstraction layer is utilized as an indirection layer between a file system and a storage environment. The storage abstraction layer obtains characteristic of a plurality of storage providers that provide access to heterogeneous types of storage of the storage environment (e.g., solid state storage, high availability storage, object storage, hard disk drive storage, etc.). The storage abstraction layer generates storage bins to manage storage of each storage provider. The storage abstraction layer generates a storage aggregate from the heterogeneous types of storage as a single storage container. The storage aggregate is exposed to the file system as the single storage container that abstracts away from the file system the management and physical storage details of data of the storage aggregate.

A host stores “context” metadata for logical block addresses (LBAs) in a manner tied to physical location. Notwithstanding log-structured or copy on write processes, the host is then provided with immediate context when the host is called upon to assist a memory controller with data identified by physical location, for example, for memory reconfiguration, garbage collection, wear leveling or other processes. The metadata for example can provide the host with insight as to which data may be moved to enhance performance optimization and where that data can be placed. In one embodiment, the host writes back one or more references that span multiple layers of indirection in concert with write of the underlying data; in another embodiment, the context can point to other metadata.

A system and method for storing data in a memory device. The method includes transmitting, to a host, information indicative of a first allowable maximum size of a first namespace associated with a first IU and a second allowable maximum size of a second namespace associated with a second IU. The first and the second IUs may be of different sizes. The includes comprise receiving configuration information comprising one or more instructions to: generate a first L2P table associated with the first IU based on the first allowable maximum size, and generate a second L2P table associated with the second IU based on the second allowable maximum size and generating the first L2P table and the second L2P table based on the configuration information; and causing first data and second data to be stored in the first namespace and the second namespace using the first and second L2P tables respectively.