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29 results about "Indirection" patented technology
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In computer programming, indirection (also called dereferencing) is the ability to reference something using a name, reference, or container instead of the value itself. The most common form of indirection is the act of manipulating a value through its memory address. For example, accessing a variable through the use of a pointer. A stored pointer that exists to provide a reference to an object by double indirection is called an indirection node.
Leveraging Different Indirection Units To Tune System Performance Based On Workload Demands
Data for a first type of workload that is to be stored in a storage system is received. A first request to store the data for the first type of workload in flash memory is transmitted to a storage device of the storage system. The data for the first type of workload is to be mapped using a first indirection unit (IU) size. Data for a second type of workload that is to be stored in the storage system is received. A second request to store the data for the second type of workload in the flash memory is transmitted to the storage device. The data for the second type of workload is to be mapped using a second IU size that is different than the first IU size.
Owner:PURE STORAGE INC
Methods and systems for storing data in a memory device having dynamic namespace with different indirection unit sizes
A system and method for storing data in a memory device. The method includes transmitting, to a host, information indicative of a first allowable maximum size of a first namespace associated with a first IU and a second allowable maximum size of a second namespace associated with a second IU. The first and the second IUs may be of different sizes. The includes comprise receiving configuration information comprising one or more instructions to: generate a first L2P table associated with the first IU based on the first allowable maximum size, and generate a second L2P table associated with the second IU based on the second allowable maximum size and generating the first L2P table and the second L2P table based on the configuration information; and causing first data and second data to be stored in the first namespace and the second namespace using the first and second L2P tables respectively.
Owner:SK HYNIX NAND PRODUCT SOLUTIONS CORP
Compression of logical-to-physical address indirection table on solid-state drives
PCT designated stage expiredWO2024205973A3Memory architecture accessing/allocationInput/output to record carriersParallel computingTheoretical computer science
This application is directed to compressing a logical-to-physical (L2P) address indirection table in a memory system of an electronic device. The electronic device determines a plurality of physical addresses corresponding to an ordered sequence of logical addresses. Each logical address corresponds to a distinct physical address. The electronic device identifies a set of most significant bits (MSBs) and a set of least significant bits (LSBs) of each of the plurality of physical addresses and determines a set of data bits based on a plurality of MSB sets including the set of MSBs of each of the plurality of physical addresses. The set of LSBs of each of the plurality of physical addresses and the set of data bits are stored jointly in the L2P address indirection table.
Owner:SK HYNIX NAND PRODUCT SOLUTIONS CORP
Write Amplification Reduction with Sub-Indirection Unit (IU) Hinting
PendingUS20260030169A1Memory architecture accessing/allocationMemory systemsWrite amplificationParallel computing
Sub indirection unit (IU) write ordering can be achieved by aggregating log data in local cache. The cache is IU sized. If a write command is analyzed and determined to need to be aggregated, through a host provided hint or perhaps a determination of sequential write commands, the log data is placed in the local cache to aggregate log data. The log data is aggregated in order both sequentially and atomically. The log data is written to a cache and then, when additional log data is to be aggregated with the log data, copied to a new cache along with the additional log data so that the order can be maintained. Sufficient log data is aggregated until IU size is reached at which time the entire log data of a full IU sized cache is sent to the memory device.
Owner:SANDISK TECHNOLOGIES LLC
Dram layout for logical-to-physical (L2P) address indirection table (AIT)
PCT designated stageWO2025240353A1Memory architecture accessing/allocationInput/output to record carriersDatabaseComputer engineering
This application is directed to compressing a logical-to-physical address indirection table in a memory system of an electronic device. The electronic device identifies an address block including a plurality of physical addresses that corresponds to an ordered sequence of logical addresses. Each logical address corresponds to a distinct physical address. The electronic device further determines that a first physical address is associated with a first word having a first word location in the address block, and extracts the first word from the first word location in the address block. Based on the first word location, the electronic device determines a first bit location in a supplemental word that is distinct from the first word. The electronic device extracts at least a first bit from the first bit location of the supplemental word, and generates the first physical address based on the first word and the first bit.
Owner:SK HYNIX NAND PRODUCT SOLUTIONS CORP
Systems, methods, and media for processing sub-indirection-unit data in solid-state drives
Mechanisms, including systems, methods, and media, for processing sub-indirection unit sized data in a solid-state drive (SSD) are provided, the methods including: identifying, in a first portion of storage of the SSD, a plurality of indirection units each containing sub indirection-unit-sized data and padding; combining the plurality of indirection units into a page-size data structure using a hardware processor; copying contents of the page-sized data structure to a second portion of storage of the SSD; and updating a data structure relating logical address of data to physical locations of data so that an entry corresponding to the sub-indirection-unit sized data of one of the plurality of indirection units changes from having a physical address in the first portion of storage to having a physical address in the second portion of storage.
Owner:SK HYNIX NAND PRODUCT SOLUTIONS CORP
Method for communicating data between a slave device and a master device, and corresponding integrated system
The present disclosure provides a method for communicating data between a slave device and a master device according to a communication protocol. An example includes the data being recorded in a memory belonging to the slave device, the method comprising a generation by the master device of a command provided by the communication protocol, and use of a field of the command in order to select an indirection register belonging to the slave device and containing an address of a region of the memory including the data.
Owner:STMICROELECTRONICS (ROUSSET) SAS
Method of data communication between a slave device and a master device, and corresponding integrated system.
One aspect concerns a method for communicating data between a slave device (SLV) and a master device (HST) according to a communication protocol (SDIO). The data is stored in a memory belonging to the slave device (SLV). The method includes the master device generating a command (CMD) as defined by the communication protocol, and using a field of the command (RegAdd) to select an indirection register (DMAi_BAdd; DMAi_Sz) belonging to the slave device and containing an address of a memory region (MEM) containing the data. Figure 2 for the abstract
Owner:STMICROELECTRONICS INT NV
Composite aggregate architecture
ActiveUS12468468B2Memory architecture accessing/allocationInput/output to record carriersHard disc driveSolid-state storage
Techniques are provided for providing a storage abstraction layer for a composite aggregate architecture. A storage abstraction layer is utilized as an indirection layer between a file system and a storage environment. The storage abstraction layer obtains characteristic of a plurality of storage providers that provide access to heterogeneous types of storage of the storage environment (e.g., solid state storage, high availability storage, object storage, hard disk drive storage, etc.). The storage abstraction layer generates storage bins to manage storage of each storage provider. The storage abstraction layer generates a storage aggregate from the heterogeneous types of storage as a single storage container. The storage aggregate is exposed to the file system as the single storage container that abstracts away from the file system the management and physical storage details of data of the storage aggregate.
Owner:NETAPP INC
Detecting host write patterns for improving storage media endurance
PendingUS20250307168A1Memory architecture accessing/allocationMemory adressing/allocation/relocationComputer hardwareEngineering
An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive, from a host system, a memory write request specifying a data item to be stored on the memory device; identify a start logical address and an end logical address associated with the data item; responsive to determining that at least one of the start logical address or the end logical address is not aligned with a respective indirection unit (IU), store a corresponding misaligned portion of the data item in a cache line; and store an identifier of the respective IU in a metadata item associated with the cache line.
Owner:MICRON TECHNOLOGY INC
Systems, methods, and media for processing sub-indirection-unit data in solid-state drives
Mechanisms, including systems, methods, and media, for processing sub-indirection unit sized data in a solid-state drive (SSD) are provided, the methods including: identifying, in a first portion of storage of the SSD, a plurality of indirection units each containing sub-indirection-unit-sized data and padding; combining the plurality of indirection units into a page-size data structure using a hardware processor; copying contents of the page-sized data structure to a second portion of storage of the SSD; and updating a data structure relating logical address of data to physical locations of data so that an entry corresponding to the sub-indirection-unit-sized data of one of the plurality of indirection units changes from having a physical address in the first portion of storage to having a physical address in the second portion of storage.
Owner:SK HYNIX NAND PRODUCT SOLUTIONS CORP
Method of distributed graph loading for minimal communication and good balance via lazy materialization and directory indirection using indexed tabular representation
ActiveUS12411672B2Input/output to record carriersResource allocationAlgorithmTheoretical computer science
Owner:ORACLE INT CORP
Systems, methods, and media for processing sub-indirection-unit data in solid-state drives
Mechanisms, including systems, methods, and media, for processing sub-indirection unit sized data in a solid-state drive (SSD) are provided, the methods including: identifying, in a first portion of storage of the SSD, a plurality of indirection units each containing sub-indirection-unit-sized data and padding; combining the plurality of indirection units into a page-size data structure using a hardware processor; copying contents of the page-sized data structure to a second portion of storage of the SSD; and updating a data structure relating logical address of data to physical locations of data so that an entry corresponding to the sub-indirection-unit-sized data of one of the plurality of indirection units changes from having a physical address in the first portion of storage to having a physical address in the second portion of storage.
Owner:SK HYNIX NAND PRODUCT SOLUTIONS CORP
Method for data communication between a slave device and a master device, and an integrated system thereof
One aspect concerns a method of data communication between a slave device (SLV) and a master device (HST) according to a communication protocol (SDIO), the data being stored in a memory belonging to the slave device (SLV), the method comprising a generation by the master device of a command (CMD) provided by said communication protocol, and a use of a field of the command (RegAdd) in order to select an indirection register (DMAi_BAdd ; DMAi_Sz) belonging to the slave device and containing an address of a region of memory (MEM) containing the data.
Owner:STMICROELECTRONICS INT NV
On-SSD-copy techniques using copy-on-write
On-SSD-copy using Copy-On-Write (COW) techniques track indirection updates to the copied data without duplicating the data. In one example, a method involves receiving a copy command to copy data from a source LBA to a destination LBA. An entry in a logical-to-physical (L2P) table corresponding to the destination LBA is updated to refer to the same physical address as the source LBA's entry in the L2P table. Flags in the L2P table are updated to indicate that more than one LBA refers to the same physical address. After updating the L2P table and before copying the data, a token is stored to the storage device. After storing the token, but before copying the data, an acknowledgement can be sent to the host to indicate the copy command is complete. A subsequent write to either the source or destination LBAs trigger a copy of the data.
Owner:SK HYNIX NAND PRODUCT SOLUTIONS CORP
Dram layout for logical-to-physical (L2P) address indirection table (AIT)
ActiveUS20250355811A1Memory architecture accessing/allocationMemory adressing/allocation/relocationDatabaseComputer engineering
This application is directed to compressing a logical-to-physical address indirection table in a memory system of an electronic device. The electronic device identifies an address block including a plurality of physical addresses that corresponds to an ordered sequence of logical addresses. Each logical address corresponds to a distinct physical address. The electronic device further determines that a first physical address is associated with a first word having a first word location in the address block, and extracts the first word from the first word location in the address block. Based on the first word location, the electronic device determines a first bit location in a supplemental word that is distinct from the first word. The electronic device extracts at least a first bit from the first bit location of the supplemental word, and generates the first physical address based on the first word and the first bit.
Owner:SK HYNIX NAND PRODUCT SOLUTIONS CORP
DRAM layout for logical-to-physical (L2P) address indirection table (AIT)
ActiveUS12591521B2Memory architecture accessing/allocationMemory adressing/allocation/relocationDatabaseComputer engineering
This application is directed to compressing a logical-to-physical address indirection table in a memory system of an electronic device. The electronic device identifies an address block including a plurality of physical addresses that corresponds to an ordered sequence of logical addresses. Each logical address corresponds to a distinct physical address. The electronic device further determines that a first physical address is associated with a first word having a first word location in the address block, and extracts the first word from the first word location in the address block. Based on the first word location, the electronic device determines a first bit location in a supplemental word that is distinct from the first word. The electronic device extracts at least a first bit from the first bit location of the supplemental word, and generates the first physical address based on the first word and the first bit.
Owner:SK HYNIX NAND PRODUCT SOLUTIONS CORP
Compression of logical-to-physical address indirection table on solid-state drives
This application is directed to compressing a logical-to-physical (L2P) address indirection table in a memory system of an electronic device. The electronic device determines a plurality of physical addresses corresponding to an ordered sequence of logical addresses. Each logical address corresponds to a distinct physical address. The electronic device identifies a set of most significant bits (MSBs) and a set of least significant bits (LSBs) of each of the plurality of physical addresses and determines a set of data bits based on a plurality of MSB sets including the set of MSBs of each of the plurality of physical addresses. The set of LSBs of each of the plurality of physical addresses and the set of data bits are stored jointly in the L2P address indirection table.
Owner:SK HYNIX NAND PRODUCT SOLUTIONS CORP
On-SSD-copy techniques using copy-on-write
On-SSD-copy using Copy-On-Write (COW) techniques track indirection updates to the copied data without duplicating the data. In one example, a method involves receiving a copy command to copy data from a source LBA to a destination LBA. An entry in a logical-to-physical (L2P) table corresponding to the destination LBA is updated to refer to the same physical address as the source LBA's entry in the L2P table. Flags in the L2P table are updated to indicate that more than one LBA refers to the same physical address. After updating the L2P table and before copying the data, a token is stored to the storage device. After storing the token, but before copying the data, an acknowledgement can be sent to the host to indicate the copy command is complete. A subsequent write to either the source or destination LBAs trigger a copy of the data.
Owner:SK HYNIX NAND PRODUCT SOLUTIONS CORP
Detecting host write patterns for improving storage media endurance
PCT designated stageWO2025207540A1Memory architecture accessing/allocationInput/output to record carriersComputer hardwareEngineering
An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive, from a host system, a memory write request specifying a data item to be stored on the memory device; identify a start logical address and an end logical address associated with the data item; responsive to determining that at least one of the start logical address or the end logical address is not aligned with a respective indirection unit (IU), store a corresponding misaligned portion of the data item in a cache line; and store an identifier of the respective IU in a metadata item associated with the cache line.
Owner:MICRON TECHNOLOGY INC
Rekeying using indirection layer for dynamic key id lookup
The subject technology stores an original file master key identifier (FMKID) in metadata associated with an encrypted file, the encrypted file including data. The subject technology determines that the encrypted file is to be re-encrypted based at least on a period of time since the original FMKID was stored. The subject technology re-encrypts the data using a new encryption key associated with a new FMKID. The subject technology generates a mapping from the original FMKID to the new FMKID. The subject technology stores the mapping in a metadata database, the mapping being associated with a re-encrypted file, the re-encrypted file including the re-encrypted data.
Owner:SNOWFLAKE INC
Compression of logical-to-physical address indirect mapping tables on solid state disks
PendingCN121195246AMemory architecture accessing/allocationInput/output to record carriersComputer architectureLeast significant bit
The present application is directed to compressing a logical-to-physical (L2P) address indirect mapping table in a memory system of an electronic device. The electronic device determines a plurality of physical addresses corresponding to an ordered sequence of logical addresses. Each logical address corresponds to a distinct physical address. The electronic device identifies a most significant bit (MSB) set and a least significant bit (LSB) set for each of the plurality of physical addresses, and determines a set of data bits based on a plurality of MSB sets including the MSB set for each of the plurality of physical addresses. The set of LSBs and the set of data bits for each of the plurality of physical addresses are jointly stored in the L2P address indirect mapping table.
Owner:SK HYNIX NAND PRODUCT SOLUTIONS CORP
Method for managing a cache memory
ActiveUS12292830B2Memory architecture accessing/allocationMemory adressing/allocation/relocationTerm memoryData mining
This method comprises:selecting, depending on an address of a word to be read or written, a first cell in an indirection table and using, as first value generated for a line index, the value contained in this first cell, andin response to triggering of a cache miss:storing the word retrieved from a memory of higher rank in a new line identified by a second line-index value, this second value being contained in a second cell of the indirection table, andpermutating, in the indirection table, only values contained in the first and second cells, so that after this permutation the first cell contains the second value and the second cell contains the first value.
Owner:COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Methods for Mimicking Multi-Level Instancing with Non-Transforming Light-Weight Instances
PendingUS20260179169A1Processor architectures/configurationImage generationComputer hardwareParallel computing
Hardware support for light-weight instances achieve the effect of multi-level instancing without incurring associated performance or area cost, enabling a Cluster-Level AS (CLAS) to be used for a faster build speed. The same subdivision mechanism can also be used to reduce the complexity of the TLAS build by dividing instances into groups. Pseudo-Instance Nodes (PIN) allow for an indirection from a BVH node to any arbitrary location of a child complet. Multi-Parent Root Complets (MPRC) allow for any CLAS to be reused across multiple BLASs.
Owner:NVIDIA CORP
Approach for providing indirect addressing in memory modules
ActiveUS12360912B2Memory architecture accessing/allocationMemory adressing/allocation/relocationSoftware engineeringPhysical address
An approach provides indirect addressing support for PIM. Indirect PIM commands include address translation information that allows memory modules to perform indirect addressing. Processing logic in a memory module processes an indirect PIM command and retrieves, from a first memory location, a virtual address of a second memory location. The processing logic calculates a corresponding physical address for the virtual address using the address translation information included with the indirect PIM command and retrieves, from the second memory location, a virtual address of a third memory location. This process is repeated any number of times until one or more indirection stop criteria are satisfied. The indirection stop criteria stop the process when work has been completed normally or to prevent errors. Implementations include the processing logic in the memory module working in cooperation with a memory controller to perform indirect addressing.
Owner:ADVANCED MICRO DEVICES INC
Composite aggregate architecture
PendingUS20260064299A1Memory architecture accessing/allocationInput/output to record carriersHard disc driveSolid-state storage
Techniques are provided for providing a storage abstraction layer for a composite aggregate architecture. A storage abstraction layer is utilized as an indirection layer between a file system and a storage environment. The storage abstraction layer obtains characteristic of a plurality of storage providers that provide access to heterogeneous types of storage of the storage environment (e.g., solid state storage, high availability storage, object storage, hard disk drive storage, etc.). The storage abstraction layer generates storage bins to manage storage of each storage provider. The storage abstraction layer generates a storage aggregate from the heterogeneous types of storage as a single storage container. The storage aggregate is exposed to the file system as the single storage container that abstracts away from the file system the management and physical storage details of data of the storage aggregate.
Owner:NETAPP INC
Rekeying using indirection layer for dynamic key ID lookup
The subject technology stores an original file master key identifier (FMKID) in metadata associated with an encrypted file, the encrypted file including data. The subject technology determines that the encrypted file is to be re-encrypted based at least on a period of time since the original FMKID was stored. The subject technology re-encrypts the data using a new encryption key associated with a new FMKID. The subject technology generates a mapping from the original FMKID to the new FMKID. The subject technology stores the mapping in a metadata database, the mapping being associated with a re-encrypted file, the re-encrypted file including the re-encrypted data.
Owner:SNOWFLAKE INC
Techniques for directed data migration
A host stores “context” metadata for logical block addresses (LBAs) in a manner tied to physical location. Notwithstanding log-structured or copy on write processes, the host is then provided with immediate context when the host is called upon to assist a memory controller with data identified by physical location, for example, for memory reconfiguration, garbage collection, wear leveling or other processes. The metadata for example can provide the host with insight as to which data may be moved to enhance performance optimization and where that data can be placed. In one embodiment, the host writes back one or more references that span multiple layers of indirection in concert with write of the underlying data; in another embodiment, the context can point to other metadata.
Owner:RADIAN MEMORY SYSTEMS INC
Methods and systems for storing data in a memory device having dynamic namespace with different indirection unit sizes
A system and method for storing data in a memory device. The method includes transmitting, to a host, information indicative of a first allowable maximum size of a first namespace associated with a first IU and a second allowable maximum size of a second namespace associated with a second IU. The first and the second IUs may be of different sizes. The includes comprise receiving configuration information comprising one or more instructions to: generate a first L2P table associated with the first IU based on the first allowable maximum size, and generate a second L2P table associated with the second IU based on the second allowable maximum size and generating the first L2P table and the second L2P table based on the configuration information; and causing first data and second data to be stored in the first namespace and the second namespace using the first and second L2P tables respectively.
Owner:SK HYNIX NAND PRODUCT SOLUTIONS CORP