7 results about "Indirection" patented technology

A system and method for storing data in a memory device. The method includes transmitting, to a host, information indicative of a first allowable maximum size of a first namespace associated with a first IU and a second allowable maximum size of a second namespace associated with a second IU. The first and the second IUs may be of different sizes. The includes comprise receiving configuration information comprising one or more instructions to: generate a first L2P table associated with the first IU based on the first allowable maximum size, and generate a second L2P table associated with the second IU based on the second allowable maximum size and generating the first L2P table and the second L2P table based on the configuration information; and causing first data and second data to be stored in the first namespace and the second namespace using the first and second L2P tables respectively.

Mechanisms, including systems, methods, and media, for processing sub-indirection unit sized data in a solid-state drive (SSD) are provided, the methods including: identifying, in a first portion of storage of the SSD, a plurality of indirection units each containing sub indirection-unit-sized data and padding; combining the plurality of indirection units into a page-size data structure using a hardware processor; copying contents of the page-sized data structure to a second portion of storage of the SSD; and updating a data structure relating logical address of data to physical locations of data so that an entry corresponding to the sub-indirection-unit sized data of one of the plurality of indirection units changes from having a physical address in the first portion of storage to having a physical address in the second portion of storage.

Mechanisms, including systems, methods, and media, for processing sub-indirection unit sized data in a solid-state drive (SSD) are provided, the methods including: identifying, in a first portion of storage of the SSD, a plurality of indirection units each containing sub-indirection-unit-sized data and padding; combining the plurality of indirection units into a page-size data structure using a hardware processor; copying contents of the page-sized data structure to a second portion of storage of the SSD; and updating a data structure relating logical address of data to physical locations of data so that an entry corresponding to the sub-indirection-unit-sized data of one of the plurality of indirection units changes from having a physical address in the first portion of storage to having a physical address in the second portion of storage.

Mechanisms, including systems, methods, and media, for processing sub-indirection unit sized data in a solid-state drive (SSD) are provided, the methods including: identifying, in a first portion of storage of the SSD, a plurality of indirection units each containing sub-indirection-unit-sized data and padding; combining the plurality of indirection units into a page-size data structure using a hardware processor; copying contents of the page-sized data structure to a second portion of storage of the SSD; and updating a data structure relating logical address of data to physical locations of data so that an entry corresponding to the sub-indirection-unit-sized data of one of the plurality of indirection units changes from having a physical address in the first portion of storage to having a physical address in the second portion of storage.

This application is directed to compressing a logical-to-physical (L2P) address indirection table in a memory system of an electronic device. The electronic device determines a plurality of physical addresses corresponding to an ordered sequence of logical addresses. Each logical address corresponds to a distinct physical address. The electronic device identifies a set of most significant bits (MSBs) and a set of least significant bits (LSBs) of each of the plurality of physical addresses and determines a set of data bits based on a plurality of MSB sets including the set of MSBs of each of the plurality of physical addresses. The set of LSBs of each of the plurality of physical addresses and the set of data bits are stored jointly in the L2P address indirection table.

Hardware support for light-weight instances achieve the effect of multi-level instancing without incurring associated performance or area cost, enabling a Cluster-Level AS (CLAS) to be used for a faster build speed. The same subdivision mechanism can also be used to reduce the complexity of the TLAS build by dividing instances into groups. Pseudo-Instance Nodes (PIN) allow for an indirection from a BVH node to any arbitrary location of a child complet. Multi-Parent Root Complets (MPRC) allow for any CLAS to be reused across multiple BLASs.

A system and method for storing data in a memory device. The method includes transmitting, to a host, information indicative of a first allowable maximum size of a first namespace associated with a first IU and a second allowable maximum size of a second namespace associated with a second IU. The first and the second IUs may be of different sizes. The includes comprise receiving configuration information comprising one or more instructions to: generate a first L2P table associated with the first IU based on the first allowable maximum size, and generate a second L2P table associated with the second IU based on the second allowable maximum size and generating the first L2P table and the second L2P table based on the configuration information; and causing first data and second data to be stored in the first namespace and the second namespace using the first and second L2P tables respectively.