10 results about "Transactional memory" patented technology

Systems and methods for managing divergence of best effort transactional support mechanisms in various transactional memory implementations using a portable transaction interface are described. This interface may be implemented by various combinations of best effort hardware features, including none at all. Because the features offered by this interface may be best effort, a default (e.g., software) implementation may always be possible without the need for special hardware support. Software may be written to the interface, and may be executable on a variety of platforms, taking advantage of best effort hardware features included on each one, while not depending on any particular mechanism. Multiple implementations of each operation defined by the interface may be included in one or more portable transaction interface libraries. Systems and / or application software may be written as platform-independent and / or portable, and may call functions of these libraries to implement the operations for a targeted execution environment.

A network flow processor integrated circuit includes a plurality of processors, a plurality of multi-threaded transactional memories (MTMs), and a configurable mesh posted transaction data bus. The configurable mesh posted transaction data bus includes a configurable command mesh and a configurable data mesh. Each of these configurable meshes includes crossbar switches and interconnecting links. A command bus transaction value issued by a processor can pass across the command mesh to an MTM. The command bus transaction bus value includes a reference value. The MTM uses the reference value to pull data across the configurable data mesh into the MTM. The MTM then uses the data to carry out the commanded transactional memory operation. Multiple such commands can pass across the posted transaction bus across different parts of the integrated circuit at the same time, and a single MTM can be carrying out multiple such operations at the same time.

In one embodiment, an apparatus couples to a host processor over a Compute Express Link (CXL)-based link. The apparatus includes a transaction queue to queue memory transactions to be completed in an addressable memory coupled to the apparatus, a transaction cache, conflict detection circuitry to determine whether a conflict exists between memory transactions, and transaction execution circuitry. The transaction execution circuitry may access a transaction from the transaction queue, the transaction to implement one or more memory operations in the memory, store data from the memory to be accessed by the transaction operations in the transaction cache, execute operations of the transaction, including modifying data from the memory location stored in the transaction cache, and based on completion of the transaction, cause the modified data from the transaction cache to be stored in the memory.

Methods and apparatus relating to a system architecture and techniques for pinned memory migration are described. In an embodiment, one or more memory devices store a source page and a destination page. Logic circuitry causes a write operation from an Input / Output (I / O) device to be observed for both the source page and the destination page. A transactional memory copy operation is to be performed from the source page to the destination page. Other embodiments are also disclosed and claimed.

A computer system (1101) for preventing a prefetch memory operation from causing a transaction to abort, the computer system (1101) comprising: one or more computer processors (804), one or more computer-readable storage media, and program instructions stored on the one or more computer-readable storage media for execution by at least one of the one or more computer processors (804), the program instructions comprising: Program instructions for receiving a pre-access request (4416) from a remote processor by a local processor; Program instructions for determining whether the prefetch request (4416) conflicts with a transaction of the local processor; Program instructions for responding to at least one of i) a determination that the local processor does not have a transaction and ii) a determination that the prefetch request (4416) does not conflict with a transaction by providing the requested prefetch data; and Program instructions for responding to a determination that the pre-access request (4416) conflicts with a transaction by suppressing processing of the pre-access request (4416), wherein the computer system (1101) comprises a transaction-bound memory system (A1104), and further wherein into the transactional memory system (A1104) non-prefetch operations (ie non-prefetch memory accesses) on a non-prefetch bus (2210) and prefetch operations (iePrefetch request memory accesses) on a bus for prefetch operations (2209), and an address decryption device (2211) decrypts the address of a non-prefetch operation and confirms the target address of a non-prefetch read operation on a read address bus (2201) and the target address of a non-prefetch write operation on a write address bus (2202), and further an address decryption device (2212) decrypts the address of a prefetch operation and confirms the target address of a prefetch read operation on a bus for a prefetch read address (2203) and the target address of a prefetch write operation on a bus for a prefetch write address (2204), and the prefetch manager (2208) is connected to an abort manager (2207) and receives all prefetch operations (2209) that are input to the transactional memory system (A1104) from the prefetch bus (2209).

Methods and apparatus relating to system architectures and techniques for fixed memory migration are described. In an embodiment, one or more memory devices store a source page and a destination page. Logic circuitry causes write operations from an input / output (I / O) device to be observed for both a source page and a destination page. A transactional memory copy operation is performed from a source page to a destination page. Other embodiments are also disclosed and claimed.

A neural processing device and transaction tracking method thereof are provided. The neural processing device comprises a first set of a plurality of neural cores, a shared memory shared by the first set of the plurality of neural cores, and a programmable hardware transactional memory (PHTM) configured to receive a memory access request directed to the shared memory from the first set of the plurality of neural cores and configured to commit or buffer the memory access request.

This invention relates to a data processing system (100) and a data processing method. The data processing system (100) is used to execute hardware transactional memory (HTM) transactions. The data processing system (100) includes a byte-addressable non-volatile memory (101) for persistently storing data; and a processor (103) for performing atomic HTM write operations related to submitting the HTM transaction by writing an indication flag indicating successful submission of the HTM transaction to the non-volatile memory (101).

A neural processing device and transaction tracking method thereof are provided. The neural processing device comprises a first set of a plurality of neural cores, a shared memory shared by the first set of the plurality of neural cores, and a programmable hardware transactional memory (PHTM) configured to receive a memory access request directed to the shared memory from the first set of the plurality of neural cores and configured to commit or buffer the memory access request.

The invention discloses a data security protection system for a hardware persistent transactional memory, belongs to the technical field of computer system memory security protection, and aims to solve the problems of high counter access and persistent overhead in a data encryption scheme in an existing hardware persistent transactional memory. The data security protection system provided by the invention adopts a hybrid encryption method of the lightweight counters, so that the number and overhead of the counters required by data encryption are reduced. In addition, in order to solve the problem of high overhead of bonsai Merkel tree node updating in an existing data integrity guarantee scheme in a hardware persistent transactional memory, the invention provides a dual-hash integrity guarantee method for a transaction revocation log and a staged integrity guarantee method for transaction local data. Expensive bonsai Merkel tree node updating on a transaction execution critical path is removed, and efficient integrity guarantee is achieved.