14 results about "Embedded hardware" patented technology

An integrated circuit (IC) chip includes a first memory storing first information and a second memory storing second information that needs to be protected against unauthorized access. A communication interface circuitry provides a processor external to the IC chip with read and / or write access to components of the IC chip. An embedded hardware security circuitry selectively provides the processor external to the IC chip with secure access to the second memory. Interconnect circuitry i) selectively grants the processor insecure access to the first memory via the communication interface circuitry, ii) selectively grants the processor secure access to the embedded hardware, and iii) restricts access to the second memory.

The application discloses a kind of hysteresis reference window sliding window adaptive threshold surge detection system and method, belong to aero-engine surge detection field.The method includes: real-time acquisition aero-engine pressure sensor output analog voltage signal, and carry out partial pressure, filtering and analog-digital conversion, obtain discrete sampling sequence;With sliding window intercept analysis window and carry out linear fitting, calculate its slope and residual standard deviation;Established by historical analysis window eigenvalue, with current window maintains hysteresis distance reference window;Based on the statistics of eigenvalue sequence in reference window, dynamically calculate adaptive threshold;By comparing current window eigenvalue with threshold value, and when the eigenvalue of continuous multiple windows exceeds threshold value, determine surge.The detection scheme provided by the application significantly reduces the amount of calculation through local window processing and dynamic threshold adjustment, solves the problem that existing algorithms are difficult to be deployed in real time in embedded hardware, and improves the detection accuracy and working condition adaptability.

The present application relates to the field of vehicle electronic control and active safety technology, and proposes a kind of vehicle driver incapacitation emergency control system and method.It includes: through driver monitoring camera and processing unit, based on eyelid closure degree and driving operation signal joint determination driver incapacitation, automatically trigger emergency response state;In response to the state, wake up forward perception unit to identify lane line and shoulder area;Local decision unit executes a finite state machine, sequentially executes lighting double flash warning light, speed gradually reduces and lane keeps based on lane line detection, and after vehicle speed reduces to threshold, guide vehicle to right side safe shoulder lane change and brake parking, while sending alarm message to terminal server in parallel to prepare subsequent remote manual takeover.The present application can fundamentally solve the timeliness and reliability problem of emergency control after driver sudden incapacitation without relying on driver active operation and remote communication large cycle, and can be deployed only with low-cost embedded hardware.

The embodiments of the present disclosure provide a kind of intelligent control method, device, equipment and medium of lightweight embedded end, method includes receiving control instruction for embedded hardware device, and the instruction mapping prompt word of pre-set is spliced with control instruction, generates instruction prompt text;Instruction prompt text is encapsulated into the session request data packet that meets the specification of cloud big language model, and session request data packet is sent to cloud big language model, to make cloud big language model parse session request data packet, and generate corresponding structured execution instruction under the guidance of instruction mapping prompt word based on control instruction, and generate session reply data packet based on structured execution instruction;Receive the session reply data packet that cloud big language model currently returns, and parse session reply data packet and obtain structured execution instruction;Based on structured execution instruction, the corresponding operation is executed, so as to improve the response speed of hardware device, improve the intelligent control experience effect of user.

This invention discloses a robot path planning method and system based on field-programmable gate array (FPGA) acceleration, belonging to the field of path planning and embedded hardware acceleration technology. The method includes: constructing a path fitness function based on a two-dimensional occupancy grid map of the robot's working environment; iteratively optimizing a population of anchor-point quasi-reflective artificial protozoan optimization algorithms using a collaborative architecture of programmable logic and processing system, where each individual in the population represents a candidate robot path containing multiple path nodes, and the candidate robot path corresponding to the final globally optimal individual is taken as the optimal path; the programmable logic side is used to perform hardware-accelerated fitness evaluation of the candidate robot paths corresponding to the individuals using the path fitness function; and the processing system side is used to update the individuals based on the fitness value of their corresponding candidate robot paths. This method can achieve fast, accurate, and stable path planning results in complex obstacle scenarios.

This invention discloses an edge medical emergency signal encryption processing method based on a race-sleep strategy, relating to information security technology and embedded hardware acceleration technology. The method includes the following steps: S1, real-time monitoring of the number K of physiological data blocks to be encrypted in the data input buffer; S2, comparing the number K of data blocks with a preset minimum start threshold, and generating a global wake-up pulse when K ≥ 0; S3, responding to the global wake-up pulse, causing the fully expanded pipeline layer to transition from a sleep state to a full-speed running state, and sequentially injecting K data blocks into the fully expanded pipeline layer for encryption processing. This invention originates from the fully expanded architecture, which eliminates iterative feedback loops and, in conjunction with a deep pipeline, cuts off critical paths. By spatially instantiating R round function units, it achieves the output of a complete ciphertext block per clock cycle, improving throughput while reducing power consumption.

The application discloses an online carrier magnetic compensation method based on an HLS tool, and aims at solving the problem of the ill-conditioned coefficient of traditional carrier magnetic compensation, wherein by researching the main source of magnetic interference, the influence of the eddy current field is ignored, the original model is simplified, a three-component magnetic compensation model is established, and thus the online carrier compensation method of the magnetic field component is proposed. Meanwhile, the method is embedded in the hardware simulation by using the high-level synthesis (HLS) tool of FPGA, the real-time performance and compensation accuracy of the method in the hardware system are verified, and the online carrier magnetic compensation has important practical significance.

This invention discloses an embedded hardware-software co-operated real-time operating system, including a main core, a coprocessor, and shared memory. The shared memory is mounted on a bus, allowing both the main core and the coprocessor to access it. The coprocessor is configured to perform RTOS task scheduling, determining tasks to be executed and storing the task control block of the task to be executed in the physical address space of the shared memory. The task control block includes task parameters for the task to be executed. It also updates a pointer structure to indicate the task control block corresponding to the currently executed task. The main core is configured to determine the indicated task control block based on the pointer structure and execute the task corresponding to that task control block. Task scheduling is exclusively performed by the coprocessor; the main core does not perform RTOS task scheduling. This invention uses a dedicated coprocessor to perform task scheduling and hardware triggers and pointers to achieve deterministic task synchronization between the main core and the coprocessor.

A cloud-edge-device collaborative intelligent cabinet management system includes a cloud server, an edge computing gateway, a low-level embedded hardware execution unit, and an integrated multi-sensor anti-tampering module. The integrated multi-sensor anti-tampering module is independently fixed in a concealed location within the cabinet and connects to the edge computing gateway via an encrypted independent communication link. It monitors physical tampering behavior within the cabinet in real time and triggers multi-level alarms and emergency locking responses, forming an integrated online and offline physical security protection system. This invention achieves highly reliable dual protection and communication fault tolerance mechanisms through a three-level cloud-edge-device collaborative architecture and offline self-healing architecture, combined with end-to-end remote seamless upgrade technology.

1. The name of the design product: core board. 2. The use of the design product: highly integrated embedded hardware module, used for rapid development of intelligent equipment, mainly used for intelligent home, security, industrial control host or sensor equipment mainboard. 3. The design points of the design product: in shape. 4. The picture or photo that best indicates the design points: perspective view.

This application provides a display system for a cleaning robot and a cleaning robot in general. The display system includes a processor and a display panel in the cleaning robot. The display panel includes a microcontroller and a dot matrix display board. The processor is connected to the microcontroller, and the microcontroller is connected to the dot matrix display board. The dot matrix display board is positioned on the front of the cleaning robot and faces the same direction as the robot's movement. The processor determines the dot matrix display data corresponding to the information to be displayed and sends the dot matrix display data to the microcontroller. The microcontroller sends the dot matrix display data to the dot matrix display board, causing the dot matrix display board to display the information to be displayed. This allows the rendering task of displaying information to be transferred from the microcontroller to other devices. The microcontroller does not need an external high-capacity storage chip, reducing the performance requirements of the microcontroller, lowering embedded hardware costs and manual maintenance costs, supporting richer display information and displaying it to surrounding users, and improving the human-computer interaction effect of the cleaning robot.

This invention relates to the field of fluid mechanics, specifically to a method for constructing a high-pressure fluid model. The method includes: acquiring multi-scale fluid data, including molecular dynamics data, experimental-scale data, and in-situ detection data; transferring data from the low- and medium-pressure domains to the ultra-high-pressure domain using a pressure-gradient transfer learning network, and outputting predicted values ​​of physical property parameters; receiving in-situ data in real time using embedded hardware and calculating correction factors; dynamically reconstructing the source terms of the fluid control equations based on the correction factors; and triggering a reinforcement learning optimizer to reconstruct the model equations when the average relative error exceeds a threshold. The purpose of this invention is to provide a method, computer equipment, and storage medium for constructing a high-pressure fluid model, solving many problems in the prior art and demonstrating significant advantages in the accuracy, real-time performance, and adaptability of the fluid model, providing strong technical support for research and applications in related fields.

A computer-implemented system for creating a graphical user interface (GUI) for an embedded hardware platform is provided. The system may include a design importer to import a structured data file representing a vector-based design, parse the structured data file into graphical elements, and render the graphical elements in a no-code visual interface, the no-code visual interface to allow codeless interaction and modification of the imported graphical elements, and a code generator to generate source code in a programming language based on the modified graphical elements and provide the generated source code to one or more simulators for testing functionality of the GUI.