531results about How to "Improve computing power" patented technology

The invention discloses a mobile phone screen glass defect detection method based on improved YOLOv8, and relates to the technical field of mobile phone screen glass cover plate quality detection. The method comprises the following steps: simulating an industrial production environment, collecting mobile phone screen glass images, and constructing a data set; improvement and optimization are carried out on the basis of the YOLOv8 target detection network model, a mobile phone screen glass defect detection classification model is constructed, and parameters are trained and optimized; constructing a semantic segmentation model of the YOLOv8 network, segmenting the defects of the mobile phone screen glass image to be identified, and realizing detection and identification of different defect category edges; and fitting the actual damage size of the mobile phone screen glass defect range. The mobile phone screen glass defect detection system is suitable for accurate detection of mobile phone screen glass defect characteristics, can measure the defect range, and provides intelligent and efficient services for the mobile phone screen glass quality inspection process.

The invention discloses an RISC-V vector optimization method, device and equipment based on thread scheduling, relates to the field of digital integrated circuit design, and is used for solving the problems of operation resource waste, relatively low operation efficiency and performance reduction caused by memory access performance limitation in the prior art. Comprising the following steps: acquiring an RISC-V vector instruction, extracting decoding information from the RISC-V vector instruction, and acquiring register configuration information in a vector state; determining thread scheduling information according to the decoding information, the register configuration information, the current thread execution state and hardware configuration; executing a corresponding thread task according to the thread scheduling information; after execution is finished, if the thread task of the current instruction is executed, updating the state and delivering the current instruction; otherwise, updating the state and executing the next thread task until all the thread tasks are executed, writing back the data, completing instruction delivery and ending the instruction cycle. According to the method, the vector instruction execution performance under memory access performance limitation can be effectively improved, and the overall operation performance is improved.

The invention discloses a client information management method based on a cloud environment and a related device, and relates to the technical field of data processing, and the method comprises the steps: carrying out the information safety analysis based on a client information composition parameter generated through the information composition analysis of client information, and obtaining an information safety parameter; acquiring category identification information of the customer information based on the category logic chain, and acquiring corresponding local density based on the preset information field and the category identification information; classifying the customer information based on the local density and the information security parameters; the client information of each category is stored and encrypted; obtaining a mapping relationship between the storage performance information and the encrypted customer information of each category, and determining an information storage strategy based on the mapping relationship in combination with a node partitioning strategy; and storing the encrypted customer information of each category into a storage node corresponding to a cloud storage center. According to the invention, the reliability of classified storage of the customer information is improved, and the classified storage of the customer information achieves a more ideal effect.

The invention discloses a sensing, storing and computing integrated visual system based on a photoelectric synapse device and a memristor device, and belongs to the field of intelligent vision and brain-like computing. The image sensing module is used for converting two-dimensional image information of an image to be detected into a two-dimensional electric signal by utilizing the matrix arrangement photoelectric synapse device, and preprocessing the two-dimensional electric signal; the array memristor-based image recognition module is used for receiving the preprocessed two-dimensional electric signals, standardizing the two-dimensional electric signals to obtain an image feature matrix by using a memristor array structure, inputting the feature matrix into a multi-layer convolutional neural network, and performing matrix operation on the input feature matrix for multiple times by the multi-layer convolutional neural network to obtain an image feature matrix; and further extracting image feature information, and finally outputting an image recognition result. The visual system can be widely applied to the field of image sensing and recognition, and has the characteristics of blurred image enhancement, high recognition rate and the like.

The invention discloses a water quality detection method and system based on artificial intelligence. The method comprises the steps of data collection, data preprocessing, water quality pre-classification, water quality trending analysis, pollution traceability prediction and water quality detection. The invention relates to the technical field of water quality detection, in particular to a water quality detection method and system based on artificial intelligence, and the scheme adopts an artificial intelligence water quality detection method including water quality pre-classification, trend analysis and pollution tracing; performing water quality pre-classification by adopting a deep neural network method combining a genetic algorithm and a random forest model; performing water quality pre-classification and water quality trend analysis by adopting a deep neural network method combining a genetic algorithm and a random forest model; according to the method, data are classified in advance through a water quality pre-classification task, unpolluted water sources are eliminated, and then the calculation speed and the calculation effect of pollution tracing are improved through a causal enlightenment operator and an improved graph neural network in combination with a causal enlightenment graph neural network.

The invention provides a prediction method for the remaining service life of a rolling bearing based on transfer learning, and belongs to the technical field of artificial intelligence and mechanical engineering. Rolling bearing vibration signals are obtained, and a data set is constructed and divided into a source domain and a target domain; constructing a prediction model of the remaining service life of the rolling bearing; the model comprises the following steps: obtaining low-dimensional features and model weights by using a coding layer; the coding layer comprises a multi-head self-attention sub-layer used for obtaining a relationship between features and a model weight; the feedforward mechanism is used for obtaining low-dimensional mapping; predicting the residual life of the bearing by using the feature representation output by the last coding layer through the full connection layer; training the prediction model of the remaining service life of the rolling bearing: calculating the difference between a source domain and a target domain by using the data set, and constructing a loss item; weight parameters are added to the loss item, the weight parameters and the root-mean-square error loss item are added for back propagation, and the model weight is updated. And the generalization ability of predicting the bearing life by the model is improved.

The invention provides a collaborative computing method, system and device based on SIMD and SIMT, and belongs to the technical field of computer processing. The method is applied to a Warp composed of a plurality of SPs, and the Warp comprises an SIMT front end and an SIMD rear end. Each SP corresponds to a vector register combined by a plurality of short registers; generating instruction fetching indication information under the condition that a thread bundle scheduler at the front end of the SIMT determines that a first thread bundle corresponding to the calculation task is in an activated state; obtaining a first cache instruction corresponding to the first thread bundle through an instruction fetching unit, and sending the first cache instruction to a decoding unit at the front end of the SIMT for analysis; obtaining one or more corresponding required operands through an operand collection unit at the rear end of the SIMD; and distributing the required operands to the corresponding calculation management units through the SIMD rear end to execute the corresponding calculation tasks, and writing the calculation results corresponding to the calculation tasks back to the storage unit through the write-back unit.

The invention relates to an intelligent behavior analysis and anomaly detection system for Internet of Things security, which is applied to the technical field of Internet of Things security, and comprises a data acquisition module, a data preprocessing module, a behavior modeling module and an anomaly detection module, the data preprocessing module cleans the data, the behavior modeling module generates a vector sequence of equipment behaviors through feature embedding and position coding, and the anomaly detection module analyzes time sequence association of the equipment behaviors by utilizing a self-attention mechanism and a multi-head attention mechanism and judges whether the equipment has abnormal behaviors or not. The cooperative defense module realizes cross-device cooperative defense through an edge detection unit and a cloud analysis unit, and the threat intelligence sharing module realizes sharing and updating of threat intelligence through a local intelligence database and an external intelligence interface. And the response module carries out automatic defense and notifies a system administrator through the automatic defense unit and the alarm unit when an abnormity is detected.

The invention belongs to the technical field of artificial intelligence, and particularly relates to a GPU (Graphics Processing Unit) and NPU (Network Processing Unit) resource scheduling method for high-performance computing, which comprises the following steps of: waiting for a scheduling optimization module to call acquired resource condition data of GPU and NPU hardware accelerators; the task analysis module analyzes a to-be-executed AI calculation task, obtains task feature data and transmits the task feature data to the scheduling optimization module; the scheduling optimization module calculates an optimal task allocation scheme and transmits the optimal task allocation scheme to the dynamic scheduling module; the dynamic scheduling module monitors task execution conditions and resource changes in real time, dynamically adjusts a task allocation scheme according to feedback information, and feeds back the task allocation scheme to the scheduling optimization module; meanwhile, the dynamic scheduling module feeds back the change information of the resource condition data and the task execution condition to the resource monitoring module and the task analysis module respectively; according to the method, dynamic scheduling is carried out on heterogeneous hardware accelerators such as the GPU and the NPU, respective advantages are fully exerted, and the overall calculation performance is improved.

The invention provides an electric power visual knowledge distillation method and system, and the method comprises the steps: collecting electric power visual image data, and building an electric power visual data set; inputting the electric power visual data set into a first model for training to obtain a teacher model; constructing a second model, combining a detection framework of the teacher model with a backbone network of the second model, and constructing a student model; inputting the electric power visual data set into the teacher model and the student model at the same time to obtain output results, and calculating the difference degree between the output results of the teacher model and the student model by using a composite loss function; using a back propagation algorithm and an Adam optimizer to update parameters of the student model according to the difference degree; and enabling the difference degree to be smaller than a set value through a plurality of rounds of iteration, and outputting a student model. According to the method, on the premise that resource consumption is greatly reduced, the obtained student model has higher calculation speed, recognition precision close to that of a teacher model and smaller model size, and the electric power visual knowledge distillation system is suitable for various resource-constrained environments.

The invention relates to the field of nonvolatile memories, in particular to an SOT-MRAM circuit unit based on a 2T2M differential structure and a storage array circuit of the SOT-MRAM circuit unit. The SOT-MRAM unit comprises a first magnetic tunnel junction, a second magnetic tunnel junction, a first field effect transistor, a second field effect transistor, a first phase inverter, a second phase inverter, a write line, a read line, an input line and an output line which have a specific connection relation. According to the SOT-MRAM circuit unit, through the special 2T2M differential structure design and in combination with the excellent performance of a spin-orbit moment magnetic tunnel junction, the storage and operation performance and efficiency of a 2T2MSOT-MRAM differential circuit unit array are integrally improved, the dependence on the performance of the MTJ is reduced, the SOT-MRAM circuit unit has the better energy efficiency ratio and the more stable read-write speed and precision, and the SOT-MRAM circuit unit has the advantages of being simple in structure, low in cost and high in reliability. And the reliability and the stability are excellent.

The invention relates to a homology analysis method and device for binary code files and computer equipment. The method comprises the following steps: obtaining and identifying a function call graph corresponding to each binary code file through a security monitoring program; identifying isomorphic sub-graphs among the binary code files through a hybrid search strategy, and performing symbol program slicing processing on respective write function nodes in each isomorphic sub-graph to obtain symbol program slicing codes corresponding to the respective write function nodes of each isomorphic sub-graph; performing escape processing on each symbol program slice code corresponding to the isomorphic sub-graph to obtain each piece of mathematical semantic information corresponding to the isomorphic sub-graph, and performing similarity calculation to obtain a code similarity value between the binary code files; therefore, the homologous binary code file is identified. By adopting the method, the homology analysis accuracy of the highly confused binary code file can be improved.

The invention relates to the technical field of unmanned aerial vehicles, and discloses an unmanned aerial vehicle attitude control method and system based on flight aerodynamic stability, and the method comprises the steps: constructing a flight control model, collecting a system attitude angle, setting an ideal attitude angle, calculating an attitude angle error, setting a proportion parameter, an integral parameter and a differential parameter, generating an attitude control signal, and setting collection time. The method comprises the steps of continuously collecting flight wind speed and flight angle of attack, setting aerodynamic resistance parameters and aerodynamic moment parameters, calculating aerodynamic moment disturbance, obtaining the surface area of the unmanned aerial vehicle, calculating aerodynamic disturbance, setting a proportion upper limit, an integral upper limit and a differential upper limit, and dynamically adjusting to obtain adjustment proportion parameters, adjustment integral parameters and adjustment differential parameters. And generating an update control signal based on the adjustment proportion parameter, the adjustment integral parameter and the adjustment differential parameter to complete unmanned aerial vehicle attitude control. The precision of unmanned aerial vehicle attitude control can be improved.

The invention discloses a power grid supply chain distribution network protocol inventory material demand prediction method based on a time sequence model, and belongs to the field of data processing. Comprising the steps of data collection and preprocessing; determining a dimension establishment model; model prediction; and correcting the model. The method comprises the following steps: introducing a time sequence model into power grid supply chain demand prediction, and establishing a time sequence model suitable for power grid supply chain distribution network protocol inventory material demands; by means of a big data analysis method and an artificial intelligence algorithm, an association rule of project and demand prediction is mined, a material demand characteristic portrait is formed by using a data analysis method, and through historical data cleaning, model establishment and event management, the material characteristic portrait is carded, analyzed, diagnosed and evaluated in an all-around and multi-view manner. The operation capability and the data applicability of an algorithm model library are improved, a material demand prediction mode is optimized and evaluated, and a support is provided for a power grid supply chain material purchase supply decision. The method can be widely applied to the field of power grid supply chain distribution network protocol inventory material demand prediction and management.

The embodiment of the invention provides a hardware processing device for a digital signature algorithm. The device comprises a control logic module, a hash module, a lattice calculation module, a signature logic module and an authentication logic module, the control logic module is used for receiving input data and inputting the input data into the hash module to generate a random polynomial; inputting the random polynomial generated by the hash module into a lattice calculation module for lattice operation; calling the signature logic module to sign the lattice operation result to generate a signature value; and calling the authentication logic module to verify the validity of the signature value. According to the embodiment of the invention, the lattice hash module and the calculation module are independently provided instead of being placed in the signature logic module and the authentication logic module, so that the control logic module can directly call the hash module to generate the random polynomial and call the lattice calculation module to carry out lattice operation, the utilization rate of resources is improved, the operation speed of an algorithm is optimized, and the operation efficiency is improved. And the overall calculation performance is improved.

The invention belongs to the technical field of embedded hardware acceleration and computer vision, and relates to a quantitative lightweight neural network hardware accelerator and a design method thereof. The hardware accelerator comprises a top-layer control module, a memory control module, a reconfigurable memory, an input data preprocessing module, a core computing unit and a post-processing module; the memory control module controls the reconfigurable memory to send data information to the top-layer control module, the input data preprocessing module and the post-processing module; the input data preprocessing module is used for data and weight preparation; and the core calculation unit is used for completing data preparation, weight preparation and post-processing through a multiplier, an adder tree and an accumulator array. The hardware accelerator has higher computing performance, hardware resource utilization rate and data reuse rate; according to the method, the problem of low storage data utilization rate of the input and output cache is solved; hardware operator fusion of a convolution operator and a pooling operator is realized, and storage delay and access power consumption of data reading and writing are reduced.

The invention discloses a three-dimensional heterogeneous integrated optical computing chip, and belongs to the field of optical computing. The computing chip consists of three parts: a spatial diffraction optical neural network core particle, a plane matrix reconfigurable optical neural network component and a plane switchable optical switch module, the single or multiple spatial diffraction optical neural network core particles, the plane matrix reconfigurable optical neural network assembly and the plane switchable optical switch module are combined together in a three-dimensional heterogeneous integration mode, and efficient multi-task optical calculation processing is achieved. The spatial diffraction optical neural network and the plane matrix reconfigurable optical neural network are combined with each other, a traditional optical calculation framework is broken through, the method has wide application prospects in the optical calculation field, and the blank of related technical fields is filled.

The invention provides an effluent quality prediction method and device suitable for remarkable long-period change. The method comprises the following steps: acquiring a monitoring data sequence of a sewage treatment plant; the monitoring data sequence comprises a plurality of historical monitoring data with a preset time interval; performing change period length monitoring on the monitoring data sequence, and determining the correlation condition of each piece of historical monitoring data in the target time; determining a time window based on the correlation condition and a preset screening rule; constructing a training label set based on the time window and preset target prediction time; inputting the training label set into a pre-constructed gated cycle unit (GRU) model for training to obtain an effluent quality prediction model; and inputting current monitoring data of the sewage treatment plant into the effluent quality prediction model, and outputting effluent quality parameters. In the mode, the model has higher computing power under the condition of smaller computing resource requirements, so that the stability of the model is improved, and the effluent quality prediction is more accurate.

The embodiment of the invention provides a secret sharing and packaging method and device. And the plurality of participants respectively encode vectors formed by secret sharing of k pieces of data owned by the participants in a specified domain space to respectively obtain first domain elements owned by the participants, and the first domain elements have data structures meeting addition homomorphism. Then, the multiple participants perform secret sharing addition operation based on first domain elements owned by the multiple participants through first data interaction based on secure multi-party calculation, so that the multiple participants respectively obtain secret sharing of first sum values of the first domain elements owned by the multiple parties; the secret sharing of the first sum value is used as the secret sharing of a second domain element obtained by coding a vector formed by k data in a directional domain space.

The invention relates to a data processing method of a neural network, the neural network and a chip, the data processing method of the neural network comprises the following steps: a weight data storage step: loading weight data into a PIM; a weight data distribution step: distributing the weight data to the corresponding Bank; and a calculation step: performing Mac calculation based on the data of each Bank. The method comprises the following steps of: loading weight data to a process In Memory (PIM) unit, distributing the weight data to different Banks, and carrying out multiply-add (MAC) operation on the basis of data in each Bank. According to the method, data processing and storage are integrated, so that the transmission bottleneck of data from a memory to a processing unit is reduced, the calculation delay and power consumption are reduced, and particularly, the efficiency can be remarkably improved in large-scale neural network calculation.

The invention discloses a signal integrity analysis and optimization method considering electrothermal coupling and parasitic effect in an artificial intelligence chip. According to the method, aiming at a random resistive memory cross array in an artificial intelligence chip, an RRAM compact model is combined to research the influence of device electrothermal coupling and parasitic effect on signal integrity in the cross array, evaluation analysis is carried out, and an optimization scheme is provided. Comprising the following steps: (1) based on a compact model of an RRAM device, establishing an equivalent thermal circuit network to represent an electrothermal coupling effect of a device in a cross array; (2) establishing an interconnection line equivalent circuit model containing parasitic resistance, capacitance and inductance, and extracting parasitic parameters in the model by adopting a partial element equivalent circuit (PEEC) method; (3) analyzing a simulation result, and realizing signal integrity evaluation considering electrothermal coupling, parasitic effect and the like; and (4) proposing an optimization scheme for the problems of parasitic voltage drop and leakage path. The method has important application value in random resistive memories and neuromorphic brain-like chips.

The invention relates to a quantum bit packaging device. The quantum bit packaging device comprises a shell, a substrate, a PCB (Printed Circuit Board) and a connector group, the shell is of a hollow structure and is made of an oxygen-free copper material; the substrate is transversely arranged in the shell, the substrate is of a straight-plate-shaped structure, a preassembling opening is formed in the substrate, and the preassembling opening is suitable for placing a chip; the PCB is transversely arranged in the shell, the PCB is located on the substrate, and the PCB abuts against the substrate; the connector group is arranged on the PCB, the connector is provided with a plurality of connectors, and the plurality of connectors and the PCB are longitudinally inserted. The quantum bit packaging device provided by the invention is high in integration level and easy to carry and deploy. Specifically, the PCB is tightly abutted against the substrate, and the chip is mounted between the substrate and the PCB, so that the overall integration level is high, the electrical connection stability between the components is further improved, and the later maintenance and upgrading work is greatly facilitated.

The invention discloses a multi-bus decoupling distributed embedded hardware rendering architecture, system and method, and relates to the technical field of ultra-high-definition video hardware processing, and the key points of the technical scheme are that the architecture comprises a multi-bus decoupling module which comprises a plurality of hardware buses which are physically isolated from one another, each hardware bus is an exclusive hardware transmission link bearing a single-type manufacturing task; the modular processing unit is an independent hardware board card and is integrated with an external signal input port, an upstream bus signal input port and a downstream bus signal output port; the plurality of modular processing units are cascaded in sequence through a hardware bus in the multi-bus decoupling module to form a distributed assembly line rendering link; when the modular processing units are newly added, the signal processing capability and the rendering synthesis capability are linearly improved along with the increase of the number of the modular processing units. According to the invention, the problem of performance bottleneck of the traditional architecture in processing 4K / 8K ultra-high-definition and multichannel rendering is fundamentally solved.

The invention provides a DNN model-based division and reasoning acceleration method and system for vehicle-mounted edge intelligence. The method comprises the following steps: constructing a DAG graph based on a vehicle-mounted DNN model; constructing an auxiliary network flow graph of the DAG; adding a head node representing local calculation of a vehicle and a tail node representing calculation of an edge server or an auxiliary vehicle, and setting the weight of an edge as time delay overhead for segmenting the edge; obtaining different layering modes of an auxiliary network flow diagram of the DAG and corresponding maximum tolerance point sets meeting local time delay, memory and energy consumption limitation of the vehicle; correspondingly modifying the weight of the edge in the auxiliary network flow graph of the DAG based on each maximum tolerance point set, and calculating the maximum flow of each modified network flow auxiliary graph; and selecting a division mode corresponding to the maximum flow as a DNN model division mode. According to the method, the vehicle and road cloud cooperative reasoning is realized through a DNN model division mode, so that the DNN task cooperative reasoning completion time delay is reduced, and the vehicle safety and the user experience are improved.

The invention discloses a GPGPU thread block synchronization method and device based on a thread lock and a medium, and relates to the technical field of electric digital data processing. The method comprises the following steps: a thread block scheduling module allocates thread blocks for each stream multiprocessor and calculates a thread start ID (Identity) to maintain a corresponding thread lock table; analyzing whether a dependency relationship exists between the memory access request and a thread in the currently occupied thread block or not under the condition that the memory access requirement exists, and if yes, adding the memory access request with the dependency relationship to a lock queue; querying a thread lock state of a thread having a dependency relationship with the memory access request in a corresponding thread lock table so as to add the thread lock state to an entry state corresponding to the lock queue; and dequeuing the memory access request from the lock queue under the condition that the entry states of all the threads with the entries in the lock queue and the thread bundle having the dependency relationship are unlocked, and performing memory access according to the memory access request to realize synchronization of GPGPU thread blocks.

The invention relates to a remote sensing image transmission tower detection method based on MFF-YOLO, and the method comprises the following steps: S1, obtaining a slice data set of a satellite image of a region, screening slice data containing a transmission tower as a data set, and carrying out the image preprocessing; s2, labeling the power transmission tower by utilizing Labelimg software, and obtaining a data set label in an xml (Extensible Markup Language) format; s3, constructing a power transmission tower detection network model based on MFF-YOLO; s4, training and verifying the transmission tower detection network model based on the constructed data set; and S5, on the basis of the trained transmission tower detection network model, detecting a satellite image of a to-be-detected area. According to the invention, the available computing resources can be utilized more efficiently to detect the transmission tower target, and the efficiency and accuracy of transmission tower identification are improved.

The invention relates to the technical field of data processing, in particular to an Internet of Vehicles task unloading and forwarding algorithm based on an MEC and an SDN controller. The real-time states of all vehicles within the coverage range of a roadside unit (RSU) are obtained through an SDN controller, available optimal relay vehicle information is fed back to a current MEC server, the MEC server calculates a global optimal forwarding path by using a bat algorithm, forwarding vehicle node information is sent to a task unloading vehicle, and the task unloading vehicle performs task unloading. And the vehicle unloads and forwards a task which cannot obtain a timely calculation service from the current MEC server to an idle MEC server in a future arrival road section through a forwarding vehicle node for calculation, and when the vehicle with the task unloaded arrives at the server, a calculation result is obtained from the server. The calculation cost and the calculation time delay can be effectively reduced, and the calculation performance and the user experience of the vehicle are improved.

The invention discloses an industrial control computing power expansion method based on a risc-v chip, and relates to the technical field of automation control, and the specific process is as follows: designing computing power expansion hardware based on the risc-v chip, and designing a computing power expansion program algorithm according to the computing power expansion hardware; running a program algorithm on the master controller, and judging whether the computing power and the performance of the master controller can meet a current execution program or not; if the master control can meet the current computing power and kernel framework requirements, executing a program in the master control; if the kernel architecture or the computing power of the main control cannot meet the requirements of the algorithm or the computing power, the corresponding algorithm is distributed to the industrial control board cards corresponding to the architecture and the computing power for calculation based on the architecture executed by the algorithm and the algorithm, real-time data interaction with the main control is carried out, and the industrial control board cards process data in parallel; and the master control outputs a data calculation result. According to the invention, the industrial control board card is expanded on the industrial personal computer through the expansion interface in an integrated mode of the board card, so that the expansion of the computing power is realized, and the cost of a plurality of industrial personal computers is reduced.

The invention discloses a computing system. The computing system comprises a universal processor and a tensor processor, wherein the general processor comprises an instruction scheduling module and at least one calculation unit, and the instruction scheduling module is used for identifying a calculation instruction and sending a tensor operation instruction to the tensor processor when the calculation instruction is identified as the tensor operation instruction; and the tensor processor is used for performing in-memory calculation and / or non-in-memory calculation according to the tensor operation instruction. The invention further provides a calculation method executed by the calculation system, the general processor and the tensor processor are combined together, the general processor is used for processing general calculation in the neural network, the tensor processor is used for carrying out in-memory calculation or non-in-memory calculation, the universality can be guaranteed, the calculation power can be improved, and the calculation efficiency is improved. And a complex and changeable calculation operator in the neural network is supported.

The invention provides a navigation computer for a small inertial navigation system, the size of the navigation computer is only 55mm * 86mm * 16mm, a navigation resolving module, an I / F conversion module and a power supply module are integrated, and the power consumption is less than 3W; the navigation resolving module takes a ZYNQ7000 all-programmable SoC as a core processor, and has the functions of inertial device original data acquisition, navigation information preprocessing, navigation resolving and the like; the I / F conversion module can directly convert a current signal of the accelerometer into a pulse signal, and the pulse signal is accessed to the navigation resolving module for navigation resolving; the power supply module can output + 5V (8W),-5V (3W), + 15V (9W) and-15V (3W) isolated voltage-stabilized power supplies to the outside, and can supply power to other loads of the inertial navigation equipment. The method is suitable for laser inertial navigation equipment with small volume, low power consumption and high reliability.