51results about How to "Improve computing power" patented technology

The invention discloses a multi-bus decoupling distributed embedded hardware rendering architecture, system and method, and relates to the technical field of ultra-high-definition video hardware processing, and the key points of the technical scheme are that the architecture comprises a multi-bus decoupling module which comprises a plurality of hardware buses which are physically isolated from one another, each hardware bus is an exclusive hardware transmission link bearing a single-type manufacturing task; the modular processing unit is an independent hardware board card and is integrated with an external signal input port, an upstream bus signal input port and a downstream bus signal output port; the plurality of modular processing units are cascaded in sequence through a hardware bus in the multi-bus decoupling module to form a distributed assembly line rendering link; when the modular processing units are newly added, the signal processing capability and the rendering synthesis capability are linearly improved along with the increase of the number of the modular processing units. According to the invention, the problem of performance bottleneck of the traditional architecture in processing 4K / 8K ultra-high-definition and multichannel rendering is fundamentally solved.

The application discloses a kind of highway maintenance digital twinborn application system construction method and system, it is related to digital twinborn technical field, the steps of this method include: real-time acquisition of the multi-source perception data of highway section, and introduce constraint engine, to highway three-dimensional entity construction, generate several three-dimensional sub-image model;Among them, multi-source perception data includes highway image, highway laser point cloud and component attribute;Based on three-dimensional sub-image model, abstractly constructed to form topological space, adopt interpolation algorithm to generate datum curve, and combine the grid vertex of three-dimensional sub-image model, identify envelope boundary, to execute cross section scanning and generate target rendering road;Based on target rendering road, identify disease area, and based on disease area introduce preset maintenance rule, through semantic mounting mapping back to topological space, form digital twinborn application system;The application improves the efficiency of highway maintenance management, improves the computing power and rendering performance of three-dimensional rendering.

The application provides a kind of deep learning optical imaging system design method based on complex function neural network, comprising the following steps: step one, object distance, system focal length, F number as input, according to the ideal optical system imaging relationship, determine image distance, imaging scale ratio;Step two, according to the imaging scale ratio and the object image of ideal optical system, the image of ideal optical system is calculated;Step three, construct complex function generator network model, step four, construct discriminator network model, step five, after the establishment, training of the above-mentioned complex function neural network deep learning model, step six, use phase.The deep learning optical imaging system design method based on complex function neural network provided by the application solves the correlation between the advantages and disadvantages of the design result and the experience value of the designer, without the designer providing initial structure parameters;Greatly improve the computing ability and optimization speed.

According to the top heat dissipation type liquid cooling container and the application control method thereof, the cooling tower container top arrangement design is adopted, a CDU module is omitted, the overall cost is reduced, more Tanks can be deployed in the spare space after the CDU module is omitted, and the computing power of a single liquid cooling container is greatly improved. The cooling tower is compact in structural form, low in space occupancy rate, higher in integration degree and good in universality and reliability, and the ground space of the cooling tower is saved. After a certain cooling tower fails, normal operation of other devices is not affected, and the disaster recovery capacity is improved. The cooling tower and the Tank carry out heat exchange one by one, the heat dissipation efficiency is higher, the number of water cooling pipelines is smaller, and the integration degree is higher.

This invention discloses a liquid-cooled heat dissipation chip structure and its packaging method, relating to the field of chip technology. The liquid-cooled heat dissipation chip structure includes: a chip with accommodating channels formed therein, and coolant filled into the accommodating channels; a substrate, on which the chip is packaged; and a cooling fan mounted on the side of the chip away from the substrate. This invention solves the problem of chip overheating leading to decreased chip computing performance and slowed data processing speed.

The application provides an activation module for data calculation, an AI processor and a data calculation method. When it is determined that a result calculated by a preceding matrix acceleration module meets an output condition, the output calculation data is stored in a cache unit. A read-write control unit reads the output calculation data from the cache unit and distributes the output calculation data to each calculation unit. Each calculation unit performs a softmax calculation and outputs a target calculation result. In this way, the output calculation data output by the preceding matrix acceleration module can be stored in the cache unit of the activation module. After processing by the read-write control unit and data distribution, the softmax calculation is performed in parallel by at least one calculation unit. The calculation and access of all data are performed in the activation module, reducing the overhead of accessing memory and improving overall calculation performance. The parallel calculation processing scheme can also improve calculation efficiency.

The application provides a synthetic aperture radar active composite jamming method and system, the method comprising: acquiring intermediate frequency radar signals to be jammed, radar related parameters and control parameters; calling DSP and multiple FPGA calculation boards to calculate modulation coefficients corresponding to each false scattering point according to pre-downloaded deception templates and radar related parameters; generating deception jamming signals corresponding to the intermediate frequency radar signals according to the intermediate frequency radar signals and the modulation coefficients corresponding to each false scattering point; generating suppression jamming signals corresponding to the intermediate frequency radar signals according to the control parameters; and determining composite jamming signals corresponding to the intermediate frequency radar signals according to the deception jamming signals and the suppression jamming signals corresponding to the intermediate frequency radar signals. The application can obtain composite jamming signals, has better jamming effect, is not easy to expose the position of the jammer, and has lower cost of the jammer. The signal processing architecture of DSP and FPGA is adopted, the calculation performance of the system is improved, and the real-time performance of system simulation is ensured.

The invention provides a configuration server. The configuration server comprises a case and a mainboard, a first installation area and a second installation area are arranged at the two ends of the case in the length direction respectively, and a first GPU set and a second GPU set which are electrically connected to the mainboard are arranged in the first installation area and the second installation area respectively. The first GPU group comprises at least eight first GPU cards, and the first GPU cards are horizontally installed in the first installation area; the second GPU group comprises at least eight second GPU cards, the total number of the first GPU cards and the second GPU cards is at least sixteen, and the second GPU cards are vertically installed in the second installation area. The installation areas are arranged at the two ends of the case respectively, the installation mode of horizontal and vertical combination is adopted, integration of sixteen GPU cards is achieved, the number bottleneck of existing GPU cards is broken through, the computing power is greatly improved, scenes such as large-scale model training can be efficiently supported, the processing period can be shortened, and application in the artificial intelligence high-end field can be assisted.

This invention discloses a computation graph optimization method, system, and storage medium based on a multi-level cost model, comprising: (1) defining a multi-level cost model to evaluate the execution cost of computation graph execution schemes; (2) setting a set of subgraph replacement rules; (3) converting a given neural network model file into unified computation graph information; (4) analyzing the candidate computation graph structure and applying the subgraph replacement rules to obtain a new computation graph; (5) selecting a cost model to evaluate the execution performance of the computation graph; (6) selecting candidate computation graphs based on the cost evaluation results and scaling factors; and (7) repeating steps (4) to (6) until the expected computation graph optimization effect or convergence condition is achieved to obtain the optimal computation graph. This invention comprehensively considers the trade-off between search time and optimization effect, can meet different needs in various scenarios, guide the optimization direction of computation graphs, and thus improve the computational efficiency and performance of neural network models.

This invention relates to the field of high-performance computing and provides a method and apparatus for optimizing the performance of a graphics processing unit (GPU) aggregate communication operator. The method includes: allocating device-side storage space on the host side; copying the structured data to be communicated to the device-side storage space to obtain a target data pointer; adjusting the kernel function parameter of the aggregate communication operator from a structure type to a pointer type and passing the target data pointer; executing the kernel function on the GPU side, directly accessing the device-side storage space based on the target data pointer to complete the aggregate communication operation; and releasing the device-side storage space after the aggregate communication operation is completed. This invention solves the problem of excessive GPU register pressure and decreased cache hit rate caused by inefficient memory access instructions generated by the compiler to pass structure parameters in existing technologies. It avoids the generation of inefficient instructions, reduces register pressure, and improves execution efficiency.

The invention discloses a remote sensing big data automatic processing method based on cloud computing, and relates to the field of remote sensing big data processing, and the remote sensing big data automatic processing method comprises the steps: (S1) collecting remote sensing data; (S2) uploading remote sensing data to a cloud computing platform; (S3) processing and analyzing the remote sensing data by adopting a cloud computing processing model; (S4) storing the remote sensing data compression package to a cloud computing platform, and debugging a data processing algorithm by adopting a container cloud integrated model; (S5) displaying and analyzing a processing result by adopting a data visualization platform; according to the invention, remote sensing big data automatic processing is realized based on cloud computing, and a low-orbit remote sensing constellation-oriented transmission routing task planning algorithm and a container cloud integrated model are fused at the same time, so that the efficiency and security of remote sensing big data automatic data processing and data transmission are improved.

This invention discloses an autonomous evolutionary AGI system and method based on dual-model decoupling and human feedback, belonging to the field of artificial intelligence technology. The system includes modules for online inference (Model A), offline training (Model B), human feedback rewards, persistent storage, training scheduling, model hot replacement, distributed communication, and a secure sandbox. This invention decouples inference and training to ensure service continuity; anchors value direction with human ratings to avoid drift; employs dual-condition triggering training to improve resource efficiency; achieves seamless updates through hot replacement; avoids memory leaks through database persistence; enables multi-machine expansion through distributed architecture; and ensures execution security through a sandbox. This invention enables 24 / 7 online, controllable, and secure autonomous evolution of AGI, suitable for code generation, intelligent agents, automated R&D, and general artificial intelligence scenarios.

The invention discloses a data processing method and device, an intelligent calculation platform, a storage medium and a product. The method comprises the steps that in response to a request of an operator calculation task, a second API of an operator under a unified programming normal form or a third API of an operator under a native programming normal form supported by processing equipment is called based on a first API; and generating a calculation result corresponding to the operator calculation task based on the second API or the third API. Therefore, operator calling under the hybrid programming normal form can be realized based on the unified first API, so that the operation performance of operators can be effectively improved based on operator calling under the hybrid programming normal form on the basis of considering the universality of AI chips of different types of native programming normal forms, and the user experience is further improved.

The application belongs to the field of big data learning models and provides a rotating machinery characteristic frequency extraction method under strong interference, which is based on the optimal balance parameter alpha in VMD decomposition roughly positioned according to the set reference modal correlation 最优 The balance parameter alpha of each decomposition is locally optimized by combining the sparrow search optimization algorithm. The modulus K of decomposition is adaptively determined by the iteration decomposition times, and the improved recursive VMD method avoids the influence of the inaccurate preset decomposition number and the balance parameter on the decomposition effect. The application is applied to the constructed simulation signal to achieve the optimal decomposition effect that can be achieved by the VMD method, and is applied to the pump cavitation flow-induced vibration signal processing to successfully achieve the effective extraction of the fluid machinery flow-induced vibration characteristic frequency under the condition of low signal-to-noise ratio.

The invention discloses a system and a method for accelerating a gene alignment execution process. The system comprises a processing thread management module, one or more dynamic caches and a dynamic cache management module. Wherein the processing thread management module is configured to set a gene comparison process as a multi-stage assembly line, each execution step of the gene comparison process corresponds to one assembly line stage on the multi-stage assembly line, and a plurality of processing threads are distributed for each assembly line stage; and dividing gene sequence data to be compared into a plurality of data blocks and providing the data blocks to the multi-stage assembly line for processing. The dynamic caches are used for data transmission between two pipeline stages, and each dynamic cache comprises at least two cache blocks. And the dynamic cache management module is configured to manage distribution and recovery of the dynamic caches between the two pipeline stages and control switching of working states between different cache blocks in each dynamic cache. According to the method, the overlapping degree of process calculation and input and output is higher, the memory efficiency is higher, and the performance of overall execution is improved.

This application relates to a cache management method, apparatus, computer device, medium, chip, and product. The method includes: acquiring a target task and a management command queue; the management command queue containing various management commands for the target task; when the last-level cache module does not contain dependency data required by a target subtask within the target task, in response to a first management command, reading the dependency data required by the target subtask from memory and storing the dependency data in the last-level cache module; in response to a second management command, initiating the execution of the target subtask; the target subtask includes an accelerator reading dependency data from the last-level cache module. This method can improve the processing efficiency of the target task.

This invention provides a method and system for achieving GPU module in-memory computing through hybrid storage. The GPU module includes a GPU chip, which contains a DDR controller, a PCM controller, and SRAM. A CXL controller is located at the front end of the GPU chip. The data bus inside the GPU chip connects to the CXL controller, DDR controller, PCM controller, and SRAM. The CXL controller reports memory addresses to the CPU for access via the CXL protocol. The space of the reported memory addresses is mapped to the PCM address range managed by the GPU chip, and the space of the reported memory addresses is smaller than the PCM address space managed by the GPU chip. The CPU directly accesses the reported memory addresses and copies data from the system DDR to the reported memory addresses. This improves the efficiency of GPU data access, reduces GPU data access latency, and enhances the overall computing performance of the system.

The application discloses a kind of computing resource scheduling method and system based on computing power network cluster, and the application relates to the technical field of computing power network cluster, according to the amount of calculation of multiple computing tasks, the node load state of multiple computing power nodes and resource scheduling system Determine the computing task matched by multiple computing power nodes, Ensure the matching accuracy of multiple computing power nodes to computing task.Therefore, according to the computing progress of multiple computing power nodes to computing task and the computing mode of multiple computing power nodes Determine the computing progress distribution diagram of computing power network cluster;According to the computing progress distribution diagram of computing power network cluster, the computing resource matched by each computing power node and the task state of multiple computing tasks Determine the optimization system of computing resource, and dynamically optimize the computing power of computing power node in computing process, based on the optimization system of computing resource Realize the further optimization of computing resource, improve the computing power of computing power node in computing process.

The application relates to a localized multi-network-port high-computing-power data acquisition device, which comprises a core module and an interface expansion module, wherein the core module and the interface expansion module are connected; the core module is based on a Ruikai micro rk3588 platform; the interface expansion module comprises five independent gigabit network ports, two USB-A interfaces, one M.2 high-speed storage interface, one Type-c high-speed interface, one HDMI output interface, one Mini-Pcie expansion interface and a plurality of expansion IO interfaces; the structure provided in the application has the advantages that the computing power is improved: the heterogeneous architecture of RK3588 NPU+extension acceleration card, the AI task processing efficiency is improved by more than 5 times compared with a traditional industrial computer; the multi-network-port redundancy: 4-network-port design supports protocol isolation and link backup, and the network availability reaches 99.99%; localization adaptation: the core chip, the peripheral chip and resistance, capacitance and inductance are all domestic, and the component localization rate is 100%; flexible expansion: 5G, LoRa and other communication modules can be expanded through the mini-PCIe and USB interfaces, and the device is suitable for diversified scenes.

The application relates to the technical field of electric power transaction data processing, and discloses a power spot transaction data time sequence mining method capable of representing market fluctuation characteristics, which comprises the following steps: performing variational mode decomposition on electric price data, locking a probability density trough by using kernel density estimation to determine a dynamic shunt threshold, routing components to a trend or fluctuation channel according to the dynamic shunt threshold, respectively generating prediction values by using a linear extrapolation model and a multi-head attention mechanism with a causal mask introduced and superimposing the prediction values, the application realizes adaptive boundary locking in a non-stationary environment by using data topological morphology, and blocks invalid feature interference by mutual information causal gating, solves the contradiction between mean regression and peak capture of a traditional model, and improves the effectiveness of a prediction result.

The invention provides a neutron transport scanning operator optimization method based on built-in function and instruction level parallelism, and the method comprises the steps: firstly reconstructing a data layout, declaring an array according to an energy group sequence, carrying out the memory alignment, and enabling a calculation process to adapt to an SIMD vectorization architecture; then implementing explicit vectorization calculation by adopting a built-in function, performing polar angle cycle expansion and instruction recombination, and fully mining instruction-level parallel potential; meanwhile, key index calculation is optimized into vectoring polynomial approximation. Based on the optimized data flow and the parallel computing mode, efficient updating of the angular flux and the standard flux is achieved, and convergence judgment and calculation are completed. According to the method, the calculation throughput rate and the hardware resource utilization rate of the scanning operator are remarkably improved, and the method can be coordinated with coarse-grained parallel strategies such as MPI / OpenMP and is suitable for a multi-architecture high-performance calculation environment.

The invention discloses a matrix multiplication optimization method and system oriented to an RISC-V architecture, and the method comprises the steps: detecting the hardware characteristics of a target RISC-V platform, and adaptively configuring optimization parameters according to a detection result; performing memory layout and data rearrangement on the input matrix B to realize memory optimization; a multi-level partitioning strategy is adopted to adapt to a memory hierarchical structure, and multi-level partitioning calculation is achieved; carrying out RVV vectorization core calculation by using RISC-V vector instruction extension to realize data-level parallel optimization; the instruction delay is hidden through loop expansion and a software assembly line, and a data prefetching mechanism is adopted to realize instruction-level parallel optimization; performing multi-core parallel computing by using an OpenMP multi-thread technology to realize thread-level parallel optimization; and calculating residual elements by using a vector register to realize tail processing optimization. According to the method, the cache hit rate and the calculation performance degree are improved, the hardware potential is fully excavated, and the method is suitable for edge devices with high requirements.

The application discloses a data operation device and method, a processing core and an electronic device. The device comprises a data reading module, which is used for receiving an instruction and reading a first matrix and a second matrix based on the instruction. The instruction comprises grouping parameters of a calculation unit array. The grouping parameters are parameters used for dividing the calculation unit array into sub-calculation arrays. The grouping parameters are related to rows of the first matrix or columns of the second matrix. The sub-calculation arrays read data of the first matrix and the second matrix and perform operations of the first matrix and the second matrix. According to the grouping parameters in the instruction, the data operation device divides the calculation unit array into multiple sub-calculation arrays, which can realize flexible combination of calculation units of the calculation unit array, and can effectively utilize the calculation units to improve the computing power of the data operation device.

This application discloses a multiply-accumulate operation method, apparatus, neural network processing apparatus, and electronic device. The multiply-accumulate operation method encodes input activation data into encoded activation data and original weight data into encoded weight units, enabling the multiplication result to be obtained in the memory array simply by selecting a shift operation, replacing complex multiplier circuits and significantly reducing computational power consumption. By shifting and accumulating the first intermediate result to obtain the second intermediate result, and using computation-based compensation codes for precise compensation, the correctness of the result is ensured while avoiding the additional cycle overhead and complex circuitry caused by processing unsigned data or sign extension in traditional schemes. This improves computational throughput while effectively enhancing computing power and optimizing power consumption, ultimately comprehensively improving the energy efficiency ratio and overall processing efficiency of the multiply-accumulate operation.

This application provides a resource scheduling method, apparatus, electronic device, medium, and program product, relating to the application of large-scale models in fintech scenarios, and applicable to the fields of big data technology and artificial intelligence technology. The method includes: acquiring multi-source heterogeneous data, wherein the multi-source heterogeneous data includes at least customer-side, environment-side, and system-side data; constructing a multimodal feature representation based on the multi-source heterogeneous data; inputting the multimodal feature representation into a customer behavior prediction model to perform multi-task prediction, obtaining prediction state information; obtaining resource allocation strategy information based on the prediction state information and resource scheduling objectives; and performing resource scheduling based on the resource allocation strategy information.

The application discloses an image transformation method, system, chip and storage medium. The application improves the calculation performance by performing coordinate transformation on output pixel points in an output image in advance. Specifically, the corresponding target input pixel points are obtained by performing coordinate transformation on the output pixel points in advance, and the target input pixel points obtained by transformation are used to manage the local cache so that the corresponding target image data is stored in the local cache. Therefore, when subsequent target image processing is required for the output pixel points, the target image data corresponding to the output pixel points has been stored in the local cache, so it is not necessary to wait for the local cache to read and store the corresponding target image data from a storage entity, time delay is reduced, processing efficiency is improved, and the design index of high performance can be met.

A kind of automobile parts defect detection method and system based on multi-scale feature fusion, detection method includes the following steps: constructing data set;Select a raw image from data set and input into pre-trained backbone network, obtain multi-scale feature;Multi-scale feature is input into multi-scale feature fusion module for feature fusion, and the feature map after fusion is obtained;Then the feature map after fusion is input into decoding module for image reconstruction and integration, and the integrated reconstruction image is obtained;Solve the Euclidean distance between original image and integrated reconstruction image, and dynamically adjust the weight of automobile parts defect detection network, obtain the trained automobile parts defect detection network;The trained automobile parts defect detection network is deployed to equipment end, and actual automobile parts defect detection is carried out.The present application improves the problem that the existing defect detection method recognizes new defect rate low, in addition, the present application also has the advantages of high efficiency, flexibility.

The invention relates to an optical nonlinear operation device, an optical nonlinear operation assembly and a preparation method of a fluorescent material. The optical nonlinear arithmetic device comprises a fluorescent material layer and a reflecting layer, wherein the fluorescent material layer covers one side of a reflecting surface of the reflecting layer; the fluorescent material layer comprises a fluorescent material, the fluorescent material layer is used for absorbing part of incident laser emitted by the incident light source, and the service life of the fluorescent material is 1 nanosecond to 50 microseconds; the reflecting layer comprises a plane reflecting mirror and is used for reflecting the rest of incident laser emitted by the incident light source except for part of the incident laser. By adopting the device provided by the invention, the calculation effect of optical calculation can be improved.

The application belongs to the field of multipliers, and discloses a multi-precision parallel multiplication array structure and method, which constructs a two-dimensional array composed of multiple same basic multiplication units, each unit serving as a minimum reuse unit to perform preset bit-width multiplication, and different bit-width multipliers are flexibly constructed through row-level and column-level combination; meanwhile, a multiplier decomposition and mapping module is provided to decompose and map the operands to corresponding units according to bit width, and a compression and summation module is provided to perform layered parallel compression and summation on the unit outputs to obtain the final result. The structure significantly improves the resource utilization, avoids the redundancy problem of traditional design, enhances the reconfigurability, can adapt to various precision combination operations, improves the structure scalability, can be expanded in bit width without redesign, optimizes the mode switching efficiency, simplifies the control logic, and thus effectively balances the high resource utilization, flexible reconfigurability and high performance.