2255 results about "Electronic systems" patented technology

The invention discloses a 3D packaged low parasitic inductance SiC power module, which comprises a substrate layer, a chip layer, a connecting layer, a middle layer and a decoupling capacitor, the chip layer is electrically connected with the substrate layer; the middle layer is located between the upper chip layer and the lower chip layer, and the upper connecting layer and the lower connecting layer are windowing type copper blocks, are externally connected with DC terminals and are used for connecting the upper substrate layer and the decoupling capacitor; and the decoupling capacitors are two groups of capacitors arranged beside the middle layer and are electrically connected with the upper connecting layer and the lower connecting layer. By adopting the copper material with high conductivity to be connected with the copper layers in the laminated layer and the substrate to form the middle layer, the inductance of the machine body is obviously reduced, the heat dissipation effect is improved, the machine body has obvious advantages in high-frequency, high-voltage and high-power applications, and the overall performance and reliability of a power electronic system can be effectively improved.

The invention discloses a fault-considered spacecraft integrated chip interface circuit potential path analysis method, a storage medium and equipment, and belongs to the technical field of integrated circuit design and fault analysis. The method aims at solving the problem that an analysis method for a path under a failure mechanism under different environmental stresses is lacked. The method comprises the following steps: constructing an interface circuit simulation model of an integrated device based on a common interface circuit and a potential path structure in a spacecraft electronic system, then supplementing degradation mechanisms in various task stress environments, and determining a fault mode table of the interface circuit of the integrated device; a circuit simulation method is adopted to carry out potential path analysis considering fault factors on an interface circuit under a typical task profile, a fault path response feature library of the interface circuit under the task profile is obtained, then a constraint clue table for interface circuit design is formed, an interface circuit failure associated fault tree model is constructed, and the interface circuit failure associated fault tree model is constructed. And calibrating a relation path between various potential paths and device degradation or local failure for failure positioning and path checking.

The invention relates to the technical field of electronic systems of spacecrafts, and discloses a fault-tolerant method for non-redundant fault reconstruction of a spaceborne computer, which comprises the following steps of: 1, accessing a hardware state manager by a BIOS (Basic Input / Output System) after the system is started; obtaining health state data recording the health state of the local storage device, a current starting target ID used for indicating a current starting target, and a retry count value associated with the current starting target ID; a BIOS (Basic Input Output System) accesses a hardware state manager to obtain health state data and a retry count value of local storage equipment, so that normal equipment is autonomously selected for starting, and the fault-tolerant effect of dynamically avoiding a fault starting path is achieved; compared with the technical scheme in the prior art that the computer starting process highly depends on a solidified single physical storage device, the single-point fault risk of permanent paralysis of the computing system caused by damage of the single storage device is solved.

The invention discloses an aging performance evaluation method and platform for a super junction MOS device, and relates to the technical field of performance evaluation, and the method comprises the steps: carrying out the test scene matching, and obtaining a target acceleration test scene group; calling a plurality of aging trend curves according to the target acceleration test scene group; locally calling a historical operation data set of the to-be-tested super junction MOS device; performing degradation feature extraction on the historical operation data set to obtain multiple groups of historical operation time sequence fragments; performing degradation increment correlation prediction on multiple groups of historical operation time sequence fragments, and outputting a device aging time sequence trend curve; comparing the aging time sequence trend curve of the device based on a preset failure threshold value, and outputting the remaining service life of the device; and interactively obtaining an equipment life design index of the target power electronic system, and quantitatively outputting an aging performance evaluation result in combination with the residual service life of the device. The technical problem that the aging performance evaluation accuracy is insufficient in the prior art is solved, and the technical effect of improving the aging performance evaluation precision is achieved.

The present invention discloses an intelligent onboard protection system for a plasma detector, comprising: an integrated protective cover and a nitrogen blowing port, a pressing device, a deployment device, a power supply subsystem and a control subsystem; the protective cover covers the sensor head and has an appearance consistent with the shape of the sensor head; the nitrogen blowing port blows nitrogen into the interior of the sensor during a ground test phase to prevent contamination; the system is sealed with a blocking cap before satellite launch to prevent dust contamination; the pressing device presses the protective cover against the sensor head when the system is in a protection state, and releases the protective cover by thermal cutting according to the instruction of the control subsystem; the deployment device cooperates with the pressing device to realize the deployment of the protective cover, and locks the protective cover after it is released to a specified position; the power supply subsystem supplies power to the pressing device according to the instruction of the control subsystem; the control subsystem periodically collects status monitoring parameters and transmits them to a payload management unit, controls the power on and off of the pressing device according to the ground remote control instruction, and executes the deployment operation of the system.

The invention relates to an electric vehicle wireless charging system LPV-Hammerstein model identification method based on an alternating least square iteration strategy, and belongs to the technical field of power electronic system modeling and parameter identification. The method comprises the following steps: firstly, constructing an LPV-Hammerstein model structure based on a WPT system circuit topology and a working mechanism, and then collecting discrete data of a system input control signal U, an output DC voltage Vo and a scheduling variable Req; then, alternately fixing other parameters by adopting an alternate least square iterative algorithm, and converting a to-be-estimated parameter problem into a linear least square sub-problem to be solved; and when a convergence condition is satisfied, a final LPV-Hammerstein model parameter estimation result is obtained. According to the method, the common nonlinear and parameter change coupling characteristics in the wireless charging system of the electric vehicle can be effectively processed, a systematized and efficient way is provided for obtaining a high-precision system dynamic model, and the limitation that the system cannot be accurately described by a traditional linear model or a simple nonlinear model is overcome.

The invention provides an electromagnetic shielding device of a complex electronic system, which belongs to the technical field of electromagnetic shielding of radio telescopes and comprises a filter shielding cabinet, a waveguide tube and a connecting mechanism. The filter shielding cabinet is arranged at the top of the shielding cabin and located outside the shielding cabin; a servo system shielding cabinet is arranged in the shielding cabin; the filter shielding cabinet is provided with a wire outlet pipe, the shielding cabin is provided with a mounting port, and the wire outlet pipe penetrates through the mounting port to enter the shielding cabin. And one end of the waveguide tube is connected with the filtering shielding mechanism, and the other end of the waveguide tube is connected with the servo system shielding cabinet. And the connecting mechanism is arranged at the wire outlet pipe and is used for connecting the wire outlet pipe and the waveguide tube or connecting the waveguide tube and the servo system shielding cabinet. The filter shielding cabinet is arranged outside the shielding cabin, the internal space of the shielding cabin is not occupied, and the problems that the space in the shielding cabin is narrow, and the filter shielding cabinet is difficult to install are solved.

Example implementations include a method, apparatus and computer-readable medium for automated analog electronic system design and analysis, comprising receiving a user query via a user interface. The implementations further include identifying, by a conversation agent of a machine learning model (MLM), at least one attribute of the user query. Additionally, the implementations further include selecting from a plurality of agents, by the conversation agent of the MLM, two or more agents that can collectively generate a response to the user query when executed in a specific sequence based on the at least one attribute of the user query. Additionally, the implementations further include prompting, by the conversation agent of the MLM, the two or more agents in the specific sequence to collectively generate the response. Additionally, the implementations further include outputting, by the conversation agent of the MLM, the response via the user interface.

A semiconductor device may include a plurality of gate electrodes apart from each other in a vertical direction on a substrate; a plurality of channel structures penetrating the plurality of gate electrodes and extending in the vertical direction; and a plurality of bit lines arranged on and connected to the plurality of channel structures. The plurality of bit lines may include a plurality of lower bit lines and a plurality of upper bit lines at different vertical levels from each other to constitute at least two layers. The plurality of upper bit lines may be apart from each other in a first horizontal direction and extend in parallel with each other in a second horizontal direction perpendicular to the first horizontal direction. A lower expansion space may be defined between two lower bit lines adjacent to each other among the plurality of lower bit lines.

The invention discloses a piezoresistive pressure sensor chip and a preparation method thereof, and belongs to the technical field of micro-electromechanical systems. The piezoresistive pressure sensor chip comprises a substrate, the back of the substrate is etched with a cavity, the center of the cavity is provided with a cross-shaped mass block, and four hollow islands and four peninsula are arranged along the linear direction of the cross-shaped mass block; a plurality of groups of piezoresistor strips are arranged on the front surface of the substrate, each group of piezoresistor strips comprises a first piezoresistor strip component arranged close to the center and a second piezoresistor strip component arranged close to the side wall of the cavity, and the first piezoresistor strip component forms an internal Wheatstone bridge through a first metal lead group; the second piezoresistor strip component forms an external Wheatstone bridge through a second metal lead group; the glass is arranged on the substrate back. The piezoresistive pressure sensor chip can measure the pressure of a micro-pressure section, can bear high overload equivalent to a plurality of times of the full scale, and has the advantages of high sensitivity, good linearity, high precision, good dynamic performance and the like.

The invention relates to the technical field of flexible electronic integrated systems, in particular to a multilayer flexible circuit, a preparation method thereof and a flexible electronic system. The multi-layer flexible circuit comprises a flexible substrate layer and a flexible conductive layer which are arranged in a stacked mode, and the flexible conductive layer comprises metal nanowire aerogel and a filled flexible base material. The flexible base material and the flexible substrate layer in the flexible conductive layer have tensile properties. The metal nanowire aerogel is in lap joint in the flexible conductive layer to form a rich conductive network, so that the flexible conductive layer has good conductivity. The special form of the metal nanowire aerogel enables the flexible conductive layer to have good electrical stability, namely resistance-strain insensitivity and resistance stability after long-term deformation, and when the flexible conductive layer deforms, the resistance does not change obviously. Due to the stacked structure design, the mechanical stretchable upper limit of the multi-layer flexible circuit is remarkably improved, the resistance change rate under the same deformation is remarkably reduced, and the resistance change is low after long-term use.

The invention discloses a multi-level pulse compensation type active EMI (Electro-Magnetic Interference) filter suitable for a multi-noise source switching power supply and a control method of the multi-level pulse compensation type active EMI filter. The invention provides a multi-level pulse compensation scheme based on switch behavior modeling, aiming at the problem of common-mode noise of adjacent rising edges and falling edges generated by a high-frequency switch in a multi-noise-source switching power supply. The time sequence delay and the edge slope of the compensation signal are calculated by analyzing the dv / dt characteristics in the switching-on and switching-off processes of the switching device, and accurate matching and offset with a noise source in phase and amplitude are achieved. Compensation control logic is realized by sharing a main control chip with a power circuit, and an additional controller and a high-precision sampling system are not needed; the self-adaptive tracking of the compensation amplitude is realized through the voltage following circuit; a multi-level compensation signal is output through the totem-pole circuit and injected into a common-mode path, and effective suppression of electromagnetic interference is achieved. The converter has the advantages of small size, low cost, simplicity and convenience in installation, high stability and the like, and is suitable for various multi-noise-source power electronic systems including a dual-active bridge converter, a phase-shifted full-bridge converter and an interleaving Buck converter.

The invention provides a computer cross-scale integrated analysis method based on a multi-physics field coupling mechanism, and the method comprises the steps: constructing a multi-level finite element model from a system level to a micro-area level, and integrating thermal-mechanical-electric coupling modeling; therefore, the technical problems that in a traditional method, multi-physics field coupling lacks, local area modeling is not fine, and electrical performance evolution is not introduced are solved, high-precision simulation of a typical device failure mechanism is achieved, and the method is suitable for device packaging reliability evaluation in special electronic systems such as military and high-reliability civil use and the like. The method can be widely popularized in microelectronic structures such as a power supply module, a processor and a memory, and can improve the evaluation precision of the high-frequency signal transmission performance of complex electronic equipment, thereby improving the precision of predicting the service life.

A method and system of diagnosing a vehicle with a vehicle diagnostic system to provide repair recommendations includes connecting a vehicle diagnostic computer tool to a diagnostic port of a vehicle to be in communication with an electronic system of the vehicle and reading vehicle data information of the vehicle with the vehicle diagnostic computer, such as diagnostic trouble codes (DTCs). A diagnostic evaluation program is operable to detect whether particular electrical vehicle systems are present on the vehicle, such as safety systems including Advanced Driver Assistance Systems. The system may additionally receive information regarding damage to the vehicle, such as from a collision. The system includes a repair information database and a report generator program that is operable to generate a repair recommendation report, including for example based on the vehicle data information, the particular electrical vehicle systems determined to be present, and the damage to the vehicle.

The invention discloses a core particle system architecture, which comprises a system management core particle, a functional core particle, an interconnection core particle and an IO core particle, the system management core particle is used for monitoring the working state of each functional core particle; the system management core particle is used for receiving externally input tasks and distributing the tasks to the functional core particles according to the working states of the functional core particles; the functional core particles are used for executing tasks distributed by the system management core particles; the interconnection core particles are used for realizing communication between the system management core particles and the functional core particles and among the functional core particles; and the IO core particle is used for realizing communication between the system management core particle and the outside. The core particle system architecture provided by the invention is comprehensive in function, high in flexibility, strong in reliability, good in compatibility and capable of effectively fusing wide core particle resources, and has a wide application prospect in a high-performance electronic system.

A method of forming a device comprises forming sacrificial pillar structures over conductive structures overlying a barrier structure substantially impermeable to hydrogen. The sacrificial pillar structures are separated from one another by trenches linearly extending in a first lateral direction orthogonal to a second lateral direction in which the conductive structures linearly extend. Gate electrodes are formed within the trenches and laterally adjacent sidewalls of the sacrificial pillar structures. The sacrificial pillar structures are removed to form openings between the gate electrodes. Dielectric liner structures are formed within the openings and laterally adjacent sidewalls of the gate electrodes. Channel structures are formed within the openings after forming the dielectric liner structures. The channel structures comprise a semiconductive material having a band gap larger than that of polycrystalline silicon. Conductive contacts are formed on the channel structures. A device, a memory device, and an electronic system are also described.

The invention belongs to the technical field of fault-tolerant control of an electronic system, and particularly relates to a dual-microcontroller system and a control method thereof, and the dual-microcontroller system comprises a hardware architecture and a software architecture; the hardware architecture specifically comprises a main MCU module, a standby MCU module, a dual-power module, a dual-measurement acquisition module, a hardware arbiter and an output switching value module; the software architecture comprises the steps of initializing a data synchronization communication interface of the main MCU module and the standby MCU module, starting the main MCU module and the standby MCU module, reading data of the measurement acquisition module in a working program state machine by the main MCU module, interacting with external equipment through the communication interface and driving switching value output; and when the main MCU module has no fault, the hardware arbiter selects the switching value output of the main MCU module to drive the external equipment, and when the main MCU module has a fault, the hardware arbiter selects the switching value output of the standby MCU to drive the external equipment.

A semiconductor device may include a plurality of gate electrodes apart from each other in a vertical direction on a substrate; a plurality of channel structures penetrating the plurality of gate electrodes and extending in the vertical direction; and a plurality of bit lines arranged on and connected to the plurality of channel structures. The plurality of bit lines may include a plurality of lower bit lines and a plurality of upper bit lines at different vertical levels from each other to constitute at least two layers. The plurality of upper bit lines may be apart from each other in a first horizontal direction and extend in parallel with each other in a second horizontal direction perpendicular to the first horizontal direction. A lower expansion space may be defined between two lower bit lines adjacent to each other among the plurality of lower bit lines.

A microelectronic device comprises a stack structure, pillar structures, a conductive plug structure, a sense transistor, and selector transistors. The stack structure comprises a vertically alternating sequence of conductive material and insulative material, and is divided into blocks separated by dielectric slot structures. The blocks individually include sub-blocks horizontally extending in parallel with one another. The pillar structures vertically extend through one of the blocks of the stack structure. Each pillar structure of a group of the pillar structures is positioned within a different one of the sub-blocks of the one of the blocks than each other pillar structure of the group. The conductive plug structure is coupled to multiple of the pillar structures of the group of the pillar structures. The sense transistor is gated by the conductive plug structure. The selector transistors couple the sense transistor to a read source line structure and a digit line structure.

The invention relates to power semiconductor device on-line monitoring and power electronic system control, in particular to a SiC MOSFET conduction current extraction circuit and method, high-frequency oscillation interference is effectively suppressed through a second-order passive RC filter circuit, a measurement error less than or equal to 1.5% is realized within a current range of 50A-300A in combination with an accurate mathematical model established by a depth symbol optimization algorithm, and the measurement accuracy is improved. The requirement of the intelligent gate driver on high-precision current feedback is met, and the measurement precision is remarkably improved; the pulse width direct analysis technology is adopted, a traditional active integrator and a digital decoding link are omitted, the system response delay is smaller than or equal to 500 ns, microsecond-level over-current protection can be supported, the response speed and the real-time performance are optimized, and the system safety in a high-frequency application scene is remarkably improved.

The invention provides an agent interaction processing method and system based on end-cloud cooperation and an electronic system, and relates to the technical field of artificial intelligence. The method comprises the following steps: in response to a user interaction request from a client, driving a target agent to perform reasoning and determining a target tool from a unified tool pool aggregated with a cloud tool and a client tool according to a reasoning result; if the target tool is a cloud tool, executing the target tool at the server side and generating an execution result, and if the target tool is a client tool, generating a calling mark object used for indicating a client to call a corresponding native function; converting the execution result or the calling mark object into a first standard instruction frame, and sending the first standard instruction frame to the client, so that the client executes a corresponding local operation; and receiving result data returned by the client, and recovering the context state of the target agent according to the result data so as to drive subsequent reasoning. According to the scheme, the problem that the end-side capability is difficult to directly call by a cloud large model can be solved.

The invention relates to an anti-radiation D flip-flop based on interconnection line crosstalk calculation. The anti-radiation D flip-flop comprises a cascade structure of a master latch module and a slave latch module, the primary latch module converts an input signal into a dual-node redundant signal through a first interconnection line crosstalk circuit (CC1), and logic storage of triggering high output only by dual high input is realized by capacitive coupling of L1-L3 and L2-L3; the slave latch module generates redundant signals L4 / L5 through a second interconnection line crosstalk circuit, and error correction is carried out on CC2 output and direct transmission signals in combination with a Muller C unit. The D flip-flop only needs 16 transistors with the minimum size, and the number of the transistors is reduced by 67% compared with that of a traditional TMR; asynchronous reset is supported, and the L3 / L6 is forced to be charged to a high level during reset; the capacitive coupling strength is controlled through metal layer wiring, and the reliability of a spaceflight electronic system in a radiation environment is remarkably improved.

The invention discloses a performance simulation calculation method for an aviation hybrid electric power system. The method comprises the following steps: firstly, constructing a sub-component calculation model covering an aerodynamic thermal component, a power generation subsystem, a power conversion and transmission subsystem, a battery subsystem, a motor and an aerodynamic system; establishing a reverse logic calculation framework driven by a load side demand, and realizing hierarchical reverse parameter solution from a load end to a power source end; and establishing a power balance equation at a bus end, carrying out iterative solution by adopting a Newton-Rafson algorithm, and realizing dynamic distribution and coordination control of multi-source energy in combination with an energy constraint module. According to the method, through a reverse solution and bus end balance strategy, the simulation calculation efficiency and convergence of the complex aviation hybrid electric power system are remarkably improved, and meanwhile, the adaptability and expandability of the model to different topological architectures and task profiles are enhanced; and an efficient and high-credibility calculation tool is provided for design, performance evaluation and energy management strategy optimization of the hybrid electric propulsion system of the aircraft.

An apparatus is described. The apparatus includes a rack shelf back interface. The rack shelf back interface has first and second flanges to mount to a rack's rear facing rack mounts. The rack shelf back interface has a power connector610 on an inside of a back face of the rack shelf interface, the power connector to mate with a corresponding power connector on an electronic system that is to be installed in the rack shelf. The rack shelf back interface has an alignment feature on the inside of the back face of the rack shelf interface to ensure that the power connector properly mates with the corresponding power connector.

The invention provides a transistor device, a manufacturing method, a power module and a power conversion circuit. The transistor device comprises a first doping type substrate, a first doping type buffer layer and a first doping type drift layer which are stacked in sequence, active columns arranged in an array are arranged in the first doping type drift layer, and the top surfaces of the active columns are flush with the top surface of the first doping type drift layer; the active columns comprise first active columns and second active columns, gate grooves are formed between the first active columns, source grooves are formed between the second active columns, and the depth of the source grooves is larger than that of the gate grooves; the grid grooves are formed in the two sides of the source groove, one of the two sides of the grid grooves is the grid groove, the other one of the two sides of the grid grooves is the source groove, or the grid grooves are formed in the two sides of the grid grooves. The avalanche reliability of the device is remarkably enhanced, and the requirement of a power electronic system for a high-reliability device is met.

An auxiliary device and an electronic system are provided. The auxiliary device includes a case body and a control assembly. The case body defines an accommodating cavity, the accommodating cavity defines an opening at one side thereof, and the accommodating cavity is configured to accommodate a mobile terminal. The control assembly is disposed in the accommodating cavity, and the control assembly is communicatively connected to the mobile terminal. The control assembly includes a transceiver module, a processing module, and an operation module, the processing module is respectively electrically connected to the transceiver module and the operation module, the transceiver module is communicatively connected to the mobile terminal, the operation module is configured to send an operation signal to the processing module, the processing module is configured to receive the operation signal and send the operation signal to the mobile terminal through the transceiver module.

Methods, systems, and devices for techniques for generating a shared secret for an electronic system are described. A memory system may identify an initial key pair and exchange a public key of the key pair with a public key associated with a server. The memory system and the server may each generate a shared secret. In some cases, the memory system and the server may use the shared secret to generate a device identifier for the memory system, for example by incorporating the device identifier into a cryptographic representation of a software layer of the memory system. The memory system and the server may use the device identifier to generate one or more asymmetric key pairs, which may be used by the server to authenticate the memory system.

A microelectronic device includes a first memory array structure including a first array region including first memory cells within a horizontal area of the first array region, each of the first memory cells having a first access device and a first storage node device vertically underlying and coupled to the first access device, a first control circuitry structure vertically overlying and attached to the first memory array structure at a boundary of the first memory array structure vertically closer to the first access devices of the first memory cells than the first storage node devices of the first memory cells, and a first shield structure vertically interposed between the first memory cells of the first memory array structure and the first control circuitry structure.