28results about "Logical operation testing" patented technology

A quantum computing system and methods for performing fusion based quantum computing on encoded qubits. A fusion controller sequentially performs a series of fusion measurements on respective photonic quantum modes of first and second encoded qubits to obtain a respective series of classical measurement results. For respective fusion measurements of the series of fusion measurements, a basis for performing the respective fusion measurement is selected based on classical measurement results of previous fusion measurements. An encoded fusion measurement result is determined based on the classical measurement results, and the encoded fusion measurement result is stored in a memory medium.

The present invention discloses a method, system and medium for fault analysis and cross-domain optimization of human-machine collaborative functional testing, which relates to the field of electronic information technology, including: constructing a fault tree, based on reverse quantitative analysis of the fault tree structure, converting the test ratio of intermediate events corresponding to test items into the test ratio of bottom events, calculating the product of the probability of occurrence of the bottom event and the test ratio of the bottom event without functional testing, and obtaining the probability of the motherboard being missed and defective; constructing a test ratio optimization model for the motherboard functional testing process, constructing the objective function of the test ratio optimization model based on the test ratio of the test items and the probability of the motherboard being missed and defective, solving the test ratio optimization model to obtain the optimal motherboard functional testing strategy, so as to test the motherboard; the cross-domain overall optimization method for functional testing improves the cross-domain overall optimization capability, and realizes cost reduction and efficiency improvement in the motherboard functional testing process.

The present invention discloses a chip test process automatic update method and system, which realizes the dynamic update, information transmission and parameter verification of the test process through automated means, so as to solve the problems of low efficiency and high error rate of existing test process management. The core of the present invention is to establish a chip test process automatic update system, which automatically identifies and configures the appropriate test process by reading batch attribute values, reducing human operation intervention. The system process covers the whole process from batch information acquisition, data verification to automatic configuration of test machines, and realizes efficient information matching and updating by designing configuration tables. Compared with the existing technology, the automatic update function in the present invention reduces human intervention and reconstruction of the test process, and significantly improves the test efficiency; through the automatic acquisition and automatic configuration of batch attributes, flexible management of the test process is realized, adapting to the testing requirements of different batches and products, and improving the adaptability and scalability of the system.

Run-time logic built-in self-test (LBIST) may be performed, while ensuring operational continuity. The compute elements in a machine learning accelerator contain LBIST circuitry that performs logic testing of the functional circuitry in the compute element. The LBIST circuitry may be self-sufficient, meaning that it contains the data and instructions needed to run and evaluate these tests. An LBIST manager enables the logic testing during idle time of the functional circuitry between blocks of statically scheduled instructions. As a result, the LBIST circuitry can perform the logic tests without disrupting the computation of the machine learning network.

The invention discloses an interrupt mechanism verification method and system, a storage medium and a computer program product. The method comprises the following steps: performing initialization configuration on an interrupt register of tested equipment through verification platform simulation software; corresponding verification is carried out on the monitored at least one interrupt event through the verification platform according to the interrupt mechanism, and the verification comprises interrupt vector mapping verification, double-shielding control verification and interrupt compensation logic verification. According to the method, by executing interrupt vector mapping verification, double-shielding control verification and interrupt compensation logic verification, whether equipment can normally use an MSI-X mechanism to report the interrupt event can be verified, and the integrity and complexity verification requirements of the MSI-X interrupt mechanism are met.

The invention provides a cell library simulation test method and device, electronic equipment and a computer storage medium. The cell library simulation test method comprises the steps of obtaining a layout of a cell library chip; isolating the test chain, and independently carrying out layout wiring on the test chain to generate test chain parasitic information; performing analog simulation on the test chain based on the test chain parasitic information to obtain an analog simulation value; combining the test chain with each partition in the layout to generate global parasitic information; performing global digital simulation on the layout by using the global parasitic information to obtain a digital simulation value; and according to the analog simulation value and the digital simulation value, obtaining a simulation result of the corresponding cell library. The test chain isolation is carried out on the cell library to independently carry out analog simulation, and digital simulation is carried out globally, so that an analog simulation value can be obtained with relatively high precision, a digital simulation value can be obtained with relatively high efficiency, and then an accurate simulation result is obtained by integrating the analog simulation value and the digital simulation value; the problem of how to improve the simulation test precision of the cell library is solved.

An embodiment of the present invention provides a receiver, a memory, and a test method. The receiver includes: a signal receiving module, which includes a first MOS transistor and a second MOS transistor. The gate of the first MOS transistor is used to receive a reference signal, and the gate of the second MOS transistor is used to receive a data signal to output a comparison signal, where the comparison signal is used to represent the magnitude relationship between the voltage value of the reference signal and the voltage value of the data signal; an adjustment module, which includes a third MOS transistor. The source of the third MOS transistor is connected to the source of the first MOS transistor, the drain of the third MOS transistor is connected to the drain of the first MOS transistor, and the gate of the third MOS transistor is used to receive an adjustment signal. The embodiment of the present invention is beneficial to expanding the range of the effective recognition window of the data signal.

The application discloses a kind of inference enhancement method and system for automated RTL debugging, method includes the following steps: by the mixed error injection mechanism of rule and LLM combination constructs diversified debugging sample, and utilizes GPT-4 to step level error positioning annotation to error CoT;Model training adopts gradual optimization process, so that it has the ability to evaluate the correctness of each step reasoning;In the reasoning phase, the candidate repair path of multiple strip CoT is generated in parallel by the generation model;Process reward model then carries out reliability scoring to each step of each path, and selects the path with the highest comprehensive score as the final output;The present application realizes the explicit supervision of intermediate reasoning, ensures that the debugging process is not only correct in results, but also reliable and traceable in logic, greatly improves the debugging success rate in complex RTL scenario.

The invention provides a processor verification method and device, electronic equipment and a storage medium, and relates to the technical field of processors, and the method comprises the steps: obtaining first instruction information corresponding to a to-be-verified processor; determining second instruction information corresponding to the reference model based on the first instruction information; based on the first instruction information and the second instruction information, determining a verification result of the to-be-verified processor; the verification result is used for representing whether the instruction set architecture behavior in the tested processor conforms to the standard definition of the instruction set architecture or not. The instruction information of the to-be-verified processor and the instruction information of the reference model are compared with each other with the instruction as the granularity, so that errors of the processor in instruction execution and memory access operation can be accurately detected in the verification process, and the verification accuracy and efficiency of the to-be-verified processor are improved.

The invention discloses a man-machine cooperation function test fault analysis and cross-domain optimization method and system and a medium, and relates to the technical field of electronic information, and the method comprises the steps: constructing a fault tree, carrying out the reverse quantitative analysis based on a fault tree structure, converting the test proportion of a test item corresponding to an intermediate event into the test proportion of a bottom event, and carrying out the fault analysis. Calculating the product of the occurrence probability of the bottom event and the test proportion of the bottom event which is not subjected to the function test, so as to obtain the probability of leak detection and badness of the mainboard; a test proportion optimization model oriented to the mainboard function test process is constructed, an objective function of the test proportion optimization model is constructed based on the test proportion of the test items and the probability that the mainboard is missed and bad, and the test proportion optimization model is solved to obtain an optimal mainboard function test strategy so as to test the mainboard; according to the function test cross-domain overall optimization method, the cross-domain overall optimization capacity is improved, and cost reduction and efficiency improvement in the mainboard function test process are achieved.

The invention discloses an embedded device debugging method and system based on a real-time environment, and belongs to the technical field of embedded systems. The invention discloses an embedded equipment debugging method based on a real-time environment. The method comprises the following steps: S1, constructing a compiling environment; s2, obtaining an embedded equipment debugging platform based on a real-time environment; s3, deploying an intelligent gateway; s4, debugging the embedded equipment; and S5, carrying out analysis and visual display on the debugging data of the embedded equipment. According to the invention, the problems of unreliable response time, increased hardware risk and low debugging efficiency in the prior art are solved. According to the method, the debugging efficiency is remarkably improved, the burden on resource-limited equipment is reduced, the real-time task execution efficiency is optimized, the development efficiency and reliability of embedded equipment are improved, the reliability of response time is improved, potential security holes can be prevented from being utilized, and it is ensured that cache service can automatically capture and cache hot data; and the debugging efficiency is improved.

A signal transmission device includes a first chip fed with an input pulse signal and a second chip that drives a switching device by generating an output pulse signal according to the input pulse signal through isolated communication with the first chip. The second chip includes a self-diagnosis circuit that checks whether individual parts of the second chip are operating properly in response to a self-diagnosis instruction transmitted from the first chip only when the output pulse signal is at a logic level corresponding to an off state.

The present disclosure provides a test control circuit and a test control method for a processor. The processor includes a plurality of test access ports connected in parallel between a signal input end and a signal output end. The signal input end is directly connected to a test signal end to receive a test signal and control whether the plurality of test access ports turn on to input the test signal. The test control circuit includes: a logic selection circuit connected to the signal input end, the signal output end, and the test signal end; a port selection circuit connected to the logic selection circuit. The logic selection circuit outputs a first selection signal to the port selection circuit based on the test signal received from the test signal end. The port selection circuit performs port selection in response to the first selection signal and outputs a second selection signal. The signal input end and the signal output end control one or more of the plurality of test access ports to turn on to input the test signal and turn on to output test data based on the second selection signal.

Embodiments of the disclosure provide a receiver, a memory, and a testing method. The receiver includes: a signal receiving module, including a first MOS transistor and a second MOS transistor, where a gate of the first MOS transistor is configured to receive a reference signal and a gate of the second MOS transistor is configured to receive a data signal, and the signal receiving module is configured to output a comparison signal, the comparison signal being configured to represent a magnitude relationship between a voltage value of the reference signal and a voltage value of the data signal; and an adjusting module, including a third MOS transistor, where a source of the third MOS transistor is connected to a source of the first MOS transistor, a drain of the third MOS transistor is connected to a drain of the first MOS transistor, and a gate of the third MOS transistor is configured to receive an adjusting signal. The embodiments of the disclosure facilitate enlarging the range of an effective recognition window of the data signal.

The embodiment of the invention provides a bad chip recovery method and device and related equipment, and the method comprises the steps: obtaining a preset chip, a chip architecture at least comprises IO core particles, the IO core particles are provided with a plurality of IO protocol controllers of different types, and the plurality of IO protocol controllers of different types share a physical layer, and are used for achieving different IO protocols; wherein, corresponding to the realization of different IO protocols, the IO core particles are provided with different packaging positions in the preset chip; the multiple IO protocol controllers are tested, the recovery types of the IO core particles are determined, and the recovery types correspond to the failure conditions of the multiple IO protocol controllers and are used for indicating the recovery states of the IO core particles; and according to the packaging position, packaging the IO core particles of the corresponding recovery type to obtain a recovery chip. According to the embodiment of the invention, the recycling rate of the core particles can be improved, and the cost of chips is reduced.

The invention provides an MCU chip communication fault intelligent diagnosis method and device, equipment and a medium, and the method comprises the steps: collecting a chip communication interface signal, obtaining communication waveform data, and carrying out the preprocessing of the communication waveform data, and obtaining time series data; inputting the time sequence data into a fault detection and parameter prediction model trained by a communication waveform data set of a simulation MCU chip communication fault type, and obtaining a fault classification result and a physical parameter prediction value of fault determination; fitting a historical multi-dimensional physical parameter sample to obtain a judgment boundary; and mapping the physical parameter predicted value to a multi-dimensional physical parameter space to obtain a vector, calculating a minimum weighted distance from the vector to a judgment boundary, determining a corresponding MCU chip communication safety margin, and comparing a preset safety margin judgment threshold to determine the communication state of the MCU chip. The reliability of the final MCU chip and the overall test verification efficiency are improved, and the contradiction between efficiency and depth in the prior art is solved.

The embodiment of the invention provides a bad chip recovery method and device and related equipment, and the method comprises the steps: obtaining a preset chip, the preset chip comprises a plurality of core particles, the core particles comprise a plurality of groups of IO modules which are symmetrically distributed, and the IO modules are correspondingly provided with IO numbers for indicating the placement positions of the IO modules in the core particles; wherein different chip particles are provided with different packaging positions in the preset chip; testing the plurality of groups of IO modules, and determining failure conditions of the plurality of groups of IO modules; according to the failure condition, the recovery type of the core particles where the multiple groups of IO modules are located is determined, and the IO numbers of the failure IO modules are recorded; according to the recorded IO number, determining a packaging strategy of the core particles of the corresponding recovery type; and according to the packaging position and the packaging strategy, packaging the core particles of the corresponding recovery type to obtain a recovered chip, thereby improving the recovery utilization rate of the core particles and reducing the cost of the chip.

An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.

The invention discloses a memory damage detection method and device, electronic equipment and a readable storage medium, and belongs to the technical field of memories. The method comprises the steps that under the condition that access operation for any target memory object is obtained, multiple real-time feature values of the target memory object are collected and based on the target memory object, and a real-time verification code to be verified is generated; obtaining a reference verification code of the target memory object from the target space; the reference verification code is generated based on a plurality of characteristic values of the collected target memory object at a historical moment; verifying the verification code to be verified based on the reference verification code, and continuing to execute the access operation under the condition that the verification code to be verified passes the verification; or, under the condition that the verification code to be verified does not pass verification, it is determined that the memory is damaged. The damage of the memory can be found in time, the process is realized through pure software, special hardware is not needed, only a small amount of extra memory is occupied, the performance overhead is small, and the real-time performance is high.

The invention relates to a memory self-checking method and device and electronic equipment. The method comprises the steps of determining a target self-checking mode in response to a self-checking enabling instruction issued for a memory; if the target self-check mode comprises a pseudo-random self-check mode, performing multiple rounds of random self-check on a target address space of the memory; each round of random self-check comprises the steps of generating a random write address, a random write length and random write data, and writing the random write data into the memory based on the random write address and the random write length; generating a random read address and a random read length, and reading the first data from the memory based on the random read address and the random read length; the random read address and the random write address correspond to the same characteristic polynomial and seed, and the random read length and the random write length correspond to the same characteristic polynomial and seed; and performing data comparison on the random write data and the first data to obtain a random self-check result of the round. The method can improve the self-checking effect and reduce the error code problem.

Embodiments of the present invention relate to an apparatus and method for checking a process and an electronic control apparatus. An apparatus for checking a process can include a conversion controller configured to control conversion into at least one process monitoring message by inputting a specific value into a virtual area included in at least one message corresponding to a preset operation when the preset operation is performed in serial communication, and a check controller configured to control a check process based on the process monitoring message.

A quantum computing system and methods for performing fusion based quantum computing on encoded qubits. A fusion controller sequentially performs a series of fusion measurements on respective photonic quantum modes of first and second encoded qubits to obtain a respective series of classical measurement results. For respective fusion measurements of the series of fusion measurements, a basis for performing the respective fusion measurement is selected based on classical measurement results of previous fusion measurements. An encoded fusion measurement result is determined based on the classical measurement results, and the encoded fusion measurement result is stored in a memory medium.

An information processing apparatus includes an integrated circuit that is capable of reconfiguring a logic circuit, executes data processing, and in a case where an error is generated in the data processing, acquires signal data from an acquisition target position set for a circuit portion that performs the data processing, and then outputs the signal data, a narrowing-down unit that narrows down an analysis target depending on the generated error, and a change unit that changes the acquisition target position depending on a result of a narrowing down by the narrowing-down unit after the signal data is output from the integrated circuit.

A method of verifying processing logic of a graphics processing unit receives a test task including a predefined set of instructions for execution on the graphics processing unit, the predefined set of instructions being configured to perform a predetermined set of operations on the graphics processing unit when executed for predefined input data. In a test phase, the test task is processed by executing the predefined set of instructions for the predefined input data first and second times at the graphics processing unit so as to, respectively, generate first and second outputs. A fault signal is raised if the first and second outputs do not match.

A quantum computing system and methods for performing fault-tolerant quantum computing. A fusion controller sequentially performs a series of fusion measurements on different fusion sites of a plurality of fusion sites to obtain a respective series of classical measurement results. The series of fusion measurements is performed on quantum modes of a logical qubit. For respective fusion measurements of the series of fusion measurements, a basis for performing the respective fusion measurement is selected based on classical measurement results of previous fusion measurements. The series of classical measurement results are in the memory medium.

The invention relates to the technical field of data storage, and discloses an LPDDR5 digital signal capturing method based on a logic analyzer, and the method comprises the steps: carrying out ball mounting welding on CA signals and CS signals of A / B channels of LPDDR5 and to-be-tested instruments on a test board, and selecting corresponding plots according to the actual connection condition, the number of the to-be-tested instruments being eight; during connection, Plot is distributed according to actually connected signal lines, sampling clocks of each group of Plot are uniformly connected to a CKt / c signal, impedance of an instrument to be tested is set according to input impedance matching of a logic analyzer, the LPDDR5 adopts a PODL level standard, and a voltage threshold value of the instrument to be tested is set as VDDQ / 2; and a special protocol decoder of the LPDDR5 is loaded in logic analyzer software. According to the invention, the problem of functional faults or performance bottlenecks existing in the final positioning digital system is solved.

The application provides a server start-up sequence debugging system applied to a server, which comprises a voltage regulator, a CPLD, a transmission module and a display module; the voltage regulator is used to adjust and transmit power-on signals required by each component during server start-up, to power on the server, and to transmit the power-on signals to the CPLD; the CPLD is used to receive the power-on signals transmitted by the voltage regulator and to distribute the power-on signals to each component of the server; the transmission module is used to receive data, to convert the data, and then to transmit the converted data to the display module; and the display module is used to display power-on signals that do not meet standard requirements in the power-on process of the server according to the data.