79 results about "Validation testing" patented technology

A computer-implemented method includes customizing artifacts of a large language model (LLM). A generative artificial intelligence (AI) (genAI) function of a software application that interfaces with the LLM and is instrumented for customer-side management is activated, as a genAI application. A verification test is activated to determine whether interactions between the LLM and genAI application generate expected results. Based on a result of the verification test, either adjusting the artifacts of the LLM or updating the genAI function of the software application. A new verification test is defined to determine whether interactions between the LLM and genAI application generate expected results. The new verification test is activated.

The embodiment of the invention discloses a security deployment method and device for enterprise-level applications and a medium, and relates to the technical field of security deployment, and the method comprises the steps: obtaining application topological graph data generated by a preset visual development platform, so as to split the application topological graph data into an atomized micro-service unit set through a quantization deconstruction engine, generating a micro-service dependency tree; scanning the target deployment environment, extracting an environment feature fingerprint of the target deployment environment, and generating an environment adaptation layer code according to the environment feature fingerprint; injecting an environment adaptation layer code into each atomized micro-service unit to generate an environment perception type micro-service package, and constructing a cross-cloud communication link matrix based on the micro-service dependency tree; and based on the environment-aware micro-service packet and the cross-cloud communication link matrix, executing a deployment verification test in the sandbox environment, generating a deployment verification report, and according to the deployment verification report, distributing the environment-aware micro-service packet to a target deployment environment node.

The invention provides a stress evaluation method and system for a TSV packaging structure, and relates to the technical field of semiconductor packaging, and the method comprises the steps: constructing a global coarse mesh model, cutting to generate a local TSV sub-model, and generating a failure feature mapping table; based on the failure feature mapping table and a preset process temperature curve, coupling solution is carried out on the local TSV sub-model, and a multi-physical field data set is output; training a failure probability prediction model by combining the failure feature mapping table based on the multi-physics field data set, and generating a digital failure atlas template; performing dynamic risk assessment based on the digital failure atlas template, the real-time process parameters and the dynamically calculated electrothermal coupling parameters, and generating a failure risk report; analyzing the failure risk report, and generating a mode-based optimization guide; and performing spatial deviation comparison based on the verification test data executed by the mode-based optimization guide, and when the spatial deviation exceeds a preset threshold value, outputting a failure map version updating mark and triggering the failure feature mapping table to iteratively update.

Systems and methods provide a HybridOps model for the identification, capture, isolation, feature engineering and adjudication of source signal data signatures for inclusion in calibration quality standard reference signal data signature libraries that improve machine learning and validation, reduces model bias and reduces model drift. The HybridOps model may include an “unlocked” AI / ML (machine learning enabled) public facing deployment pipeline in parallel with a clone AI / ML deployed in an internal development environment using a ML-Ops pipeline and in parallel with a clone“locked” AI / ML (machine learning disabled) as a standard reference. The three deployed models enables monitoring and measuring model drift, context drift and product progression for improved verification and validation of model reliability. The parallel environment AI / ML testing using randomized learning, validation, testing sets drawn from calibration quality adjudicated standard reference signal data signature libraries provides for validation, verification and test to failure procedures.

The systems and methods disclosed herein enable evaluation of machine learning model outputs within a virtual environment. The disclosed model validation platform enables testing of code generated for detection of malicious or anomalous outputs. For example, the model validation platform can construct a virtual machine isolated from the system and test model-generated code for validation of LLM-generated outputs. In some implementations, the model validation platform determines parameters of the virtual machine and / or associated validation test based on an evaluation of the machine learning model's output and / or the associated underlying prompt. For example, the parameters of the validation test depend on an evaluation of the user or the provided input (e.g., depending on the presence of sensitive data within the prompt). By doing so, the system enables dynamic evaluation of machine learning model outputs to improve the security and robustness of associated generated code.

The invention relates to a verification and test integrated platform for a probe processor, and belongs to the technical field of processor verification and test. A probe processor adopts a self-defined probe instruction and a special probe operator unit, and a traditional verification and test mode is difficult to consider the requirements of module-level verification and system-level test. The UVM verification system, the test system and the management module are integrated, and unified management of verification and test is achieved. The UVM verification system is based on a UVM architecture, a virtual interface is associated with a to-be-tested unit (such as a probe operator, GPIO, UART and the like) of a probe processor through a forced binding mechanism, and module-level verification is achieved. The test system is responsible for compiling test codes into machine codes and loading the machine codes to the probe processor by starting the read-only memory, and system-level test is executed by the probe processor. And the management module adopts an automatic script to realize intelligent switching between verification and test modes, so that the probe processor is suitable for different test scenes, the test efficiency is improved, and the environmental redundancy is reduced. According to the method, the reusability of the test case is improved, the test consistency is ensured, the resource utilization rate is optimized, the automation degree and efficiency of verification are improved, and the method is suitable for efficient verification and test of probe processors and similar architecture chips.

Systems and methods for bias testing and remediation are disclosed. Decentralized Web Application Testing Systems use a Holochain framework to distribute testing workloads across Full Nodes and Lightning Nodes. A Holochain Node Management Application for configuring nodes, a UI Application creates test cases, and a Version Management System tracks changes. Test results are stored and analyzed in a Test Result Store, with a Bias Intelligence module detecting biases and generating additional test cases. A Consensus Algorithm validates test cases through decentralized nomination. An AI-Driven Defect Remediation System automates defect detection, root cause analysis, and remediation using AI modules. Machine learning algorithms identify patterns and anomalies, while NLP techniques generate code fixes. Predictive maintenance monitors application performance to preemptively address issues. A feedback loop mechanism continuously improves AI models through reinforcement learning. Together, these systems provide a holistic approach to web application testing and maintenance.

The invention discloses a chip parameter verification method and device, equipment and a storage medium. The chip parameter verification method comprises the steps of sampling a to-be-tested parameter space of a chip to obtain a parameter point file; performing a regression test on the parameter point file to obtain verification test results, and associating each verification test result with the corresponding parameter point to obtain a data pair set; performing parameter point iteration prediction on the set through a model according to the data; and when it is determined that the predicted parameter points meet the optimization target, taking the predicted parameter points as to-be-applied target parameter points of the chip. The parameter point file is obtained by sampling from the to-be-tested parameter space, and the sampling result is used for the regression verification test, so that the number of tasks needing to be executed is reduced, the overall verification investment is reduced, fitting and prediction are carried out through the model according to the verification test result, the coupling effect and hidden defects among parameters are conveniently found, and the verification efficiency is improved. And the accuracy of the determined target parameter is improved.

A diversified validation test suite application (DVTSA) for a generative AI powered tool or large language model (LLM) tool includes at least first, second, and third control logics. The first control logic receives a seed test input or user input, analyzes the seed test input or user input, and extracts key elements for variations. The second control logic performs a coverage measurement of outputs of the first control logic. The third control logic causes a human validator to evaluate outputs of the second control logic relative to predefined coverage metrics and selectively and continuously iterate to cause outputs of the second control logic to increase LLM tool input robustness and output robustness from a first level to a second level greater than the first level, in both production and pre-production LLM tool processes.

This disclosure describes systems, methods, and devices related to enhanced validation of video codecs. A device may receive validation results for a video codec using a first computer programming language, the validation results indicative of invocations of functions and conditions of the code; identify, from the validation results, a first validation test that invoked a first function or condition of the code; identify, from the validation results, a second validation test that invoked the first function or condition of the code; determine, from the validation results, that the first validation test and the second validation test overlap in invoking the first function or condition of the code using the first computer programming language; and generate, based on the overlap, a first subset of the validation tests with which to validate code of the video codec using a second computer programming language.

The invention discloses an automatic generation method of an API process scene based on a gateway and a large model, and relates to the technical field of API testing. The method comprises the steps of marking and executing a test case, capturing and verifying gateway data, exporting a JMX test script, exporting request response details, intelligently analyzing a large model, storing returned content as a standard JMX file, and executing verification. Through cooperative work of the gateway and the large model, automatic capture, data association analysis and test script generation of an API test scene are realized, the generation time of the API test script is shortened from an hour level to a minute level, and the efficiency is improved by more than 10 times; non-professionals can generate complex test scripts through simple operation, and dependence on professional testers is reduced; a large model automatically analyzes data association, and omission and errors caused by manual analysis are avoided; full-process automation from interface calling and capturing to test script generation is achieved, and tool switching is reduced.

A server system sends, via a linearly ordered communication orbit, to computational machines at a first subset of nodes in a computer network, a set of local environment verification tests and a set of mappings that map results of the local environment verification tests into a set of risk scores. Requests sent by the server system cause the computational machines at the plurality of nodes to: locally evaluate the set of local environment verification tests to produce test results, and locally map the test results using the set of mappings into a set of risk scores. Queries sent by the server cause the computational machines at the plurality of nodes to return to the server system at least a portion of the test results and risk scores. The server, identifies, based on the received test results and risk scores, computational machines and / or control categories having risk scores satisfying predefined criteria.

According to the test method for the high-low priority scheduling mechanism of the A664 switch, a minimum test environment is established, an A664 tester with four physical ports is used, and verification cases of high-priority data frame priority forwarding, priority data integrity and the number of high-low priority buffer areas in a congestion scene are designed. The integrity and accuracy of high-low priority transmission function verification are ensured, and the problem of verification test of the high-low priority working mechanism of the A664 network in the prior art is effectively solved. The method is high in universality and can be suitable for various A664 network devices and application scenes.

The application discloses a PLC code generation and verification method based on a large language model, which comprises the following steps: generating multi-stage multi-modal input data, wherein the multi-stage multi-modal input data is used for representing user requirements and formulating a system design scheme according to a requirement analysis result; the multi-stage comprises a requirement analysis stage and a design stage of a complete engineering cycle; the multi-modal input comprises a P&I D diagram and natural language; then, PLC code is generated according to the multi-stage multi-modal input data; then, the generated PLC code is verified and tested, wherein the verification and testing comprises code verification and compiler verification; finally, the PLC code is deployed after the verification and testing of the PLC code are completed. The embodiment of the application has high accuracy and high automation degree, can provide a network security researcher with an efficient and accurate PLC code deployment method, and can be widely applied to the technical field of computers.

The present application provides a vehicle usage scenario simulation test method, device, equipment, medium and program product, which obtains and parses the simulation configuration information input by the developer; according to the parsing result of the simulation configuration information, loads the scenario configuration data corresponding to the simulation configuration information, and determines the scenario simulation data according to the scenario configuration data and the preset scenario simulation protocol; according to the transmission configuration information in the parsing result, sends the scenario simulation data to the test engine to change the vehicle usage scenario in the test engine, and tests the various preset services corresponding to the vehicle usage scenario. It solves the technical problem in the prior art that the vehicle usage scenario is uncontrollable during vehicle research and development testing, resulting in long research and development time and high testing costs. It achieves the technical effect of providing vehicle development and testing personnel with a simple and fast testing method when verifying scenario services, reducing the waiting time for test scenarios, and reducing the cost of development and testing.

An apparatus and method is provided for simulating a physical computer system using virtualization. The disclosed system virtualizes devices of a physical computer system by modeling hardware and software components that are physically present within the physical computer system. The system simulates changing at least one of a piece of hardware or software in the virtualized computer system and assesses an effect of the change in the virtualized computer system to determine a potential effect of the change if the change were implemented on the physical computer system.

Techniques are described for a data recovery validation test. In examples, a processor receives a command to be included in the validation test that is configured to validate performance of an activity by a server prior to a failure to perform the activity by the server. The processor stores the validation test including the command on a memory device, and prior to the failure of the activity by the server, executes the validation test including the command responsive to an input. The processor receives results of the validation test corresponding to the command and indicating whether the server performed the activity in accordance with a standard for the activity during the validation test. The processor provides the results of the validation test in a user interface.

The application discloses a kind of integrated power supply basic module test method and system, the method includes: establishing integrated power supply basic module unified test data model, based on the model, the basic module test index verification data sequence is constructed, with the sequence as foundation, local data and task processing thread are established to carry out the processing of each test data;Create local communication thread, and the automatic verification of each index of integrated power supply basic module is carried out in combination with test index verification data sequence and data and task processing thread, and module performance index verification test report is generated;Create enterprise cloud end interactive thread and carry out the association of test report and cloud end order data.The application improves the production test efficiency of integrated power supply basic module.

The application discloses a complex electronic hardware compliance verification test system based on simulation vector multiplexing, and belongs to the technical field of electronic hardware testing.The simulation test vector generation module is configured to receive a hardware design requirement document, establish a requirement pin mapping table, encapsulate a simulation excitation vector with timing annotation, generate a test vector file, and design a high-fidelity verification module board card module, so that the board card module is kept consistent with a target product board card, the measured hardware circuit is connected, preset test points monitor signals of the measured hardware circuit, the core control module includes a timing reconstruction engine, the test vector file is read, an actual output vector file is generated, the actual output vector file is verified by an automatic verification closed loop module, a test report including a compliance evidence chain is generated, efficient simulation vector multiplexing can be realized, simulation and actual measurement timing behaviors are consistent and aligned, synchronous linkage of excitation application and response acquisition is realized, and verification efficiency and checking accuracy are improved.

A method comprises selecting a first data set including a first magnetic anomaly map of a given area, the first map having a first accuracy; selecting a second data set including geological data for the given area; sending the first and second data sets to a machine learning model; and generating a second magnetic anomaly map of the given area based on the first and second data sets, the second map having a second accuracy higher than the first accuracy. The method further comprises comparing the second map with a ground truth map to train the machine learning model; and performing a validation test of the trained machine learning model by sending an additional data set including held-out magnetic anomaly map data to the machine learning model. In response to a validation threshold being met, the trained machine learning model is used to generate higher accuracy magnetic anomaly maps.

A method of performing static verification of a circuit design that includes a number of circuit blocks, includes, in part, receiving a first model of a first block generated using a first version of a verification tool and having associated therewith data representative of a version number of each of a multitude of verification tests performed by the first version of the tool as well as associated first setup information. In response to the determination that, for each of the of tests performed, the version number of the test to be run on the circuit design is incompatible with the version number of the test performed by the first version of the tool, portions of the first model that were tested with the version number(s) of the test(s) determined to be incompatible with the version number(s) of the test(s) to be run on the circuit design are regenerated.

The invention discloses a storage capacity fraud detection method, through steps S1-1A to S1-4A, data distribution abnormity of a detected storage medium can be identified, the defect of single physical layer verification in the prior art is made up, the identification rate of software capacity expansion fraud is effectively improved, and through tests, the identification rate of the software capacity expansion fraud is improved to 99.7%. Through the steps S1-1B to S1-3B, the influence of the temperature on the detected storage medium can be quantified, the capacity shrinkage risk at the low temperature can be identified, and misjudgment of storage capacity fraud caused by the environment is avoided. Through the steps S2-1C to S2-2C, whether the detected storage medium has the file system compatibility fraud problem or not can be detected. Through the steps S2-1D to S2-4D, three verification tests can be carried out on three test areas obtained by dividing the detected storage medium according to the segmentation proportions of 0%-38%, 38%-62% and 62%-100%, the segmentation proportions can cover 98% of storage abnormal points, redundant tests are reduced, and the test efficiency is improved by 82%.

A computer-implemented method for performing a regulatory validation process is provided. The method includes receiving, via a web-based application, a request to initiate a validation study for a selected asset or process; retrieving, from a validation protocol database, a pre-approved validation protocol corresponding to a type of the selected asset or process; displaying, via a user interface, one or more verification tests of the validation protocol, each verification test having associated instructions, acceptance criteria, and / or required data entry fields; receiving, from an authenticated user, input data for at least one of the verification tests; receiving an electronic signature from the authenticated user, the electronic signature being applied using multi-factor authentication; automatically recording the user input data, electronic signature, and corresponding timestamps in an audit trail database; and generating, responsive to completion of the validation protocol, an electronic validation report in a compliance-ready format.

Generative artificial intelligence is applied to a manufacturing process to create a test plan for validation, including proof of execution of various test, process steps, and the like.

The invention provides an LVS verification method and device for an integrated circuit test structure, equipment and a medium, and the verification method comprises the steps: defining a design description of a to-be-verified test structure, and forming a design description file of the to-be-verified test structure; forming a layout file of the test structure to be verified according to the design description file and the PDK; forming a layout netlist file of the to-be-verified test structure based on the layout file; based on the design description file and the PDK, forming a circuit netlist file of the to-be-verified test structure through a pre-configured circuit netlist generation program; and carrying out LVS check on the layout netlist file and the circuit netlist file. According to the invention, the LVS check of the test structure can be quickly realized.

Automated verification and generation of coverage data for a circuit design includes generating, by computer hardware, valid value ranges for coverpoint variables of a circuit design based on constraints for the coverpoint variables. A regression test is run on the circuit design using a verification testbench to generate test results and sampled values for the coverpoint variables. The sampled values of the coverpoint variables from the regression test are classified by a machine learning model based on the test results. Coverage data for the regression test is generated by the computer hardware by assigning the sampled values of the coverpoint variables to different ones of a plurality of bins based on the classifying.

A method for providing an automated AI teaching and learning environment includes selecting an AI agent from an AI agent pool as a candidate AI agent according to performance of the AI agent after previous training and further according to capability requirements for capability-based training, and providing the capability-based training for the candidate AI agent. Providing the capability-based training includes acquiring first training data, generating a trained artificial intelligence (AI) agent by training the candidate AI agent to have at least one capability associated with using the first training data, generating synthetic validation data different from the synthetic training data, validating the trained AI agent by performing validation testing on the trained AI agent using first validation data that includes the synthetic validation data, and providing the trained AI agent as a validated AI agent after the validating the AI agent.

A system acquires verification software to be executed by a storage controller. The verification software includes a program for detecting tampering in the verification software. The system tampers with a part of the verification software according to an instruction from a user. The system installs the verification software tampered with at the part in the storage controller and activates the verification software. The system presents, to the user, the result of verification of tampering by the verification software which has been received from the storage controller.

The systems and methods disclosed herein enable evaluation of machine learning model outputs within a virtual environment. The disclosed model validation platform enables testing of code generated for detection of malicious or anomalous outputs. For example, the model validation platform can construct a virtual machine isolated from the system and test model-generated code for validation of LLM- generated outputs. In some implementations, the model validation platform determines parameters of the virtual machine and / or associated validation test based on an evaluation of the machine learning model's output and / or the associated underlying prompt. For example, the parameters of the validation test depend on an evaluation of the user or the provided input (e.g., depending on the presence of sensitive data within the prompt). By doing so, the system enables dynamic evaluation of machine learning model outputs to improve the security and robustness of associated generated code.