16 results about "Analog processor" patented technology

Proposed herein are an apparatus for providing terrain information on a green and a method for providing terrain information on a green. According to one embodiment, there is proposed an apparatus for providing terrain information on a green, the apparatus including: a simulation processor configured to display a virtual golf course image regarding a green, a hole cup on the green, and a first ball; and a guide processor configured to display a guide path between the hole cup and the first ball to provide terrain information on the green.

A processor may receive an air dataset associated with a smart environment having one or more storage objects. The processor may simulate the smart environment using the air dataset. The processor may apply an optimization criteria to the simulation of the smart environment. The processor may generate an optimum smart environment design associated with an improved air condition level of the smart environment and the optimization criteria.

An analog processor includes an array of Configurable Analog Blocks ("CABs") to receive analog signals as vector input data. Each CAB includes an analog delay element storing multiple time steps of the vector input data, and an analog convolution layer applies a set of analog weights to the vector input data to generate vector output data. Analog parameter storage and control circuitry configure operation of the CAB to apply a data processing network to the vector input data. A switch matrix interconnects CABs and transmits analog vector signals between CABs without conversion to digital signals. The analog processor applies the data processing network to the vector input data by propagating analog vectors through the array such that each CAB applies a portion of the data processing network.

The invention relates to a method for designing a processor, which comprises the following steps of: acquiring performance data after running by utilizing an analog processor, and enabling initial hardware simulated by the analog processor to have a design improvement multiple relative to reference hardware, when the performance improvement of the performance data relative to the reference performance data of the reference hardware does not reach the design improvement multiple, adjusting initial software of the analog processor, and updating the analog processor according to the adjusted initial software; and repeating the steps until the performance improvement of the performance data relative to the reference performance data reaches the design improvement multiple. According to the method for designing the processor, resource waste caused by the fact that a hardware entity processor is adopted for design can be avoided, specification parameters or implementation strategies of hardware can be adjusted more conveniently, and the design efficiency of the processor is improved.

The invention provides an automatic circuit design method of a TAGE branch predictor, which comprises the following steps: constructing a superscalar front-end simulator comprising a branch prediction unit, an instruction cache, an instruction queue and a prediction information cache, and simulating processor front-end behaviors through parameterized configuration; a time sequence and combinatorial logic decoupling normal form is introduced into the branch prediction unit, the branch prediction unit is decomposed into a time sequence component and a combinatorial logic component, the time sequence component comprises a global historical register, a folding historical register and a multi-stage prediction table, and the combinatorial logic component comprises a metadata generation unit, a direction prediction unit, a table item updating unit and a historical maintenance unit; obtaining input and output data of the branch prediction unit in the execution process; and based on the input and output data, generating a hardware description language code of the combinatorial logic component by using an automatic circuit design algorithm so as to realize automatic circuit design of the TAGE branch predictor. Therefore, the design efficiency and the performance of automatically designing the branch prediction component can be improved.

Simulated interaction between processor hardware as part of processor functional verification includes, in an example, commencing a simulation in a simulation environment. The simulation executes a test case using a model of a processor core for functional verification of the processor core. It also includes monitoring progression of the simulation for a trigger condition for simulated interaction. Based on recognizing the trigger condition for simulated interaction at a point in the test case, it additionally includes changing an architected state of the model, where the changing directs the progression of the simulation, at the point in the test case, to simulate interaction between the processor core and another executing entity. Based on a determination to end the simulated interaction, it further includes continuing progression of the simulation from the point in the test case.

An automotive diagnostic digital training system comprising a virtual vehicle including a data simulating processor and a database in communication with the data simulating processor and having simulated, vehicle-specific vehicle data stored thereon. The data simulating processor is configured to access simulated vehicle data stored on the database and generate a signal including a desired set of simulated vehicle data. A student workstation is disposable in communication with the virtual vehicle. The student workstation includes a handheld diagnostic device configured to communicate with the virtual vehicle to receive the simulated, vehicle-specific vehicle data therefrom and generate a student input signal representative of a student diagnostic decision. An instructor controller is disposable in communication with the virtual vehicle and the student workstation, with the instructor controller being configured to provide instructor input regarding the desired set of simulated, vehicle-specific vehicle data and review the student input.

The application provides a clock management unit, a system on chip and an electronic device. The i-th group of low-power top interfaces of the interface selector is a first type of top interface, and the interface selector connects the i-th group of low-power top interfaces and the i-th group of low-power bottom interfaces in the interface selector; the i-th group of low-power top interfaces of the interface selector is a second type of top interface, and the interface selector connects the analog processor module and the i-th group of low-power distribution interfaces of the low-power distributor; and the clock controller performs clock management on the network on chip system according to the monitoring results of the low-power distributor, the target module and the analog processor module. When the processor module deployed on the top of the system on chip is increased or reduced, only the software configuration of the interface selector is needed, without changing the connection of the low-power distributor, without re-designing the code, and without re-dividing the chip layout, thereby reducing the overall design cost and improving the flexibility of clock management.

Embodiments of the present disclosure include techniques for simulating a circuit, such as a system on a chip (SoC). In various embodiments, the simulated circuit may include one or more processors. However, using a hardware description language (HDL) to emulate circuitry may execute firmware instructions using a virtualized processor, rather than using an HDL to emulate the processor. Certain instructions from the virtualized processor may be sent to the HDL simulation for execution during the simulation.

An analog processor includes an array of Configurable Analog Blocks ("CABs") to receive analog signals as vector input data. Each CAB includes an analog delay element storing multiple time steps of the vector input data, and an analog convolution layer applies a set of analog weights to the vector input data to generate vector output data. Analog parameter storage and control circuitry configure operation of the CAB to apply a data processing network to the vector input data. A switch matrix interconnects CABs and transmits analog vector signals between CABs without conversion to digital signals. The analog processor applies the data processing network to the vector input data by propagating analog vectors through the array such that each CAB applies a portion of the data processing network.

Systems and methods are disclosed for deep learning solutions with analog AI. Analog AI systems can outperform their digital counterparts in speed and energy efficiency since computations are conducted directly in memory and analog processors inherently support parallel operations. An analog AI system may comprise a DAC, a programming module, row / column switches, a crossbar array and an ADC. The DAC provides an analog signal to the row / column switches, which along with the programming module, select a phase of operation, i.e., a forward, backward, or update path. A crossbar array is a trainable neural network that operates in the analog domain and comprises a matrix of programmable resistors, e.g., memristor devices. The crossbar array couples an output in the analog domain to the ADC. The result is a digital output from the crossbar array processing architecture.

Systems and methods are disclosed for analog-to-digital-converter (ADC) solutions supporting analog AI deep learning systems. These systems can outperform their digital counterparts in speed and energy efficiency since computations are conducted directly in memory and analog processors inherently support parallel operations. ADCs play a crucial role in analog AI deep learning because they serve as the bridge between the analog and digital worlds. An analog AI deep learning system may comprise a DAC, a programming module, row / column switches, a crossbar array and an ADC. The ADC may comprise switches for time interleaving of an analog neural network output signal, received from the row / column switches associated with the crossbar array. The time interleaved signals are separately ported between two capacitive paths, and are subsequently coupled to separate inverters. A frequency signal is generated by a logic gate, which is coupled to a digital filter that generates an n-bit digital word.

Embodiments are directed to a new radio distributed unit (NRDU) simulation server for testing in 5G standalone (SA) communication network. The NRDU simulation server includes a memory, a processor, a communicator. The processor includes a test controller connected to the plurality of simulated UEs configured to receive at least one testing profile associated with a DUT and a multi user equipment (UE) simulator (MUCE) configured to dynamically generate a plurality of simulated UEs based on the at least one testing profile. The processor also includes a DU simulator configured to generate a plurality of simulated DUs based on the at least one testing profile; an IP security Manager (IPSEC MGR) configured to simulate internet protocol (IPSEC) functionality between at least one DU and the DUT; and a first traffic generator and a second traffic generator configured to generate a traffic profile based on the at least one testing profile.

The systems, devices, articles, and methods generally relate to sampling from an available probability distribution. The samples may be used to create a desirable probability distribution, for instance for use in computing values used in computational techniques including: Importance Sampling and Markov chain Monte Carlo systems. An analog processor may operate as a sample generator, for example by: programming the analog processor with a configuration of the number of programmable parameters for the analog processor, which corresponds to a probability distribution over qubits of the analog processor, evolving the analog processor, and reading out states for the qubits. The states for the qubits in the plurality of qubits correspond to a sample from the probability distribution. Operation of the sampling device may be summarized as including updating a set of samples to include the sample from the probability distribution, and returning the set of samples.

A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.