140 results about "Analog processor" patented technology

Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

An analog processor, for example a quantum processor may include a plurality of elongated qubits that are disposed with respect to one another such that each qubit may selectively be directly coupled to each of the other qubits via a single coupling device. Such may provide a fully interconnected topology.

A dynamic test generation method and apparatus enabling verification of the parallel instruction execution capabilities of VLIW processor systems is described. The test generator includes a user preference queue, a rules table, plurality of resource-related data structures, an instruction packer, and an instruction generator and simulator. The present invention generates a test by selecting instructions for parallel execution based upon resource availability as indicated by the resource-related data structures and the processor's instruction grouping rules, simulating the parallel execution of the instructions on a golden model, updating the resource-related data structures, and evaluating the updated architectural state of the golden model.

Discrete optimization problem are solved using an analog optimization device such as a quantum processor. Problems are solved using an objective function and at least one constraint corresponding to the discrete optimization problems. The objective function is converted into a first set of inputs and the at least one constraint is converted into a second set of inputs for the analog optimization device. A third set of inputs is generated which are indicative of at least one penalty coefficient. A final state of the analog optimization device corresponds to at least a portion of the solution to the discrete optimization problem.

Systems, devices, and methods for using an analog processor to solve computational problems. A digital processor is configured to track computational problem processing requests received from a plurality of different users, and to track at least one of a status and a processing cost for each of the computational problem processing requests. An analog processor, for example a quantum processor, is operable to assist in producing one or more solutions to computational problems identified by the computational problem processing requests via a physical evolution.

Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, for instance qubits, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

A circuit comprising a digital processor, analogue processing means, a digital to analogue converter for converting digital values output from the digital processor into analogue values which are processed by the analogue processing means, and an analogue to digital converter for converting resulting analogue values into digital values for input to the digital processor, wherein the analogue processing means comprises one or more analogue processors, and the circuit is dynamically reconfigurable under the control of the digital processor, such that analogue values are processed according to a first function by the analogue processing means, and following reconfiguration, analogue values are processed according to a second function by the analogue processing means.

Approaches to embedding source graphs into targets graphs in a computing system are disclosed. Such may be advantageously facilitate computation with computing systems that employ one or more analog processors, for example one or more quantum processors.

A second problem Hamiltonian may replace a first problem Hamiltonian during evolution of an analog processor (e.g., quantum processor) during a first iteration in solving a first problem. This may be repeated during a second, or further successive iterations on the first problem, following re-initialization of the analog processor. An analog processor may evolve under a first non-monotonic evolution schedule during a first iteration, and second non-monotonic evolution schedule under second, or additional non-monotonic evolution schedule under even further iterations. A first graph and second graph may each be processed to extract final states versus a plurality of evolution schedules, and a determination made as to whether the first graph is isomorphic with respect to the second graph. An analog processor may evolve by decreasing a temperature of, and a set of quantum fluctuations, within the analog processor until the analog processor reaches a state preferred by a problem Hamiltonian.

A hardware-accelerated simulator includes a storage memory and a program memory that are separately accessible by the simulation processor. The program memory stores instructions to be executed in order to simulate the chip. The storage memory is used to simulate the user memory. Since the program memory and storage memory are separately accessible by the simulation processor, the simulation of reads and writes to user memory does not block the transfer of instructions between the program memory and the simulation processor, thus increasing the speed of simulation. In one aspect, user memory addresses are mapped to storage memory addresses by adding a fixed, predetermined offset to the user memory address. Thus, no address translation is required at run-time.

Analog processors such as quantum processors are employed to predict the native structures of proteins based on a primary structure of a protein. A target graph may be created of sufficient size to permit embedding of all possible native multi-dimensional topologies of the protein. At least one location in a target graph may be assigned to represent a respective amino acid forming the protein. An energy function is generated based assigned locations in the target graph. The energy function is mapped onto an analog processor, which is evolved from an initial state to a final state, the final state predicting a native structure of the protein.

Systems and methods for debugging software and/or hardware are disclosed. A processor may execute a program for a certain amount of time. The context of the processor at the end of that time may then be made available to a simulator operable to simulate the processor. The program can then be executed from that point on the simulator using the context. Additionally, a context resulting from the execution of the program on the simulator may result and be restored to the processor for continued execution.

An image processing apparatus includes a scatter simulation processor which processes measured sinograms generated from imaging data acquired for an imaging subject by an imaging apparatus to produce a scatter sinogram that represents a shape of scatter contribution. A scatter scaling processor utilizesa Monte Carlo simulation to determine a scatter fraction and scales the scatter sinogram to generate a scaled scatter sinogram that matches the scatter contribution in the measured sinogram. A reconstruction processor reconstructs the imaging data into an image representation using the scaled scatter sinogram for scatter correction.

A method is described for simulating a set of instructions to be executed on a processor. The method comprises performing a functional simulation of the processor over a number of simulation cycles. Performing the functional simulation of the processor thereby may comprise using an analytical model comprising a timing estimator and estimating during the functional simulation timing information of the processor.

An analog front-end circuit that controls an imaging device and processes an analog image signal output from the imaging device comprises: an analog processor that receives an analog image signal from the imaging device, provides the image signal with predetermined processing, and outputs a resultant signal; an A/D converter that performs A/D conversion with the image signal output from the analog processor; a holding circuit that holds digital image data output from the A/D converter; a timing generator that, based on a first reference clock, generates a plurality of clocks and outputs the clocks to at least one of the analog processor and the A/D converter; and a spread spectrum modulation circuit that performs spread spectrum modulation with the first reference clock and outputs a resultant clock that has been subject to the spread spectrum modulation as a modulated clock to the holding circuit; wherein the holding circuit holds the digital image data from the A/D converter based on the modulated clock output from the spread spectrum modulation circuit.