12 results about "Processor time" patented technology

The invention relates to the technical field of computer security, in particular to a security isolation method for an edge computing node of the Internet of Things, which comprises the following steps of: identifying a trust domain in the edge computing node of the Internet of Things, defining a sensitive data source, and generating a sensitive data identifier set, and based on the sensitive data identifier set, planning minimum central processing unit time and maximum memory bandwidth for each isolation domain to form an isolation domain resource limit, and establishing initial security isolation configuration. According to the method, the identification mechanism based on the sensitive data identification set is introduced into the edge computing node of the Internet of Things, the definition of the trust domain can be realized, and the resource limit is constructed in combination with the minimum central processing unit time and the maximum memory bandwidth of each isolation domain, so that the basic distribution mode of computing resources is restrained, and the computing efficiency is improved. And resources are prevented from being occupied by high-frequency low-priority tasks. After a data entry is positioned on a system level and stain marks are applied according to sensitive attributes, sensitive data images have identifiable features on a memory level.

The invention relates to the technical field of serial port communication, and discloses a serial port-based DSP (Digital Signal Processor) application program online upgrading method, which comprises the following steps of: 1, designing an upgrading program to be used as a program which is firstly operated after a DSP is powered on, judging whether upgrading is needed or not, and executing an upgrading process, and 2, designing a circuit with a power-off detection function and integrating the circuit in a power management module of the DPS host. According to the method, smaller data structures and algorithms are selected from data structures of arrays, linked lists, stacks and queues and linear search algorithms to design the upgrading program, so that memory occupation can be reduced, and in the upgrading process, upgrading program codes are divided into small data packets which are sent to a buffer area of an RAM in batches; the data volume transmitted each time can be ensured to be controllable, the pressure on system resources can be reduced by sending the data packets in batches, and particularly on equipment with limited resources, the situation that a large amount of memory or processor time is occupied at a time is avoided.

The embodiment of the invention discloses a task processing method and device, equipment, a computer storage medium and a computer program product, and the method comprises the steps: carrying out the grouping processing of to-be-processed training tasks for model training, obtaining a plurality of groups of training sub-tasks, and distributing a corresponding service node for each group of training sub-tasks; executing the plurality of groups of training sub-tasks in a parallel processing mode through the plurality of service nodes corresponding to each group of training sub-tasks; if a target service node fault occurs in execution of the multiple groups of training sub-tasks, stopping execution of the target group training sub-task where the target service node is located; determining a standby service node, and executing unexecuted training subtasks in the target group of training subtasks through the standby service node and other service nodes; and the other service nodes are service nodes except the target service node in the service nodes corresponding to the target group training sub-task, so that the problem that a large amount of processor time is wasted is solved.

A processor times a capped time that is a duration time of a capped state of a nozzle unit when the ink is not being ejected, and an open time that is a duration time of an open state of the nozzle unit when the ink is not being ejected. The processor sets a number of times parameter relating to a number of times that a meniscus of the ink in a plurality of nozzles of the nozzle unit is oscillated according to the capped time and the open time. The processor generates the meniscus oscillation of the ink a number of times corresponding to the number of times parameter from when a request for image formation is received until when the image formation is started.

Embodiments of the present disclosure provide a processor time scheduling and container creation method, a device, a medium, and a program product. In the embodiments of the present disclosure, in order to implement flexible processor bandwidth control in a secure container, by means of extending a virtual processor core allocated to a conventional secure container, a constraint requiring one-to-one correspondence between usage duration (Quota) in the conventional secure container and virtual processor cores is broken, and the secure container can use the extended virtual processor core to consume unconsumed duration accumulated by a historical scheduling cycle under a high load, so that flexible processor bandwidth control is implemented, thereby meeting burst load demand and improving service quality of the secure container.

The invention provides a self-adaptive clock implementation method and system for developing a time sequence margin of a reconfigurable processor. The method comprises the steps that S1, a simulation tool conducts dynamic time sequence analysis on an application program executed by the reconfigurable processor to obtain delay information; the delay information is sent to a compiler, the compiler carries out data flow diagram generation and mapping optimization on the application program, meanwhile, the corresponding delay information is coded into configuration information, and a working load factor is obtained based on the coded configuration information; and S2, inputting the working load factor and a PVT factor generated by the PVT detection module into a phase selection module together, selecting one of the multi-phase clocks generated by the multi-phase clock generation module by the phase selection module according to the working load factor and the PVT factor as an adaptive clock, and providing the adaptive clock to the reconfigurable processor.

The invention relates to the technical field of resource allocation, in particular to a wind turbine generator state monitoring method based on edge computing, which comprises the following steps of: acquiring a vibration data block of a wind turbine generator, computing time domain kurtosis, comparing the kurtosis with a preset warning line and an alarm line, judging a scheduling mode of a monitoring task and generating an activation instruction, and calling a fast Fourier-K transform processing data block based on an instruction, identifying a main frequency band center frequency with the highest energy, querying a frequency-time slice mapping table in a kernel based on the frequency, and adjusting an execution time upper limit of a monitoring task. According to the method, the vibration kurtosis is analyzed through edge nodes, the monitoring frequency is dynamically adjusted according to the health state, state-driven monitoring is achieved, when fault signs are recognized, a main frequency band is extracted through fast Fourier transform, the center frequency is used for adjusting processor time slices, computing resources are matched for fine diagnosis, and the resource efficiency and the response speed are improved; and efficient scheduling of computing power and sensitive response of operation and maintenance are realized.

Embodiments of the present application disclose a task processing method, device and equipment, a computer storage medium and a computer program product, which comprise: performing grouping processing on a to-be-processed training task for model training to obtain multiple groups of training subtasks, and assigning each group of training subtasks a corresponding service node; executing the multiple groups of training subtasks in a parallel processing manner through the multiple service nodes corresponding to each group of training subtasks; stopping execution of a target group of training subtasks in which a target service node is located when a fault occurs in the target service node during execution of the multiple groups of training subtasks; determining a backup service node, and executing unexecuted training subtasks in the target group of training subtasks through the backup service node and other service nodes; the other service nodes are service nodes corresponding to the target group of training subtasks except the target service node, and the problem of a large amount of waste of processor time is solved.

Improving Coordinated Sampled Listening (CSL) stability using calculated CSL packet transmission time delay in processor-based devices is disclosed herein. In some aspects, an application processor device determines an application processor time base value, and receives a first CSL packet comprising a first time differential value between a radio processor time base value and a reception time of the first CSL packet by a radio processor device. The application processor device calculates a second time differential value between the application processor time base value and a reception time of the first CSL packet by the application processor device, and calculates a delay value using the first and second time differential values. The application processor device uses the delay value to calculate a reception timestamp value and a CSL channel sampling window value, and transmits a second CSL packet directed at a time indicated by the CSL channel sampling window value.

This invention provides a method for secure startup and end-to-end authentication of DCS controllers based on trusted computing, relating to the field of industrial control system security. The method includes performing layer-by-layer integrity measurements on the controller's startup firmware and software components to generate a set of hierarchical measurement values, and periodically performing memory checks during operation to generate runtime measurement values. Deviation measurements are then calculated and encapsulated as bi-state credentials. Simultaneously, relevant measurement values ​​are linked by a timestamp-based chained hash to generate an evidence chain. During inter-controller communication, credentials and evidence chains are exchanged. By calculating negotiated measurements and adaptive thresholds, resource allocation ratios are dynamically determined, and processor time slices and memory space are allocated to and executed for peer control commands. This invention achieves dynamic trusted authentication and resource isolation throughout the entire lifecycle of the controller from startup to operation, improving the overall security of the DCS system.

A host receives a request to instantiate a plurality of containers, such as a host of a KUBERNETES pod. The host instantiates application instances of the plurality of containers within a single virtual machine without instantiating the plurality of containers. The CRI for the containers is a container emulator that maintains simulated states for the containers and responds to instructions for the containers. The container emulator performs binding of application instances to processors and the monitoring and reporting of usage information, such as processor time.

This invention provides a laboratory safety self-control method and system for fault self-diagnosis. The method includes: S1 periodically and actively generating health labels through self-checks; S2 dividing the time slice of a single processor into execution time slots and self-test time slots, calculating the CRC signature of key data in the execution time slot, executing test vectors and comparing them with historical signatures in the self-test time slot, and locking the output to a safe state via independent hardwired connection in case of a fault; S3 based on incremental causal graph and online parameter learning, collecting samples using fault labels, updating the conditional probability table through online EM, automatically expanding the causal graph structure through normalized mutual information, and outputting the fault type and confidence level using confidence propagation; S4 actuator closed-loop feedback and hardwired bypass protection; S5 dynamic reconstruction degradation fault tolerance; S6 emergency shutdown and solidification. This invention achieves high-coverage fault detection with a single processor, eliminates blind spots of common faults, and simultaneously achieves small-sample adaptive and accurate fault reasoning, significantly improving system reliability and intelligence.